aarch64: Rework reporting of failed register checks
There are many opcode table entries that share the same mnemonic.
Trying to parse an invalid assembly line will trigger an error for
each of these entries, but the specific error might vary from one
entry to another, depending on the exact nature of the problem.
GAS has quite an elaborate system for picking the most appropriate
error out of all the failed matches. And in many cases it works well.
However, one of the limitations is that the error is always reported
against a single opcode table entry. If that table entry isn't the
one that the user intended to use, then the error can end up being
overly specific.
This is particularly true if an instruction has a typoed register
name, or uses a type of register that is not accepted by any
opcode table entry. For example, one of the expected error
matches for an attempted SVE2 instruction is:
Error: operand 1 must be a SIMD scalar register -- `addp z32\.s,p0/m,z32\.s,z0\.s'
even though the hypothetical user was presumably attempting to use
the SVE form of ADDP rather than the Advanced SIMD one. There are
many other instances of this in the testsuite.
The problem becomes especially acute with SME2, since many SME2
instructions reuse existing mnemonics. This could lead to us
reporting an SME-related error against a non-SME instruction,
or a non-SME-related error against an SME instruction.
This patch tries to improve things by collecting together all
the register types that an opcode table entry expected for a
given operand. It also records what kind of register was
actually seen, if any. It then tries to summarise all this
in a more directed way, falling back to a generic error if
the combination defies a neat summary.
The patch includes tests for all new messages except REG_TYPE_ZA,
which only triggers with SME2.
To test this, I created an assembly file that contained the cross
product of all known mnemonics and one example from each register
class. I then looked for cases where the new routines fell back on the
generic errors ("expected a register" or "unexpected register type").
I locally added dummy messages for each one until there were no
more hits. The patch adds a specimen instruction to diagnostics.s
for each of these combinations. In each case, the combination didn't
seem like something that could be summarised in a natural way, so the
generic messages seemed better. There's always going to be an element
of personal taste around this kind of thing though.
Adding more register types made 1<<REG_TYPE_MAX exceed the range
of the type, but we don't actually need/want 1<<REG_TYPE_MAX.
This commit is contained in:
Richard Sandiford
parent
405f0c4131
commit
e426521ed1
@ -161,6 +161,32 @@ static aarch64_instruction inst;
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static bool parse_operands (char *, const aarch64_opcode *);
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static bool programmer_friendly_fixup (aarch64_instruction *);
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/* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
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data fields contain the following information:
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data[0].i:
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A mask of register types that would have been acceptable as bare
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operands, outside of a register list. In addition, SEF_DEFAULT_ERROR
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is set if a general parsing error occured for an operand (that is,
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an error not related to registers, and having no error string).
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data[1].i:
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A mask of register types that would have been acceptable inside
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a register list. In addition, SEF_IN_REGLIST is set if the
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operand contained a '{' and if we got to the point of trying
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to parse a register inside a list.
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data[2].i:
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The mask associated with the register that was actually seen, or 0
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if none. A nonzero value describes a register inside a register
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list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
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register.
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The idea is that stringless errors from multiple opcode templates can
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be ORed together to give a summary of the available alternatives. */
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#define SEF_DEFAULT_ERROR (1U << 31)
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#define SEF_IN_REGLIST (1U << 31)
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/* Diagnostics inline function utilities.
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These are lightweight utilities which should only be called by parse_operands
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@ -212,6 +238,14 @@ static inline void
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set_default_error (void)
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{
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set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
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inst.parsing_error.data[0].i = SEF_DEFAULT_ERROR;
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}
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static inline void
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set_expected_error (unsigned int flags)
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{
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set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
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inst.parsing_error.data[0].i = flags;
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}
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static inline void
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@ -317,17 +351,25 @@ struct reloc_entry
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MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
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| REG_TYPE(SP_32) | REG_TYPE(SP_64) \
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| REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
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/* Any vector register. */ \
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MULTI_REG_TYPE(VZ, REG_TYPE(VN) | REG_TYPE(ZN)) \
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/* An SVE vector or predicate register. */ \
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MULTI_REG_TYPE(ZP, REG_TYPE(ZN) | REG_TYPE(PN)) \
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/* Any vector or predicate register. */ \
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MULTI_REG_TYPE(VZP, REG_TYPE(VN) | REG_TYPE(ZN) | REG_TYPE(PN)) \
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/* The whole of ZA or a single tile. */ \
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MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT)) \
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/* A horizontal or vertical slice of a ZA tile. */ \
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MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV)) \
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/* Pseudo type to mark the end of the enumerator sequence. */ \
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BASIC_REG_TYPE(MAX)
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END_REG_TYPE(MAX)
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#undef BASIC_REG_TYPE
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#define BASIC_REG_TYPE(T) REG_TYPE_##T,
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#undef MULTI_REG_TYPE
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#define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
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#undef END_REG_TYPE
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#define END_REG_TYPE(T) BASIC_REG_TYPE(T)
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/* Register type enumerators. */
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typedef enum aarch64_reg_type_
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@ -342,6 +384,8 @@ typedef enum aarch64_reg_type_
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#define REG_TYPE(T) (1 << REG_TYPE_##T)
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#undef MULTI_REG_TYPE
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#define MULTI_REG_TYPE(T,V) V,
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#undef END_REG_TYPE
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#define END_REG_TYPE(T) 0
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/* Structure for a hash table entry for a register. */
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typedef struct
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@ -361,84 +405,129 @@ static const unsigned reg_type_masks[] =
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#undef BASIC_REG_TYPE
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#undef REG_TYPE
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#undef MULTI_REG_TYPE
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#undef END_REG_TYPE
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#undef AARCH64_REG_TYPES
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/* Diagnostics used when we don't get a register of the expected type.
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Note: this has to synchronized with aarch64_reg_type definitions
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above. */
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static const char *
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get_reg_expected_msg (aarch64_reg_type reg_type)
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{
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const char *msg;
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/* We expected one of the registers in MASK to be specified. If a register
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of some kind was specified, SEEN is a mask that contains that register,
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otherwise it is zero.
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switch (reg_type)
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{
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case REG_TYPE_R_32:
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msg = N_("integer 32-bit register expected");
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break;
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case REG_TYPE_R_64:
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msg = N_("integer 64-bit register expected");
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break;
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case REG_TYPE_R_N:
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msg = N_("integer register expected");
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break;
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case REG_TYPE_R64_SP:
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msg = N_("64-bit integer or SP register expected");
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break;
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case REG_TYPE_SVE_BASE:
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msg = N_("base register expected");
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break;
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case REG_TYPE_R_Z:
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msg = N_("integer or zero register expected");
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break;
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case REG_TYPE_SVE_OFFSET:
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msg = N_("offset register expected");
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break;
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case REG_TYPE_R_SP:
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msg = N_("integer or SP register expected");
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break;
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case REG_TYPE_R_Z_SP:
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msg = N_("integer, zero or SP register expected");
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break;
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case REG_TYPE_FP_B:
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msg = N_("8-bit SIMD scalar register expected");
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break;
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case REG_TYPE_FP_H:
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msg = N_("16-bit SIMD scalar or floating-point half precision "
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"register expected");
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break;
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case REG_TYPE_FP_S:
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msg = N_("32-bit SIMD scalar or floating-point single precision "
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"register expected");
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break;
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case REG_TYPE_FP_D:
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msg = N_("64-bit SIMD scalar or floating-point double precision "
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"register expected");
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break;
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case REG_TYPE_FP_Q:
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msg = N_("128-bit SIMD scalar or floating-point quad precision "
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"register expected");
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break;
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case REG_TYPE_R_Z_BHSDQ_V:
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case REG_TYPE_R_Z_SP_BHSDQ_VZP:
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msg = N_("register expected");
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break;
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case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
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msg = N_("SIMD scalar or floating-point register expected");
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break;
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case REG_TYPE_VN: /* any V reg */
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msg = N_("vector register expected");
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break;
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case REG_TYPE_ZN:
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msg = N_("SVE vector register expected");
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break;
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case REG_TYPE_PN:
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msg = N_("SVE predicate register expected");
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break;
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default:
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as_fatal (_("invalid register type %d"), reg_type);
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}
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return msg;
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If it is possible to provide a relatively pithy message that describes
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the error exactly, return a string that does so, reporting the error
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against "operand %d". Return null otherwise.
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From a QoI perspective, any REG_TYPE_* that is passed as the first
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argument to set_expected_reg_error should generally have its own message.
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Providing messages for combinations of such REG_TYPE_*s can be useful if
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it is possible to summarize the combination in a relatively natural way.
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On the other hand, it seems better to avoid long lists of unrelated
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things. */
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static const char *
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get_reg_expected_msg (unsigned int mask, unsigned int seen)
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{
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/* First handle messages that use SEEN. */
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if ((mask & reg_type_masks[REG_TYPE_ZAT])
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&& (seen & reg_type_masks[REG_TYPE_ZATHV]))
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return N_("expected an unsuffixed ZA tile at operand %d");
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if ((mask & reg_type_masks[REG_TYPE_ZATHV])
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&& (seen & reg_type_masks[REG_TYPE_ZAT]))
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return N_("missing horizontal or vertical suffix at operand %d");
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if ((mask & reg_type_masks[REG_TYPE_ZA])
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&& (seen & (reg_type_masks[REG_TYPE_ZAT]
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| reg_type_masks[REG_TYPE_ZATHV])))
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return N_("expected 'za' rather than a ZA tile at operand %d");
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/* Integer, zero and stack registers. */
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if (mask == reg_type_masks[REG_TYPE_R_64])
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return N_("expected a 64-bit integer register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_R_Z])
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return N_("expected an integer or zero register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_R_SP])
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return N_("expected an integer or stack pointer register at operand %d");
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/* Floating-point and SIMD registers. */
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if (mask == reg_type_masks[REG_TYPE_BHSDQ])
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return N_("expected a scalar SIMD or floating-point register"
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" at operand %d");
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if (mask == reg_type_masks[REG_TYPE_VN])
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return N_("expected an Advanced SIMD vector register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZN])
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return N_("expected an SVE vector register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_PN])
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return N_("expected an SVE predicate register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_VZ])
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return N_("expected a vector register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZP])
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return N_("expected an SVE vector or predicate register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_VZP])
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return N_("expected a vector or predicate register at operand %d");
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/* ZA-related registers. */
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if (mask == reg_type_masks[REG_TYPE_ZA])
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return N_("expected a ZA array vector at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZA_ZAT])
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return N_("expected 'za' or a ZA tile at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZAT])
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return N_("expected a ZA tile at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZATHV])
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return N_("expected a ZA tile slice at operand %d");
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/* Integer and vector combos. */
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if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VN]))
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return N_("expected an integer register or Advanced SIMD vector register"
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" at operand %d");
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if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_ZN]))
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return N_("expected an integer register or SVE vector register"
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" at operand %d");
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if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZ]))
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return N_("expected an integer or vector register at operand %d");
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if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_PN]))
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return N_("expected an integer or predicate register at operand %d");
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if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZP]))
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return N_("expected an integer, vector or predicate register"
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" at operand %d");
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/* SVE and SME combos. */
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if (mask == (reg_type_masks[REG_TYPE_ZN] | reg_type_masks[REG_TYPE_ZATHV]))
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return N_("expected an SVE vector register or ZA tile slice"
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" at operand %d");
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return NULL;
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}
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/* Record that we expected a register of type TYPE but didn't see one.
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REG is the register that we actually saw, or null if we didn't see a
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recognized register. FLAGS is SEF_IN_REGLIST if we are parsing the
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contents of a register list, otherwise it is zero. */
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static inline void
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set_expected_reg_error (aarch64_reg_type type, const reg_entry *reg,
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unsigned int flags)
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{
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assert (flags == 0 || flags == SEF_IN_REGLIST);
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set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
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if (flags & SEF_IN_REGLIST)
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inst.parsing_error.data[1].i = reg_type_masks[type] | flags;
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else
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inst.parsing_error.data[0].i = reg_type_masks[type];
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if (reg)
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inst.parsing_error.data[2].i = reg_type_masks[reg->type];
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}
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/* Record that we expected a register list containing registers of type TYPE,
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but didn't see the opening '{'. If we saw a register instead, REG is the
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register that we saw, otherwise it is null. */
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static inline void
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set_expected_reglist_error (aarch64_reg_type type, const reg_entry *reg)
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{
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set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
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inst.parsing_error.data[1].i = reg_type_masks[type];
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if (reg)
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inst.parsing_error.data[2].i = reg_type_masks[reg->type];
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}
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/* Some well known registers that we refer to directly elsewhere. */
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@ -1092,6 +1181,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
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struct vector_type_el atype;
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struct vector_type_el parsetype;
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bool is_typed_vecreg = false;
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unsigned int err_flags = (flags & PTR_IN_REGLIST) ? SEF_IN_REGLIST : 0;
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atype.defined = 0;
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atype.type = NT_invtype;
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@ -1108,7 +1198,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
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else if (flags & PTR_GOOD_MATCH)
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set_fatal_syntax_error (NULL);
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else
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set_default_error ();
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set_expected_reg_error (type, reg, err_flags);
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return NULL;
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}
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@ -1118,7 +1208,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
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if (flags & PTR_GOOD_MATCH)
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set_fatal_syntax_error (NULL);
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else
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set_default_error ();
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set_expected_reg_error (type, reg, err_flags);
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return NULL;
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}
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type = reg->type;
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@ -1275,7 +1365,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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if (*str != '{')
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{
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set_syntax_error (_("expecting {"));
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set_expected_reglist_error (type, parse_reg (&str));
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return PARSE_FAIL;
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}
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str++;
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@ -3612,7 +3702,7 @@ parse_shifter_operand (char **str, aarch64_opnd_info *operand,
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if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
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{
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set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
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set_expected_reg_error (REG_TYPE_R_Z, reg, 0);
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return false;
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}
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@ -4110,7 +4200,7 @@ parse_x0_to_x30 (char **str, aarch64_opnd_info *operand)
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const reg_entry *reg = parse_reg (str);
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if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R_64))
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{
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set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
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set_expected_reg_error (REG_TYPE_R_64, reg, 0);
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return false;
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}
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operand->reg.regno = reg->number;
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@ -4509,7 +4599,7 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
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{
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if (!skip_past_char (str, '{'))
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{
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set_syntax_error (_("expected '{'"));
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set_expected_reglist_error (REG_TYPE_ZATHV, parse_reg (str));
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return false;
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}
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@ -4783,17 +4873,14 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
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#define po_reg_or_fail(regtype) do { \
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reg = aarch64_reg_parse (&str, regtype, NULL); \
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if (!reg) \
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{ \
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set_default_error (); \
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goto failure; \
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} \
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goto failure; \
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} while (0)
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#define po_int_fp_reg_or_fail(reg_type) do { \
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reg = parse_reg (&str); \
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if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
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{ \
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set_default_error (); \
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set_expected_reg_error (reg_type, reg, 0); \
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goto failure; \
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} \
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info->reg.regno = reg->number; \
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@ -5389,6 +5476,64 @@ output_info (const char *format, ...)
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(void) putc ('\n', stderr);
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}
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/* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
|
||||
relates to registers or register lists. If so, return a string that
|
||||
reports the error against "operand %d", otherwise return null. */
|
||||
|
||||
static const char *
|
||||
get_reg_error_message (const aarch64_operand_error *detail)
|
||||
{
|
||||
/* Handle the case where we found a register that was expected
|
||||
to be in a register list outside of a register list. */
|
||||
if ((detail->data[1].i & detail->data[2].i) != 0
|
||||
&& (detail->data[1].i & SEF_IN_REGLIST) == 0)
|
||||
return _("missing braces at operand %d");
|
||||
|
||||
/* If some opcodes expected a register, and we found a register,
|
||||
complain about the difference. */
|
||||
if (detail->data[2].i)
|
||||
{
|
||||
unsigned int expected = (detail->data[1].i & SEF_IN_REGLIST
|
||||
? detail->data[1].i & ~SEF_IN_REGLIST
|
||||
: detail->data[0].i & ~SEF_DEFAULT_ERROR);
|
||||
const char *msg = get_reg_expected_msg (expected, detail->data[2].i);
|
||||
if (!msg)
|
||||
msg = N_("unexpected register type at operand %d");
|
||||
return msg;
|
||||
}
|
||||
|
||||
/* Handle the case where we got to the point of trying to parse a
|
||||
register within a register list, but didn't find a known register. */
|
||||
if (detail->data[1].i & SEF_IN_REGLIST)
|
||||
{
|
||||
unsigned int expected = detail->data[1].i & ~SEF_IN_REGLIST;
|
||||
const char *msg = get_reg_expected_msg (expected, 0);
|
||||
if (!msg)
|
||||
msg = _("invalid register list at operand %d");
|
||||
return msg;
|
||||
}
|
||||
|
||||
/* Punt if register-related problems weren't the only errors. */
|
||||
if (detail->data[0].i & SEF_DEFAULT_ERROR)
|
||||
return NULL;
|
||||
|
||||
/* Handle the case where the only acceptable things are registers. */
|
||||
if (detail->data[1].i == 0)
|
||||
{
|
||||
const char *msg = get_reg_expected_msg (detail->data[0].i, 0);
|
||||
if (!msg)
|
||||
msg = _("expected a register at operand %d");
|
||||
return msg;
|
||||
}
|
||||
|
||||
/* Handle the case where the only acceptable things are register lists,
|
||||
and there was no opening '{'. */
|
||||
if (detail->data[0].i == 0)
|
||||
return _("expected '{' at operand %d");
|
||||
|
||||
return _("expected a register or register list at operand %d");
|
||||
}
|
||||
|
||||
/* Output one operand error record. */
|
||||
|
||||
static void
|
||||
@ -5402,6 +5547,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
|
||||
|
||||
typedef void (*handler_t)(const char *format, ...);
|
||||
handler_t handler = detail->non_fatal ? as_warn : as_bad;
|
||||
const char *msg = detail->error;
|
||||
|
||||
switch (detail->kind)
|
||||
{
|
||||
@ -5422,18 +5568,31 @@ output_operand_error_record (const operand_error_record *record, char *str)
|
||||
break;
|
||||
|
||||
case AARCH64_OPDE_SYNTAX_ERROR:
|
||||
if (!msg && idx >= 0)
|
||||
{
|
||||
msg = get_reg_error_message (detail);
|
||||
if (msg)
|
||||
{
|
||||
char *full_msg = xasprintf (msg, idx + 1);
|
||||
handler (_("%s -- `%s'"), full_msg, str);
|
||||
free (full_msg);
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Fall through. */
|
||||
|
||||
case AARCH64_OPDE_RECOVERABLE:
|
||||
case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
|
||||
case AARCH64_OPDE_OTHER_ERROR:
|
||||
/* Use the prepared error message if there is, otherwise use the
|
||||
operand description string to describe the error. */
|
||||
if (detail->error != NULL)
|
||||
if (msg != NULL)
|
||||
{
|
||||
if (idx < 0)
|
||||
handler (_("%s -- `%s'"), detail->error, str);
|
||||
handler (_("%s -- `%s'"), msg, str);
|
||||
else
|
||||
handler (_("%s at operand %d -- `%s'"),
|
||||
detail->error, idx + 1, str);
|
||||
msg, idx + 1, str);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -5554,11 +5713,11 @@ output_operand_error_record (const operand_error_record *record, char *str)
|
||||
case AARCH64_OPDE_OUT_OF_RANGE:
|
||||
if (detail->data[0].i != detail->data[1].i)
|
||||
handler (_("%s out of range %d to %d at operand %d -- `%s'"),
|
||||
detail->error ? detail->error : _("immediate value"),
|
||||
msg ? msg : _("immediate value"),
|
||||
detail->data[0].i, detail->data[1].i, idx + 1, str);
|
||||
else
|
||||
handler (_("%s must be %d at operand %d -- `%s'"),
|
||||
detail->error ? detail->error : _("immediate value"),
|
||||
msg ? msg : _("immediate value"),
|
||||
detail->data[0].i, idx + 1, str);
|
||||
break;
|
||||
|
||||
@ -5600,8 +5759,6 @@ output_operand_error_record (const operand_error_record *record, char *str)
|
||||
static void
|
||||
output_operand_error_report (char *str, bool non_fatal_only)
|
||||
{
|
||||
int largest_error_pos;
|
||||
const char *msg = NULL;
|
||||
enum aarch64_operand_error_kind kind;
|
||||
operand_error_record *curr;
|
||||
operand_error_record *head = operand_error_report.head;
|
||||
@ -5633,7 +5790,17 @@ output_operand_error_report (char *str, bool non_fatal_only)
|
||||
for (curr = head; curr != NULL; curr = curr->next)
|
||||
{
|
||||
gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
|
||||
DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
|
||||
if (curr->detail.kind == AARCH64_OPDE_SYNTAX_ERROR)
|
||||
{
|
||||
DEBUG_TRACE ("\t%s [%x, %x, %x]",
|
||||
operand_mismatch_kind_names[curr->detail.kind],
|
||||
curr->detail.data[0].i, curr->detail.data[1].i,
|
||||
curr->detail.data[2].i);
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
|
||||
}
|
||||
if (operand_error_higher_severity_p (curr->detail.kind, kind)
|
||||
&& (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))
|
||||
kind = curr->detail.kind;
|
||||
@ -5642,7 +5809,6 @@ output_operand_error_report (char *str, bool non_fatal_only)
|
||||
gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);
|
||||
|
||||
/* Pick up one of errors of KIND to report. */
|
||||
largest_error_pos = -2; /* Index can be -1 which means unknown index. */
|
||||
for (curr = head; curr != NULL; curr = curr->next)
|
||||
{
|
||||
/* If we don't want to print non-fatal errors then don't consider them
|
||||
@ -5654,13 +5820,23 @@ output_operand_error_report (char *str, bool non_fatal_only)
|
||||
mismatching operand index. In the case of multiple errors with
|
||||
the equally highest operand index, pick up the first one or the
|
||||
first one with non-NULL error message. */
|
||||
if (curr->detail.index > largest_error_pos
|
||||
|| (curr->detail.index == largest_error_pos && msg == NULL
|
||||
&& curr->detail.error != NULL))
|
||||
if (!record || curr->detail.index > record->detail.index)
|
||||
record = curr;
|
||||
else if (curr->detail.index == record->detail.index
|
||||
&& !record->detail.error)
|
||||
{
|
||||
largest_error_pos = curr->detail.index;
|
||||
record = curr;
|
||||
msg = record->detail.error;
|
||||
if (curr->detail.error)
|
||||
record = curr;
|
||||
else if (kind == AARCH64_OPDE_SYNTAX_ERROR)
|
||||
{
|
||||
record->detail.data[0].i |= curr->detail.data[0].i;
|
||||
record->detail.data[1].i |= curr->detail.data[1].i;
|
||||
record->detail.data[2].i |= curr->detail.data[2].i;
|
||||
DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
|
||||
operand_mismatch_kind_names[kind],
|
||||
curr->detail.data[0].i, curr->detail.data[1].i,
|
||||
curr->detail.data[2].i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -5675,9 +5851,9 @@ output_operand_error_report (char *str, bool non_fatal_only)
|
||||
if (non_fatal_only && !record)
|
||||
return;
|
||||
|
||||
gas_assert (largest_error_pos != -2 && record != NULL);
|
||||
gas_assert (record);
|
||||
DEBUG_TRACE ("Pick up error kind %s to report",
|
||||
operand_mismatch_kind_names[record->detail.kind]);
|
||||
operand_mismatch_kind_names[kind]);
|
||||
|
||||
/* Output. */
|
||||
output_operand_error_record (record, str);
|
||||
@ -6299,10 +6475,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
|
||||
vector_reg:
|
||||
reg = aarch64_reg_parse (&str, reg_type, &vectype);
|
||||
if (!reg)
|
||||
{
|
||||
first_error (_(get_reg_expected_msg (reg_type)));
|
||||
goto failure;
|
||||
}
|
||||
goto failure;
|
||||
if (vectype.defined & NTA_HASINDEX)
|
||||
goto failure;
|
||||
|
||||
@ -6325,10 +6498,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
|
||||
case AARCH64_OPND_VnD1:
|
||||
reg = aarch64_reg_parse (&str, REG_TYPE_VN, &vectype);
|
||||
if (!reg)
|
||||
{
|
||||
set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
|
||||
goto failure;
|
||||
}
|
||||
goto failure;
|
||||
if (vectype.type != NT_d || vectype.index != 1)
|
||||
{
|
||||
set_fatal_syntax_error
|
||||
@ -6361,10 +6531,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
|
||||
vector_reg_index:
|
||||
reg = aarch64_reg_parse (&str, reg_type, &vectype);
|
||||
if (!reg)
|
||||
{
|
||||
first_error (_(get_reg_expected_msg (reg_type)));
|
||||
goto failure;
|
||||
}
|
||||
goto failure;
|
||||
if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
|
||||
goto failure;
|
||||
|
||||
@ -6392,10 +6559,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
|
||||
{
|
||||
reg = aarch64_reg_parse (&str, reg_type, &vectype);
|
||||
if (!reg)
|
||||
{
|
||||
first_error (_(get_reg_expected_msg (reg_type)));
|
||||
goto failure;
|
||||
}
|
||||
goto failure;
|
||||
info->reglist.first_regno = reg->number;
|
||||
info->reglist.num_regs = 1;
|
||||
}
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
[^:]+: Assembler messages:
|
||||
[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h X0,Q0,V1.2D'
|
||||
[^:]+:[0-9]+: Error: expected a scalar SIMD or floating-point register at operand 1 -- `sha512h X0,Q0,V1.2D'
|
||||
[^:]+:[0-9]+: Error: operand mismatch -- `sha512h Q0,Q1,V2.16B'
|
||||
[^:]+:[0-9]+: Info: did you mean this\?
|
||||
[^:]+:[0-9]+: Info: sha512h q0, q1, v2.2d
|
||||
[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h2 X0,Q0,V1.2D'
|
||||
[^:]+:[0-9]+: Error: expected a scalar SIMD or floating-point register at operand 1 -- `sha512h2 X0,Q0,V1.2D'
|
||||
[^:]+:[0-9]+: Error: operand mismatch -- `sha512h2 Q0,Q1,V2.16B'
|
||||
[^:]+:[0-9]+: Info: did you mean this\?
|
||||
[^:]+:[0-9]+: Info: sha512h2 q0, q1, v2.2d
|
||||
@ -11,7 +11,7 @@
|
||||
[^:]+:[0-9]+: Info: did you mean this\?
|
||||
[^:]+:[0-9]+: Info: sha512su0 v1.2d, v2.2d
|
||||
[^:]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `sha512su0 V0,V2.2D'
|
||||
[^:]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sha512su1 X0,X1,X2'
|
||||
[^:]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 1 -- `sha512su1 X0,X1,X2'
|
||||
[^:]+:[0-9]+: Error: operand mismatch -- `sha512su1 V1.2D,V2.16B,V2.2D'
|
||||
[^:]+:[0-9]+: Info: did you mean this\?
|
||||
[^:]+:[0-9]+: Info: sha512su1 v1.2d, v2.2d, v2.2d
|
||||
|
||||
@ -51,7 +51,7 @@
|
||||
[^:]*:53: Error: invalid floating-point constant at operand 2 -- `fmov s3,1.01'
|
||||
[^:]*:54: Error: invalid floating-point constant at operand 2 -- `fmov d3,1.01'
|
||||
[^:]*:55: Error: immediate zero expected at operand 2 -- `fcmp d0,#1.0'
|
||||
[^:]*:56: Error: operand 2 must be a floating-point register -- `fcmp d0,x0'
|
||||
[^:]*:56: Error: expected a scalar SIMD or floating-point register at operand 2 -- `fcmp d0,x0'
|
||||
[^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
|
||||
[^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
|
||||
[^:]*:59: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
|
||||
@ -59,7 +59,7 @@
|
||||
[^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
|
||||
[^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
|
||||
[^:]*:63: Error: shift amount out of range 0 to 63 at operand 2 -- `movz x0,2134,lsl#64'
|
||||
[^:]*:64: Error: operand 1 must be an integer register -- `adds sp,sp,2134,lsl#12'
|
||||
[^:]*:64: Error: expected an integer or zero register at operand 1 -- `adds sp,sp,2134,lsl#12'
|
||||
[^:]*:65: Error: the optional immediate offset can only be 0 at operand 2 -- `ldxrb w2,\[x0,#1\]'
|
||||
[^:]*:66: Error: invalid addressing mode at operand 2 -- `ldrb w0,x1,x2,sxtx'
|
||||
[^:]*:67: Error: invalid shift amount at operand 2 -- `prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
|
||||
@ -98,11 +98,11 @@
|
||||
[^:]*:100: Error: operand 3 must be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
|
||||
[^:]*:101: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
|
||||
[^:]*:102: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
|
||||
[^:]*:106: Error: operand 1 must be an integer register -- `ret kk'
|
||||
[^:]*:106: Error: expected an integer or zero register at operand 1 -- `ret kk'
|
||||
[^:]*:107: Error: immediate operand required at operand 1 -- `clrex x0'
|
||||
[^:]*:108: Error: immediate operand required at operand 1 -- `clrex w0'
|
||||
[^:]*:109: Error: constant expression required at operand 1 -- `clrex kk'
|
||||
[^:]*:110: Error: operand 5 must be an integer register -- `sys #0,c0,c0,#0,kk'
|
||||
[^:]*:110: Error: expected an integer or zero register at operand 5 -- `sys #0,c0,c0,#0,kk'
|
||||
[^:]*:111: Error: unexpected comma before the omitted optional operand at operand 5 -- `sys #0,c0,c0,#0,'
|
||||
[^:]*:113: Error: selected processor does not support `casp w0,w1,w2,w3,\[x4\]'
|
||||
[^:]*:116: Warning: unpredictable load of register pair -- `ldp x0,x0,\[sp\]'
|
||||
@ -186,3 +186,21 @@
|
||||
[^:]*:317: Error: expected a base register at operand 2 -- `ldr x0,\[1\]'
|
||||
[^:]*:318: Error: expected a base register at operand 2 -- `ldr x0,\[\]'
|
||||
[^:]*:319: Error: expected a base register at operand 2 -- `ldr x0,\[,xzr\]'
|
||||
[^:]*:321: Error: expected a vector or predicate register at operand 1 -- `zip2 x1'
|
||||
[^:]*:322: Error: expected an integer register or SVE vector register at operand 1 -- `uxtw d2'
|
||||
[^:]*:323: Error: unexpected register type at operand 1 -- `usra x3'
|
||||
[^:]*:324: Error: unexpected register type at operand 1 -- `ushr z4'
|
||||
[^:]*:325: Error: expected an integer register or Advanced SIMD vector register at operand 1 -- `umull z5'
|
||||
[^:]*:326: Error: expected an integer or vector register at operand 1 -- `umin d6'
|
||||
[^:]*:327: Error: unexpected register type at operand 1 -- `stur v7'
|
||||
[^:]*:328: Error: expected an SVE vector or predicate register at operand 1 -- `sel v8'
|
||||
[^:]*:329: Error: expected an integer, vector or predicate register at operand 1 -- `orn d9'
|
||||
[^:]*:330: Error: unexpected register type at operand 1 -- `frecpx v10'
|
||||
[^:]*:331: Error: expected an integer or predicate register at operand 1 -- `bics z11'
|
||||
[^:]*:332: Error: unexpected register type at operand 1 -- `rev wsp'
|
||||
[^:]*:333: Error: unexpected register type at operand 1 -- `orr b12'
|
||||
[^:]*:334: Error: unexpected register type at operand 1 -- `neg p13'
|
||||
[^:]*:335: Error: unexpected register type at operand 1 -- `fcvtpu za14h'
|
||||
[^:]*:336: Error: unexpected register type at operand 1 -- `fcmlt z15'
|
||||
[^:]*:337: Error: unexpected register type at operand 1 -- `clastb sp'
|
||||
[^:]*:338: Error: unexpected register type at operand 1 -- `ldr sp'
|
||||
|
||||
@ -317,3 +317,22 @@
|
||||
ldr x0, [1]
|
||||
ldr x0, []
|
||||
ldr x0, [,xzr]
|
||||
|
||||
zip2 x1
|
||||
uxtw d2
|
||||
usra x3
|
||||
ushr z4
|
||||
umull z5
|
||||
umin d6
|
||||
stur v7
|
||||
sel v8
|
||||
orn d9
|
||||
frecpx v10
|
||||
bics z11
|
||||
rev wsp
|
||||
orr b12
|
||||
neg p13
|
||||
fcvtpu za14h
|
||||
fcmlt z15
|
||||
clastb sp
|
||||
ldr sp
|
||||
|
||||
@ -25,28 +25,28 @@
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt z32\.s,z0\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalt z0\.s,z32\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlalt z0\.s,z0\.h,z32\.h'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt z0\.s,z0\.h,z0\.h\[8\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalt z0\.s,z0\.h,z8\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalb z0\.s,z0\.h,z32\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb z32\.s,z0\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalb z0\.s,z32\.h,z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlalb z0\.s,z0\.h,z32\.h'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb z0\.s,z0\.h,z0\.h\[8\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalb z0\.s,z0\.h,z8\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot v0\.2s,v1\.4h,v2\.2s\[3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
@ -61,18 +61,18 @@
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.8h
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.4h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.8h
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
|
||||
[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v0\.h\[8\]'
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v16\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
@ -87,8 +87,8 @@
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.h\[0\]
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v0\.h\[8\]'
|
||||
[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v16\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt h0,h1'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
[^:]+: Assembler messages:
|
||||
[^:]+:8: Error: operand 1 must be an integer register -- `fjcvtzs d0,d1'
|
||||
[^:]+:9: Error: operand 1 must be an integer register -- `fjcvtzs s0,d1'
|
||||
[^:]+:8: Error: expected an integer or zero register at operand 1 -- `fjcvtzs d0,d1'
|
||||
[^:]+:9: Error: expected an integer or zero register at operand 1 -- `fjcvtzs s0,d1'
|
||||
[^:]+:10: Error: operand mismatch -- `fjcvtzs x0,d1'
|
||||
[^:]+:11: Error: operand mismatch -- `fjcvtzs w0,s1'
|
||||
[^:]+:12: Error: operand mismatch -- `fjcvtzs w0,h1'
|
||||
[^:]+:13: Error: operand mismatch -- `fjcvtzs w0,q1'
|
||||
[^:]+:14: Error: operand 2 must be a floating-point register -- `fjcvtzs w0,x1'
|
||||
[^:]+:14: Error: expected a scalar SIMD or floating-point register at operand 2 -- `fjcvtzs w0,x1'
|
||||
|
||||
@ -18,38 +18,38 @@
|
||||
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldgm x4,\[x5,#16\]!'
|
||||
[^:]*:[0-9]+: Error: the optional immediate offset can only be 0 at operand 2 -- `stgm x2,\[x3,#16\]'
|
||||
[^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `stgm x4,\[x5,#16\]!'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
|
||||
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
|
||||
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
|
||||
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `gmi x1,x2,sp'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `gmi sp,x2,x3'
|
||||
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `gmi x1,xzr,x3'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `addg xzr,x2,#0,#0'
|
||||
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subg x1,xzr,#0,#0'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `subp sp,x1,x2'
|
||||
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subp x1,xzr,x2'
|
||||
[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subp x1,x2,xzr'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `subps sp,x1,x2'
|
||||
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subps x1,xzr,x2'
|
||||
[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
|
||||
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `irg xzr,x2,x3'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `irg x1,xzr,x3'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 3 -- `irg x1,x2,sp'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 3 -- `gmi x1,x2,sp'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gmi sp,x2,x3'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `gmi x1,xzr,x3'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `addg xzr,x2,#0,#0'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subg x1,xzr,#0,#0'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subp sp,x1,x2'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subp x1,xzr,x2'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subp x1,x2,xzr'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subps sp,x1,x2'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subps x1,xzr,x2'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subps x1,x2,xzr'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `cmpp xzr,x2'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `cmpp x2,xzr'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stg x2,\[xzr,#0\]'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `st2g x2,\[xzr,#0\]!'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzg x2,\[xzr\],#0'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stz2g x2,\[xzr,#0\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stg xzr,\[x2,#0\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `st2g xzr,\[x2,#0\]!'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stzg xzr,\[x2\],#0'
|
||||
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stz2g xzr,\[x2,#0\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stgp sp,x2,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 2 -- `stgp x1,sp,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 3 -- `stgp x0,x0,\[xzr\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `ldg sp,\[x0,#16\]'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldg x0,\[xzr,#16\]'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzgm x0,\[xzr\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stzgm sp,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldgm x0,\[xzr\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgm sp,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `ldgm sp,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stgm x0,\[xzr\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgm sp,\[x3\]'
|
||||
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stgm sp,\[x3\]'
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
[^:]*: Assembler messages:
|
||||
[^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]'
|
||||
[^:]*:6: Error: operand 1 must be an integer register -- `mov r0.w,r1.w'
|
||||
[^:]*:7: Error: operand 2 must be a SIMD vector element -- `dup s0,s1\[3\]'
|
||||
[^:]*:6: Error: expected a register at operand 1 -- `mov r0.w,r1.w'
|
||||
[^:]*:7: Error: expected an Advanced SIMD vector register at operand 2 -- `dup s0,s1\[3\]'
|
||||
|
||||
@ -10,44 +10,44 @@
|
||||
[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,#0\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,xzr\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: operand 3 must be an integer register with writeback -- `cpyfp \[x0\]!,\[x1\]!,x2'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,!x2'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[x31\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[sp\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[zr\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w30\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wsp\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wzr\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[b0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[h0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[s0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[d0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[q0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0.2d\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0.d\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0.d\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[foo\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[x31\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[sp\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[zr\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[w30\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[w0\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wsp\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wzr\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[foo\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,x31!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,sp!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,zr!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,w30!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,w0!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wsp!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wzr!'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,foo!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,!x2'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[x31\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[sp\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[zr\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[w30\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[w0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[wsp\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[wzr\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[b0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[h0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[s0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[d0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[q0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[v0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[v0.2d\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[z0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[z0.d\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[p0\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[p0.d\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[foo\]!,\[x1\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[x31\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[sp\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[zr\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[w30\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x1\]!,\[w0\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[wsp\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[wzr\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x1\]!,\[foo\]!,x2!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,x31!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,sp!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,zr!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,w30!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,w0!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wsp!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wzr!'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,foo!'
|
||||
[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x0\]!,\[x0\]!,x1!'
|
||||
[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x10\]!,\[x1\]!,x10!'
|
||||
[^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x1\]!,\[x30\]!,x30!'
|
||||
@ -56,24 +56,24 @@
|
||||
[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0\],x1!,x2'
|
||||
[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,#0\]!,x1!,x2'
|
||||
[^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,xzr\]!,x1!,x2'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[x31\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[sp\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[zr\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w30\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w0\]!,x1!,x2'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wsp\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wzr\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[foo\]!,x1!,x2'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,x31!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,sp!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,zr!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,w30!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,w0!,x2'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wsp!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wzr!,x1'
|
||||
[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,foo!,x2'
|
||||
[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,sp'
|
||||
[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,wsp'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[x31\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[sp\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[zr\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[w30\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[w0\]!,x1!,x2'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[wsp\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[wzr\]!,x0!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[foo\]!,x1!,x2'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,x31!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,sp!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,zr!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,w30!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x1\]!,w0!,x2'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,wsp!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,wzr!,x1'
|
||||
[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x1\]!,foo!,x2'
|
||||
[^:]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `setp \[x30\]!,x0!,sp'
|
||||
[^:]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `setp \[x30\]!,x0!,wsp'
|
||||
[^:]+:[0-9]+: Error: operand mismatch -- `setp \[x30\]!,x0!,wzr'
|
||||
[^:]+:[0-9]+: Info: did you mean this\?
|
||||
[^:]+:[0-9]+: Info: setp \[x30\]!, x0!, xzr
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.h,p0/m,za2h\.h\[w12,#0\]'
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]'
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]'
|
||||
[^:]*:[0-9]+: Error: operand 3 must be an SME horizontal or vertical vector access register -- `mova z0\.q,p0/m,za16h.q\[w12\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 3 -- `mova z0\.q,p0/m,za16h.q\[w12\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]'
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h'
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `mova za16v\.q\[w12\],p0/m,z0.q'
|
||||
[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s'
|
||||
|
||||
@ -22,11 +22,11 @@
|
||||
[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
|
||||
[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
|
||||
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za_}'
|
||||
[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {za_}'
|
||||
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zaX}'
|
||||
[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zaX}'
|
||||
[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zax}'
|
||||
[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zax}'
|
||||
[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}'
|
||||
[^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}'
|
||||
[^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}'
|
||||
@ -37,5 +37,5 @@
|
||||
[^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.q}'
|
||||
[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za.2d}'
|
||||
[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za0.2d}'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0h\.b}'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0v\.b}'
|
||||
[^:]*:[0-9]+: Error: expected an unsuffixed ZA tile at operand 1 -- `zero {za0h\.b}'
|
||||
[^:]*:[0-9]+: Error: expected an unsuffixed ZA tile at operand 1 -- `zero {za0v\.b}'
|
||||
|
||||
@ -35,10 +35,10 @@
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
|
||||
@ -49,3 +49,10 @@
|
||||
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[x0,x1,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1q {za0v.q\[w12,0\]},p0/z,\[x0,x1,lsl#1\]'
|
||||
[^:]*:[0-9]+: Error: missing immediate offset at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]'
|
||||
[^:]*:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `ld1b {za0.b\[w12,0\]},p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {za.b\[w12,0\]},p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1b za0h.b\[w12,0\],p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1h za0h.h\[w12,0\],p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1w za0h.s\[w12,0\],p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1d za0h.d\[w12,0\],p0/z,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1q za0h.q\[w12,0\],p0/z,\[x0\]'
|
||||
|
||||
@ -50,3 +50,10 @@ ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1, lsl #3]
|
||||
ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1, lsl #4]
|
||||
ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1, lsl #1]
|
||||
ld1q {za0v.q[w12]}, p0/z, [x0, x1, lsl #1]
|
||||
ld1b {za0.b[w12, 0]}, p0/z, [x0]
|
||||
ld1b {za.b[w12, 0]}, p0/z, [x0]
|
||||
ld1b za0h.b[w12, 0], p0/z, [x0]
|
||||
ld1h za0h.h[w12, 0], p0/z, [x0]
|
||||
ld1w za0h.s[w12, 0], p0/z, [x0]
|
||||
ld1d za0h.d[w12, 0], p0/z, [x0]
|
||||
ld1q za0h.q[w12, 0], p0/z, [x0]
|
||||
|
||||
@ -35,10 +35,10 @@
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
|
||||
[^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
|
||||
|
||||
@ -48,3 +48,9 @@
|
||||
[^:]*:[0-9]+: Info: ldr za\[w12, 0\], \[x0\]
|
||||
[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `ldr za/z\[w12,0\],\[x0\]'
|
||||
[^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `ldr za.2b\[w12,0\],\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0\[w12,0\],\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0.b\[w12,0\],\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0h\[w12,0\],\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0h.h\[w12,0\],\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v\[w12,0\],\[x0\]'
|
||||
[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v.s\[w12,0\],\[x0\]'
|
||||
|
||||
@ -45,3 +45,10 @@ ldr za.d[w12, 0], [x0]
|
||||
ldr za.q[w12, 0], [x0]
|
||||
ldr za/z[w12, 0], [x0]
|
||||
ldr za.2b[w12, 0], [x0]
|
||||
|
||||
ldr za0[w12, 0], [x0]
|
||||
ldr za0.b[w12, 0], [x0]
|
||||
ldr za0h[w12, 0], [x0]
|
||||
ldr za0h.h[w12, 0], [x0]
|
||||
ldr za0v[w12, 0], [x0]
|
||||
ldr za0v.s[w12, 0], [x0]
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.s,p2/m,p3/m,z2.d'
|
||||
[^:]*:[0-9]+: Info: did you mean this\?
|
||||
[^:]*:[0-9]+: Info: addha za0.d, p2/m, p3/m, z2.d
|
||||
[^:]*:[0-9]+: Error: expected a ZA tile at operand 1 -- `addha z0.s,p0/m,p1/m,z1.s'
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za8.d,p0/m,p1/m,z1.d'
|
||||
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za15.d,p2/m,p3/m,z2.d'
|
||||
[^:]*:[0-9]+: Error: operand mismatch -- `addha za0.d,p2/m,p3/m,z2.s'
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
addha za4.s, p0/m, p1/m, z1.s
|
||||
addha za15.s, p2/m, p3/m, z2.s
|
||||
addha za0.s, p2/m, p3/m, z2.d
|
||||
addha z0.s, p0/m, p1/m, z1.s
|
||||
|
||||
/* ADDHA 64-bit variant. */
|
||||
addha za8.d, p0/m, p1/m, z1.d
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
[^:]*: Assembler messages:
|
||||
.*: Error: operand 2 must be an SVE predicate register -- `fmov z1,z2'
|
||||
.*: Error: expected an SVE predicate register at operand 2 -- `fmov z1,z2'
|
||||
.*: Error: operand mismatch -- `fmov z1,#1\.0'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: fmov z1\.h, #1\.000000000000000000e\+00
|
||||
@ -126,7 +126,7 @@
|
||||
.*: Info: movprfx z0\.s, p1/m, z1\.s
|
||||
.*: Info: movprfx z0\.d, p1/z, z1\.d
|
||||
.*: Info: movprfx z0\.d, p1/m, z1\.d
|
||||
.*: Error: operand 1 must be an SVE vector register -- `movprfx p0,p1'
|
||||
.*: Error: expected an SVE vector register at operand 1 -- `movprfx p0,p1'
|
||||
.*: Error: operand mismatch -- `ldr p0\.b,\[x1\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ldr p0, \[x1\]
|
||||
@ -184,7 +184,7 @@
|
||||
.*: Info: add z0\.s, z0\.s, #1
|
||||
.*: Info: add z0\.d, z0\.d, #1
|
||||
.*: Error: constant expression required at operand 2 -- `mov z0\.b,z32\.b'
|
||||
.*: Error: operand 2 must be an SVE predicate register -- `mov p0\.b,p16\.b'
|
||||
.*: Error: expected an SVE predicate register at operand 2 -- `mov p0\.b,p16\.b'
|
||||
.*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p8/z,z1\.b,z2\.b'
|
||||
.*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p15/z,z1\.b,z2\.b'
|
||||
.*: Error: operand mismatch -- `ld1w z0\.s,p0,\[x0\]'
|
||||
@ -275,12 +275,12 @@
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1h {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1w {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1d {z0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {x0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {b0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {h0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {s0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {d0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {v0\.2s},p1/z,\[x1\]'
|
||||
.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {x0},p1/z,\[x1\]'
|
||||
.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {b0},p1/z,\[x1\]'
|
||||
.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {h0},p1/z,\[x1\]'
|
||||
.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {s0},p1/z,\[x1\]'
|
||||
.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {d0},p1/z,\[x1\]'
|
||||
.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {v0\.2s},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.h},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.s},p1/z,\[x1\]'
|
||||
@ -859,7 +859,7 @@
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#8'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#9'
|
||||
.*: Error: operand 3 must be an SVE vector register -- `lsl z0\.b,z0\.b,x0'
|
||||
.*: Error: expected an SVE vector register at operand 3 -- `lsl z0\.b,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#16'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#17'
|
||||
@ -872,7 +872,7 @@
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#8'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#9'
|
||||
.*: Error: operand 4 must be an SVE vector register -- `lsl z0\.b,p1/m,z0\.b,x0'
|
||||
.*: Error: expected an SVE vector register at operand 4 -- `lsl z0\.b,p1/m,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#16'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#17'
|
||||
@ -885,7 +885,7 @@
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#0'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#9'
|
||||
.*: Error: operand 3 must be an SVE vector register -- `lsr z0\.b,z0\.b,x0'
|
||||
.*: Error: expected an SVE vector register at operand 3 -- `lsr z0\.b,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#17'
|
||||
@ -898,7 +898,7 @@
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#0'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#9'
|
||||
.*: Error: operand 4 must be an SVE vector register -- `lsr z0\.b,p1/m,z0\.b,x0'
|
||||
.*: Error: expected an SVE vector register at operand 4 -- `lsr z0\.b,p1/m,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#17'
|
||||
@ -914,8 +914,8 @@
|
||||
.*: Error: immediate value out of range -16 to 15 at operand 3 -- `index z0\.s,#0,#16'
|
||||
.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl x0,sp,#-33'
|
||||
.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl sp,x0,#32'
|
||||
.*: Error: operand 2 must be an integer register or SP -- `addpl x0,xzr,#1'
|
||||
.*: Error: operand 1 must be an integer or stack pointer register -- `addpl xzr,x0,#1'
|
||||
.*: Error: expected an integer or stack pointer register at operand 2 -- `addpl x0,xzr,#1'
|
||||
.*: Error: expected an integer or stack pointer register at operand 1 -- `addpl xzr,x0,#1'
|
||||
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#-129'
|
||||
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#128'
|
||||
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.s,z0\.s,#-129'
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
.*: Assembler messages:
|
||||
.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,x0'
|
||||
.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,s0'
|
||||
.*: Error: expected an Advanced SIMD vector register at operand 3 -- `cmeq v0\.4s,v1\.4s,x0'
|
||||
.*: Error: expected an Advanced SIMD vector register at operand 3 -- `cmeq v0\.4s,v1\.4s,s0'
|
||||
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,p0\.b'
|
||||
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,#p0\.b'
|
||||
.*: Error: invalid base register at operand 2 -- `ldr x1,\[s0\]'
|
||||
@ -19,6 +19,6 @@
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#z0\.s'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,p0'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#p0'
|
||||
.*: Error: operand 3 must be an integer register -- `lsl x0,x0,s0'
|
||||
.*: Error: expected an integer or zero register at operand 3 -- `lsl x0,x0,s0'
|
||||
.*: Error: immediate operand required at operand 1 -- `svc x0'
|
||||
.*: Error: immediate operand required at operand 1 -- `svc s0'
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
.*: Error: constant expression required at operand 1 -- `tcancel wsp'
|
||||
.*: Error: constant expression required at operand 1 -- `tcancel xsp'
|
||||
.*: Error: constant expression required at operand 1 -- `tcancel sp'
|
||||
.*: Error: operand 1 must be an integer register -- `tstart'
|
||||
.*: Error: expected an integer or zero register at operand 1 -- `tstart'
|
||||
.*: Error: operand mismatch -- `tstart w1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: tstart x1
|
||||
@ -22,5 +22,5 @@
|
||||
.*: Error: operand mismatch -- `tstart wzr'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: tstart xzr
|
||||
.*: Error: operand 1 must be an integer register -- `tstart wsp'
|
||||
.*: Error: operand 1 must be an integer register -- `tstart xsp'
|
||||
.*: Error: expected an integer or zero register at operand 1 -- `tstart wsp'
|
||||
.*: Error: expected an integer or zero register at operand 1 -- `tstart xsp'
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user