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CSKY: Change plsl.u16 to plsl.16.

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gas/
	* testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16.
	* testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16.

opcodes/
	* csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.

Change-Id: Ifb43573192e215527355f6541365b9f6a8ec80a4
This commit is contained in:
Cooper Qu 2020-10-12 22:31:14 +08:00 committed by Lifang Xia
parent 9d1ccf22fd
commit eae61d61e9
5 changed files with 12 additions and 3 deletions
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5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
* testsuite/gas/csky/enhance_dsp.s : Change plsl.u16 to plsl.16.
* testsuite/gas/csky/enhance_dsp.d : Change plsl.u16 to plsl.16.
2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
* config/tc-csky.c (md_begin): Add version flag in eflag.

2
gas/testsuite/gas/csky/enhance_dsp.d
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@ -110,7 +110,7 @@ Disassembly of section \.text:
\s*[0-9a-f]*:\s*f8e3d302\s*plsri\.u16\.r\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f883d342\s*plsr\.u16\.r\s*r2,\s*r3,\s*r4
\s*[0-9a-f]*:\s*f8e3d402\s*plsli\.16\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*fa03d442\s*plsl\.u16\s*r2,\s*r3,\s*r16
\s*[0-9a-f]*:\s*fa03d442\s*plsl\.16\s*r2,\s*r3,\s*r16
\s*[0-9a-f]*:\s*f8e3d502\s*plsli\.u16\.s\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f8e3d582\s*plsli\.s16\.s\s*r2,\s*r3,\s*8
\s*[0-9a-f]*:\s*f883d542\s*plsl\.u16\.s\s*r2,\s*r3,\s*r4

2
gas/testsuite/gas/csky/enhance_dsp.s
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@ -110,7 +110,7 @@ hello:
plsri.u16.r r2, r3, 8
plsr.u16.r r2, r3, r4
plsli.16 r2, r3, 8
plsl.u16 r2, r3, r16
plsl.16 r2, r3, r16
plsli.u16.s r2, r3, 8
plsli.s16.s r2, r3, 8
plsl.u16.s r2, r3, r4

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
* csky-dis.c (csky_output_operand): Add handler for

2
opcodes/csky-opc.h
View File

@ -5782,7 +5782,7 @@ const struct csky_opcode csky_v2_opcodes[] =
(16_20, AREG, OPRND_SHIFT_0_BIT),
(21_25, OIMM4b, OPRND_SHIFT_0_BIT)),
CSKY_ISA_DSP_ENHANCE),
OP32 ("plsl.u16",
OP32 ("plsl.16",
OPCODE_INFO3 (0xf800d440,
(0_4, AREG, OPRND_SHIFT_0_BIT),
(16_20, AREG, OPRND_SHIFT_0_BIT),