* Patch for PR 18196, brought over from d30v branch.
[d30v/ChangeLog] 1998-11-06 Frank Ch. Eigler <fche@cygnus.com> * d30v-insns (do_mvfacc): Use loop to limit shift count to 63 .. 0. [testsuite/d30v-elf/ChangeLog] 1998-11-06 Frank Ch. Eigler <fche@cygnus.com> * do-shifts.S: Add test for large mvfacc shifts.
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sim/testsuite/d30v-elf/ChangeLog
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sim/testsuite/d30v-elf/ChangeLog
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1998-11-06 Frank Ch. Eigler <fche@cygnus.com>
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* do-shifts.S: Add test for large mvfacc shifts.
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Tue Oct 13 10:54:51 EDT 1998 Frank Ch. Eigler <fche@cygnus.com>
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* Makefile.in (TESTS): Added do-shifts test case.
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* do-shifts.S: New file.
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Wed Apr 29 12:49:00 1998 Frank Ch. Eigler <fche@cygnus.com>
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* ls-modaddr.S: New test for modular addressing.
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* Makefile.in: Run it.
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Wed Sep 3 14:33:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* Makefile.in (.S.run): Replace .d30v with .run.
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Wed Apr 2 14:10:43 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
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* Makefile.in (.d30v.ko): Limit the cpu time to 5 seconds.
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Wed Mar 26 11:13:42 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
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* Makefile.in (.d30v.ko): Disable the shell's exit-on-error which
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is enabled by BSD style make.
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sim/testsuite/d30v-elf/do-shifts.S
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sim/testsuite/d30v-elf/do-shifts.S
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# Test macro
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.macro assert reg,value
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cmpeq f0,\reg,\value
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bra/fx fail
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.endm
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# PR 14580 - a.s
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add r8,r0,0x11112222
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add r9,r0,-32
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sra r1,r8,r9 ||nop
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sra r2,r8,-32 ||nop
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srl r3,r8,r9 ||nop
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srl r4,r8,-32 ||nop
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assert r1, 0
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assert r2, 0
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assert r3, 0
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assert r4, 0
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# PR 17266 - a.s
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add r20, r0, 0xffffffff
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add r21, r0, 0xffffffff
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add r22, r0, 0xffffffff
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add r23, r0, 0xffffffff
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add r1, r0, 0x12345678
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add r2, r0, -33
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srahh r20, r1, r2
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srahl r21, r1, r2
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srlhh r22, r1, r2
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srlhl r23, r1, r2
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sra r24, r1, r2
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srl r25, r1, r2
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rot r26, r1, r2
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assert r20, 0xacf0ffff
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assert r21, 0xffffacf0
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assert r22, 0xacf0ffff
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assert r23, 0xffffacf0
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assert r24, 0x2468acf0
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assert r25, 0x2468acf0
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assert r26, 0x2468acf0
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# PR 17266 - a2.s
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add r20, r0, 0xffffffff
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add r21, r0, 0xffffffff
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add r22, r0, 0xffffffff
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add r23, r0, 0xffffffff
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add r1, r0, 0x12345678
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add r2, r0, -17
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sra2h r20, r1, r2
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srl2h r21, r1, r2
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rot2h r22, r1, r2
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assert r20, 0x2468acf0
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assert r21, 0x2468acf0
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assert r22, 0x2468acf0
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# PR 17685 - a.s
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add r20,r0,r0
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add r21,r0,r0
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add r22,r0,r0
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add r23,r0,r0
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add r24,r0,r0
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add r25,r0,r0
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add r30,r0,r0
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add r31,r0,r0
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add r8,r0,0x55555555
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add r9,r0,0x1f
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sra r20,r8,r9 ||nop
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srl r21,r8,r9 ||nop
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srahh r22,r8,r9 ||nop
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srahl r23,r8,r9 ||nop
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srlhh r24,r8,r9 ||nop
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srlhl r25,r8,r9 ||nop
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add r8,r0,0x5555aaaa
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add r9,r0,0x000ffff1
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sra2h r30,r8,r9 ||nop
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srl2h r31,r8,r9 ||nop
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assert r20, 0
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assert r21, 0
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assert r22, 0
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assert r23, 0
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assert r24, 0
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assert r25, 0
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assert r30, 0
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assert r31, 0
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# PR 18196 - a.s
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add r1,r0,0xfedcba98
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add r2,r0,0x76543210
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add r3,r0,0x41
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add r4,r0,1
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nop || mvtacc a0 r1,r2
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nop || mvfacc r10,a0 r3
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nop || mvfacc r11,a0 r4
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assert r10, 0x3b2a1908
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assert r11, 0x3b2a1908
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# all okay
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bra ok
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ok:
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add r2, r0, 0
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.long 0x0e000004
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nop
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fail:
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add r2, r0, 47
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.long 0x0e000004
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nop
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