RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.
Consider the following case, vsetvli a0, a1, 0x4 # unrecognized vlmul vsetvli a0, a1, 0x20 # unrecognized vsew vsetivli a0, 0xb, 0x4 # unrecognized vlmul vsetivli a0, 0xb, 0x20 # unrecognized vsew For the current dis-assembler, we get the result, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,e8,(null),tu,mu 4: 0205f557 vsetvli a0,a1,e128,m1,tu,mu 8: c045f557 vsetivli a0,11,e8,(null),tu,mu c: c205f557 vsetivli a0,11,e128,m1,tu,mu The vsew e128 and vlmul (null) are preserved according to the spec, so dump these fields looks wrong. Consider that we are used to dump the unrecognized csr as csr numbers directly, we should also dump the whole vset[i]vli immediates as numbers, once the vsew or vlmul is reserved. Therefore, following is what I expected, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,4 4: 0205f557 vsetvli a0,a1,32 8: c045f557 vsetivli a0,11,4 c: c205f557 vsetivli a0,11,32 gas/ * testsuite/gas/riscv/vector-insns.d: Rewrite the vset[i]vli testcases since we should dump the immediate as numbers once the vsew or vlmul is reserved. * testsuite/gas/riscv/vector-insns.s: Likewise. opcodes/ * riscv-dis.c (print_insn_args): The reserved vsew and vlmul are NULL string in the riscv_vsew and riscv_vlmul, so dump the whole imm as numbers once one of them is NULL. * riscv-opc.c (riscv_vsew): Set the reserved vsew to NULL. (riscv_vlmul): Set the reserved vlmul to NULL.
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Nelson Chu
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@ -10,40 +10,20 @@ Disassembly of section .text:
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[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
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[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu
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[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
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[ ]+[0-9a-f]+:[ ]+0095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+02b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu
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[ ]+[0-9a-f]+:[ ]+0335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu
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[ ]+[0-9a-f]+:[ ]+03b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu
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[ ]+[0-9a-f]+:[ ]+0385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu
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[ ]+[0-9a-f]+:[ ]+03f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu
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[ ]+[0-9a-f]+:[ ]+0365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu
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[ ]+[0-9a-f]+:[ ]+02d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu
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[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
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[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
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[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+0e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma
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[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
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[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
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[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4
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[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32
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[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu
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[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu
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[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma
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[ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu
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[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,ta,ma
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[ ]+[0-9a-f]+:[ ]+c095f557[ ]+vsetivli[ ]+a0,11,e16,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+c2b5f557[ ]+vsetivli[ ]+a0,11,e256,m8,tu,mu
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[ ]+[0-9a-f]+:[ ]+c335f557[ ]+vsetivli[ ]+a0,11,e512,m8,tu,mu
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[ ]+[0-9a-f]+:[ ]+c3b5f557[ ]+vsetivli[ ]+a0,11,e1024,m8,tu,mu
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[ ]+[0-9a-f]+:[ ]+c385f557[ ]+vsetivli[ ]+a0,11,e1024,m1,tu,mu
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[ ]+[0-9a-f]+:[ ]+c3f5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,tu,mu
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[ ]+[0-9a-f]+:[ ]+c365f557[ ]+vsetivli[ ]+a0,11,e512,mf4,tu,mu
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[ ]+[0-9a-f]+:[ ]+c2d5f557[ ]+vsetivli[ ]+a0,11,e256,mf8,tu,mu
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[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu
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[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma
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[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+ce95f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,ma
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[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma
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[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu
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[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023
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[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4
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[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32
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[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu
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[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu
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[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu
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[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma
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[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
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[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
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[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
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@ -1,40 +1,20 @@
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vsetvl a0, a1, a2
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vsetvli a0, a1, 0
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vsetvli a0, a1, 0x7ff
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vsetvli a0, a1, e16, m2
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vsetvli a0, a1, e256, m8
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vsetvli a0, a1, e512, m8
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vsetvli a0, a1, e1024, m8
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vsetvli a0, a1, e1024, m1
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vsetvli a0, a1, e1024, mf2
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vsetvli a0, a1, e512, mf4
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vsetvli a0, a1, e256, mf8
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vsetvli a0, a1, e256, m2, ta
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vsetvli a0, a1, e256, m2, ma
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vsetvli a0, a1, e256, m2, tu
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vsetvli a0, a1, e256, m2, mu
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vsetvli a0, a1, e256, m2, ta, ma
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vsetvli a0, a1, e256, m2, tu, ma
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vsetvli a0, a1, e256, m2, ta, mu
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vsetvli a0, a1, e256, m2, tu, mu
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vsetvl a0, a1, a2
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vsetvli a0, a1, 0
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vsetvli a0, a1, 0x7ff
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vsetvli a0, a1, 0x4 # unrecognized vlmul
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vsetvli a0, a1, 0x20 # unrecognized vsew
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vsetvli a0, a1, e8, m2
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vsetvli a0, a1, e16, m4, ta
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vsetvli a0, a1, e32, mf4, mu
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vsetvli a0, a1, e64, mf8, tu, ma
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vsetivli a0, 0xb, 0
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vsetivli a0, 0xb, 0x3ff
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vsetivli a0, 0xb, e16, m2
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vsetivli a0, 0xb, e256, m8
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vsetivli a0, 0xb, e512, m8
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vsetivli a0, 0xb, e1024, m8
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vsetivli a0, 0xb, e1024, m1
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vsetivli a0, 0xb, e1024, mf2
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vsetivli a0, 0xb, e512, mf4
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vsetivli a0, 0xb, e256, mf8
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vsetivli a0, 0xb, e256, m2, ta
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vsetivli a0, 0xb, e256, m2, ma
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vsetivli a0, 0xb, e256, m2, tu
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vsetivli a0, 0xb, e256, m2, mu
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vsetivli a0, 0xb, e256, m2, ta, ma
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vsetivli a0, 0xb, e256, m2, tu, ma
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vsetivli a0, 0xb, e256, m2, ta, mu
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vsetivli a0, 0xb, e256, m2, tu, mu
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vsetivli a0, 0xb, 0x4 # unrecognized vlmul
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vsetivli a0, 0xb, 0x20 # unrecognized vsew
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vsetivli a0, 0xb, e8, m2
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vsetivli a0, 0xb, e16, m4, ta
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vsetivli a0, 0xb, e32, mf4, mu
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vsetivli a0, 0xb, e64, mf8, tu, ma
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vlm.v v4, (a0)
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vlm.v v4, 0(a0)
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@ -334,7 +334,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
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&& imm_vlmul < ARRAY_SIZE (riscv_vlmul)
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&& imm_vta < ARRAY_SIZE (riscv_vta)
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&& imm_vma < ARRAY_SIZE (riscv_vma)
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&& !imm_vtype_res)
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&& !imm_vtype_res
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&& riscv_vsew[imm_vsew] != NULL
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&& riscv_vlmul[imm_vlmul] != NULL)
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print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew],
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riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
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riscv_vma[imm_vma]);
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@ -76,13 +76,13 @@ const char * const riscv_vecm_names_numeric[NVECM] =
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/* The vsetvli vsew constants. */
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const char * const riscv_vsew[8] =
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{
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"e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
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"e8", "e16", "e32", "e64", NULL, NULL, NULL, NULL
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};
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/* The vsetvli vlmul constants. */
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const char * const riscv_vlmul[8] =
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{
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"m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
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"m1", "m2", "m4", "m8", NULL, "mf8", "mf4", "mf2"
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};
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/* The vsetvli vta constants. */
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