gas/
* config/tc-sparc.c: Accept 'softint_clear' and 'softint_set' %asr aliases. * doc/c-sparc.texi: Consistently refer to architecture 'versions', rather than occaisionally 'levels'. Consistently refer to Sun's UNIX variant as SunOS, every version of Solaris is also SunOS. Document new 'softint_clear' and 'softint_set' aliases. Clarify which architecture versions support '%dcr', '%cq', and '%gl'. Add section on 32-bit/64-bit opcode translations. opcodes/ * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr instead of %sys_tick_cmpr, as suggested in architecture manuals.
This commit is contained in:
David S. Miller
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@ -1,3 +1,15 @@
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2008-04-25 David S. Miller <davem@davemloft.net>
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* config/tc-sparc.c: Accept 'softint_clear' and 'softint_set'
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%asr aliases.
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* doc/c-sparc.texi: Consistently refer to architecture 'versions',
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rather than occaisionally 'levels'. Consistently refer to Sun's
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UNIX variant as SunOS, every version of Solaris is also SunOS.
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Document new 'softint_clear' and 'softint_set' aliases. Clarify
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which architecture versions support '%dcr', '%cq', and '%gl'. Add
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section on 32-bit/64-bit opcode translations.
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2008-04-23 Mike Frysinger <vapier@gentoo.org>
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* Makefile.am (OBJ_FORMAT_CFILES): Add config/obj-fdpicelf.c.
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@ -779,6 +779,8 @@ struct priv_reg_entry v9a_asr_table[] =
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{"stick_cmpr", 25},
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{"stick", 24},
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{"softint", 22},
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{"softint_clear", 21},
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{"softint_set", 20},
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{"set_softint", 20},
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{"pic", 17},
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{"pcr", 16},
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@ -28,9 +28,9 @@
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@cindex SPARC options
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@cindex architectures, SPARC
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@cindex SPARC architectures
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The SPARC chip family includes several successive levels, using the same
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The SPARC chip family includes several successive versions, using the same
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core instruction set, but including a few additional instructions at
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each level. There are exceptions to this however. For details on what
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each version. There are exceptions to this however. For details on what
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instructions each variant supports, please see the chip's architecture
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reference manual.
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@ -40,7 +40,7 @@ successively higher architectures as it encounters instructions that
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only exist in the higher levels.
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If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
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passed sparclite by default, an option must be passed to enable the
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past sparclite by default, an option must be passed to enable the
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v9 instructions.
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GAS treats sparclite as being compatible with v8, unless an architecture
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@ -74,7 +74,7 @@ support.
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UltraSPARC extensions.
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@item -xarch=v8plus | -xarch=v8plusa
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For compatibility with the Solaris v9 assembler. These options are
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For compatibility with the SunOS v9 assembler. These options are
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equivalent to -Av8plus and -Av8plusa, respectively.
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@item -bump
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@ -96,12 +96,12 @@ and require that the necessary BFD support has been included.
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@cindex SPARC data alignment
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SPARC GAS normally permits data to be misaligned. For example, it
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permits the @code{.long} pseudo-op to be used on a byte boundary.
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However, the native SunOS and Solaris assemblers issue an error when
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they see misaligned data.
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However, the native SunOS assemblers issue an error when they see
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misaligned data.
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@kindex --enforce-aligned-data
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You can use the @code{--enforce-aligned-data} option to make SPARC GAS
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also issue an error about misaligned data, just as the SunOS and Solaris
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also issue an error about misaligned data, just as the SunOS
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assemblers do.
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The @code{--enforce-aligned-data} option is not the default because gcc
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@ -123,6 +123,7 @@ for their UltraSPARC and Niagara line of processors.
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* Sparc-Regs:: Register Names
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* Sparc-Constants:: Constant Names
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* Sparc-Relocs:: Relocations
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* Sparc-Size-Translations:: Size Translations
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@end menu
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@node Sparc-Chars
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@ -177,7 +178,7 @@ is a legal floating point register, but @samp{%f35} is not.
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Certain V9 instructions allow access to ancillary state registers.
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Most simply they can be referred to as @samp{%asr@var{n}} where
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@var{n} can be from 16 to 31. However, there are some aliased
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@var{n} can be from 16 to 31. However, there are some aliases
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defined to reference ASR registers defined for various UltraSPARC
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processors:
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@ -200,10 +201,12 @@ The software interrupt register is referred to as @samp{%softint}.
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@item
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The set software interrupt register is referred to as @samp{%set_softint}.
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The mnemonic @samp{%softint_set} is provided as an alias.
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@item
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The clear software interrupt register is referred to as
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@samp{%clear_softint}.
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@samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
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as an alias.
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@item
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The performance instrumentation counters register is referred to as
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@ -216,7 +219,7 @@ The performance control register is referred to as @samp{%pcr}.
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The graphics status register is referred to as @samp{%gsr}.
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@item
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The dispatch control register is referred to as @samp{%dcr}.
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The V9 dispatch control register is referred to as @samp{%dcr}.
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@end itemize
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Various V9 branch and conditional move instructions allow
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@ -249,7 +252,7 @@ The V9 current window pointer register is referred to as @samp{%cwp}.
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The floating-point queue register is referred to as @samp{%fq}.
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@item
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The co-processor queue register is referred to as @samp{%cq}.
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The V8 co-processor queue register is referred to as @samp{%cq}.
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@item
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The floating point status register is referred to as @samp{%fsr}.
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@ -312,7 +315,7 @@ The V8 window invalid mask register is referred to as @samp{%wim}.
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The V8 processor state register is referred to as @samp{%psr}.
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@item
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The global register level register is referred to as @samp{%gl}.
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The V9 global register level register is referred to as @samp{%gl}.
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@end itemize
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Several special register names exist for hypervisor mode code:
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@ -644,6 +647,73 @@ specified in an address expression that would normally generate
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an @code{R_SPARC_LO10} relocation, the assembler will emit an
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@code{R_SPARC_OLO10} instead.
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@node Sparc-Size-Translations
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@subsection Size Translations
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@cindex Sparc size translations
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@cindex size, translations, Sparc
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Often it is desirable to write code in an operand size agnostic
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manner. @code{@value{AS}} provides support for this via
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operand size opcode translations. Translations are supported
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for loads, stores, shifts, compare-and-swap atomics, and the
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@samp{clr} synthetic instruction.
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If generating 32-bit code, @code{@value{AS}} will generate the
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32-bit opcode. Whereas if 64-bit code is being generated,
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the 64-bit opcode will be emitted. For example @code{ldn}
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will be transformed into @code{ld} for 32-bit code and
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@code{ldx} for 64-bit code.
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Here is an example meant to demonstrate all the supported
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opcode translations:
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@example
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ldn [%o0], %o1
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ldna [%o0] %asi, %o2
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stn %o1, [%o0]
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stna %o2, [%o0] %asi
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slln %o3, 3, %o3
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srln %o4, 8, %o4
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sran %o5, 12, %o5
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casn [%o0], %o1, %o2
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casna [%o0] %asi, %o1, %o2
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clrn %g1
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@end example
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In 32-bit mode @code{@value{AS}} will emit:
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@example
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ld [%o0], %o1
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lda [%o0] %asi, %o2
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st %o1, [%o0]
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sta %o2, [%o0] %asi
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sll %o3, 3, %o3
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srl %o4, 8, %o4
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sra %o5, 12, %o5
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cas [%o0], %o1, %o2
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casa [%o0] %asi, %o1, %o2
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clr %g1
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@end example
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And in 64-bit mode @code{@value{AS}} will emit:
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@example
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ldx [%o0], %o1
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ldxa [%o0] %asi, %o2
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stx %o1, [%o0]
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stxa %o2, [%o0] %asi
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sllx %o3, 3, %o3
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srlx %o4, 8, %o4
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srax %o5, 12, %o5
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casx [%o0], %o1, %o2
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casxa [%o0] %asi, %o1, %o2
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clrx %g1
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@end example
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Finally, the @samp{.nword} translating directive is supported
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as well. It is documented in the section on Sparc machine
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directives.
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@node Sparc-Float
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@section Floating Point
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@ -1,3 +1,8 @@
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2008-04-25 David S. Miller <davem@davemloft.net>
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* sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
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instead of %sys_tick_cmpr, as suggested in architecture manuals.
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2008-04-23 Paolo Bonzini <bonzini@gnu.org>
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* aclocal.m4: Regenerate.
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@ -107,7 +107,7 @@ static char *v9_hpriv_reg_names[] =
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static char *v9a_asr_reg_names[] =
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{
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"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
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"softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
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"softint", "tick_cmpr", "stick", "stick_cmpr"
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};
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/* Macros used to extract instruction fields. Not all fields have
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