PR26656 testcases
* testsuite/ld-powerpc/tlsget.d, * testsuite/ld-powerpc/tlsget.s, * testsuite/ld-powerpc/tlsget.wf, * testsuite/ld-powerpc/tlsget2.d. * testsuite/ld-powerpc/tlsget2.wf: New testcases. * testsuite/ld-powerpc/powerpc.exp: Run them.
This commit is contained in:
Alan Modra
parent
2c72d5e58a
commit
f243e458cd
@ -1,3 +1,12 @@
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2020-09-28 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/tlsget.d,
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* testsuite/ld-powerpc/tlsget.s,
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* testsuite/ld-powerpc/tlsget.wf,
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* testsuite/ld-powerpc/tlsget2.d.
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* testsuite/ld-powerpc/tlsget2.wf: New testcases.
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* testsuite/ld-powerpc/powerpc.exp: Run them.
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2020-09-26 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/elfv2so.d,
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@ -286,6 +286,12 @@ set ppc64elftests {
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{"TLSdesc4" "-melf64ppc --no-tls-optimize tmpdir/tlsdll.o" "" "-a64" {tlsdesc4.s}
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{{objdump -dr tlsdesc4.d} {readelf -wf tlsdesc4.wf}}
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"tlsdesc4"}
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{"tlsget" "-shared --hash-style=both -melf64ppc --plt-align=0" "tmpdir/tlsdll.so" "-a64 -mpower10" {tlsget.s}
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{{objdump -dr tlsget.d} {readelf -wf tlsget.wf}}
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"tlsget.so"}
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{"tlsget2" "-shared --hash-style=both -melf64ppc --plt-align=0 --power10-stubs=yes" "tmpdir/tlsdll.so" "-a64 -mpower10" {tlsget.s}
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{{objdump -dr tlsget2.d} {readelf -wf tlsget2.wf}}
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"tlsget2.so"}
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{"sym@tocbase" "-shared -melf64ppc" "" "-a64" {symtocbase-1.s symtocbase-2.s}
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{{objdump -dj.data symtocbase.d}} "symtocbase.so"}
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{"TOC opt" "-melf64ppc" "" "-a64" {tocopt.s}
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89
ld/testsuite/ld-powerpc/tlsget.d
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89
ld/testsuite/ld-powerpc/tlsget.d
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@ -0,0 +1,89 @@
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#source: tlsget.s
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#as: -a64 -mpower10
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#ld: -shared --plt-align=0 tlsdll.so
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#objdump: -dr
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#target: powerpc64*-*-*
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.*: file format .*
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Disassembly of section \.text:
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.* <.*\.plt_call\..*>:
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.*: (04 10 .. ..|.. .. 10 04) pld r12,.*
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.*: (e5 80 .. ..|.. .. 80 e5)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 .. ..|.. .. 82 e9) ld r12,.*\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <.*\.plt_call\.__tls_get_addr_opt.*>:
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.*: (e8 03 00 00|00 00 03 e8) ld r0,0\(r3\)
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.*: (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
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.*: (2c 20 00 00|00 00 20 2c) cmpdi r0,0
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.*: (7c 60 1b 78|78 1b 60 7c) mr r0,r3
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.*: (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
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.*: (4d 82 00 20|20 00 82 4d) beqlr
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.*: (7c 03 03 78|78 03 03 7c) mr r3,r0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 10 .. ..|.. .. 10 04) pld r12,.*
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.*: (e5 80 .. ..|.. .. 80 e5)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.*: (e8 03 00 00|00 00 03 e8) ld r0,0\(r3\)
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.*: (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
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.*: (2c 20 00 00|00 00 20 2c) cmpdi r0,0
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.*: (7c 60 1b 78|78 1b 60 7c) mr r0,r3
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.*: (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
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.*: (4d 82 00 20|20 00 82 4d) beqlr
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.*: (7c 03 03 78|78 03 03 7c) mr r3,r0
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (f8 01 00 08|08 00 01 f8) std r0,8\(r1\)
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 .. ..|.. .. 82 e9) ld r12,.*\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 21|21 04 80 4e) bctrl
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (e8 01 00 08|08 00 01 e8) ld r0,8\(r1\)
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (4e 80 00 20|20 00 80 4e) blr
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#...
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.* <_start>:
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.*: (06 10 .. ..|.. .. 10 06) pla r3,.*
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.*: (38 60 .. ..|.. .. 60 38)
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*\.plt_call\.__tls_get_addr_opt[^\+]*>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 62 .. ..|.. .. 62 38) addi r3,r2,.*
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*\.plt_call\.__tls_get_addr_opt.*\+0x30>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*\.plt_call\..*:[^\+]*>
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*.plt_call\..*:.*\+0x10>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.* <fun>:
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.*: (06 10 00 00|00 00 10 06) pla r3,8
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.*: (38 60 00 08|08 00 60 38)
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.*: (4e 80 00 20|20 00 80 4e) blr
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (00 00 00 00|90 02 01 00) .*
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.*: (00 01 02 90|00 00 00 00) .*
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.* <__glink_PLTresolve>:
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.* <__glink_PLTresolve\+0x8>
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.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\)
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.*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <__tls_get_addr_opt@plt>:
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.*: (4b ff .. ..|.. .. ff 4b) b .* <__glink_PLTresolve>
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24
ld/testsuite/ld-powerpc/tlsget.s
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24
ld/testsuite/ld-powerpc/tlsget.s
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@ -0,0 +1,24 @@
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.text
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.abiversion 2
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.globl _start
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_start:
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.cfi_startproc
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pla 3,gd@got@tlsgd@pcrel
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bl __tls_get_addr@notoc(gd@tlsgd)
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addis 3,2,gd@got@tlsgd@ha
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addi 3,3,gd@got@tlsgd@l
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bl __tls_get_addr(gd@tlsgd)
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nop
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bl fun@notoc
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bl fun
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nop
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.type fun,@gnu_indirect_function
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fun:
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pla 3,1f@pcrel
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1:
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blr
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.cfi_endproc
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27
ld/testsuite/ld-powerpc/tlsget.wf
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27
ld/testsuite/ld-powerpc/tlsget.wf
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@ -0,0 +1,27 @@
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Contents of the .eh_frame section:
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0+ 0+10 0+ CIE
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Version: 1
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Augmentation: "zR"
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Code alignment factor: 4
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Data alignment factor: -8
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Return address column: 65
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Augmentation data: 1b
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DW_CFA_def_cfa: r1 ofs 0
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0+14 0+14 0+18 FDE cie=0+ pc=0+280..0+314
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DW_CFA_advance_loc: 128 to 0+300
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DW_CFA_offset_extended_sf: r65 at cfa\+8
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DW_CFA_advance_loc: 16 to .*
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DW_CFA_restore_extended: r65
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0+2c 0+14 0+30 FDE cie=0+ pc=0+380..0+3b8
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DW_CFA_advance_loc: 8 to 0+388
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DW_CFA_register: r65 in r0
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DW_CFA_advance_loc: 8 to .*
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DW_CFA_restore_extended: r65
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0+44 0+10 0+48 FDE cie=0+ pc=0+340..0+374
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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76
ld/testsuite/ld-powerpc/tlsget2.d
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76
ld/testsuite/ld-powerpc/tlsget2.d
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@ -0,0 +1,76 @@
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#source: tlsget.s
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#as: -a64 -mpower10
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#ld: -shared --plt-align=0 --power10-stubs=yes tlsdll.so
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#objdump: -dr
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#target: powerpc64*-*-*
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.*: file format .*
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Disassembly of section \.text:
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.* <.*\.plt_call\..*>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 10 .. ..|.. .. 10 04) pld r12,.*
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.*: (e5 80 .. ..|.. .. 80 e5)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <.*\.plt_call\.__tls_get_addr_opt.*>:
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.*: (e8 03 00 00|00 00 03 e8) ld r0,0\(r3\)
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.*: (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
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.*: (2c 20 00 00|00 00 20 2c) cmpdi r0,0
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.*: (7c 60 1b 78|78 1b 60 7c) mr r0,r3
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.*: (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
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.*: (4d 82 00 20|20 00 82 4d) beqlr
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.*: (7c 03 03 78|78 03 03 7c) mr r3,r0
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (f8 01 00 08|08 00 01 f8) std r0,8\(r1\)
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (04 10 .. ..|.. .. 10 04) pld r12,.*
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.*: (e5 80 .. ..|.. .. 80 e5)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 21|21 04 80 4e) bctrl
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (e8 01 00 08|08 00 01 e8) ld r0,8\(r1\)
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (4e 80 00 20|20 00 80 4e) blr
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#...
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.* <_start>:
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.*: (06 10 .. ..|.. .. 10 06) pla r3,.*
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.*: (38 60 .. ..|.. .. 60 38)
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*\.plt_call\.__tls_get_addr_opt[^\+]*>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 62 .. ..|.. .. 62 38) addi r3,r2,.*
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*\.plt_call\.__tls_get_addr_opt[^\+]*>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*\.plt_call\..*:.*\+0x4>
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.*: (4b ff .. ..|.. .. ff 4b) bl .* <.*.plt_call\..*:[^\+]*>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.* <fun>:
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.*: (06 10 00 00|00 00 10 06) pla r3,8
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.*: (38 60 00 08|08 00 60 38)
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.*: (4e 80 00 20|20 00 80 4e) blr
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (00 00 00 00|d0 02 01 00) .*
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.*: (00 01 02 d0|00 00 00 00) .*
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.* <__glink_PLTresolve>:
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.* <__glink_PLTresolve\+0x8>
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.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\)
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.*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\)
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <__tls_get_addr_opt@plt>:
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.*: (4b ff .. ..|.. .. ff 4b) b .* <__glink_PLTresolve>
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27
ld/testsuite/ld-powerpc/tlsget2.wf
Normal file
27
ld/testsuite/ld-powerpc/tlsget2.wf
Normal file
@ -0,0 +1,27 @@
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Contents of the .eh_frame section:
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0+ 0+10 0+ CIE
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Version: 1
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Augmentation: "zR"
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Code alignment factor: 4
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Data alignment factor: -8
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Return address column: 65
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Augmentation data: 1b
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DW_CFA_def_cfa: r1 ofs 0
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0+14 0+14 0+18 FDE cie=0+ pc=0+280..0+2e0
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DW_CFA_advance_loc: 76 to 0+2cc
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DW_CFA_offset_extended_sf: r65 at cfa\+8
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DW_CFA_advance_loc: 16 to .*
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DW_CFA_restore_extended: r65
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0+2c 0+14 0+30 FDE cie=0+ pc=0+340..0+378
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DW_CFA_advance_loc: 8 to 0+348
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DW_CFA_register: r65 in r0
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DW_CFA_advance_loc: 8 to .*
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DW_CFA_restore_extended: r65
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0+44 0+10 0+48 FDE cie=0+ pc=0+300..0+334
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DW_CFA_nop
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DW_CFA_nop
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DW_CFA_nop
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