yggdrasil/binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sim: sh64: delete port

Browse Source 
Support for sh64 was dropped from bfd et al in 2018.  Without
that, the sim port is useless.  So clean up this code too.
This commit is contained in:
Mike Frysinger 2021-01-09 02:40:14 -05:00
parent 50df264dae
commit f8cab0b995
430 changed files with 13 additions and 73941 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
sim/ChangeLog
View File

@ -1,3 +1,10 @@
2021-01-09 Mike Frysinger <vapier@gentoo.org>
* MAINTAINERS (sh64): Move to past maintainers.
* configure: Regenerate.
* configure.tgt (sh64*-*-*): Delete.
* sh64/: Delete.
2021-01-09 Mike Frysinger <vapier@gentoo.org>
* README-HACKING (AC_PREREQ): Delete.

2
sim/MAINTAINERS
View File

@ -32,7 +32,6 @@ msp430 Nick Clifton <nickc@redhat.com>
or1k Stafford Horne <shorne@gmail.com>
pru Dimitar Dimitrov <dimitar@dinux.eu>
sh (global maintainers)
sh64 Dave Brolley <brolley@redhat.com>
common Frank Ch. Eigler <fche@redhat.com>
* (target, then global maintainers)
@ -50,5 +49,6 @@ ppc Geoff Keating <geoffk@geoffk.org>
ppc Andrew Cagney <cagney@gnu.org>
rl78 DJ Delorie <dj@redhat.com>
rx DJ Delorie <dj@redhat.com>
sh64 Dave Brolley <brolley@redhat.com>
v850 DJ Delorie <dj@redhat.com>
* Mike Frysinger <vapier@gentoo.org>

8
sim/configure vendored
View File

@ -690,7 +690,6 @@ or1k
pru
rl78
rx
sh64
sh
erc32
ppc
@ -3867,13 +3866,6 @@ subdirs="$subdirs aarch64"
subdirs="$subdirs rx"
;;
sh64*-*-*)
sim_arch=sh64
subdirs="$subdirs sh64"
;;
sh*-*-*)

3
sim/configure.tgt
View File

@ -91,9 +91,6 @@ case "${target}" in
rx-*-*)
SIM_ARCH(rx)
;;
sh64*-*-*)
SIM_ARCH(sh64)
;;
sh*-*-*)
SIM_ARCH(sh)
;;

864
sim/sh64/ChangeLog
View File

@ -1,864 +0,0 @@
2021-01-09 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2021-01-08 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2021-01-04 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2017-09-06 John Baldwin <jhb@FreeBSD.org>
* configure: Regenerate.
2017-02-13 Mike Frysinger <vapier@gentoo.org>
* decode-compact.c (sh64_compact_init_idesc_table): Use ARRAY_SIZE.
* decode-media.c (sh64_media_init_idesc_table): Likewise.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* config.in, configure: Regenerate.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
* configure: Regenerate.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_AC_OPTION_INLINE): Delete call.
* configure: Regenerate.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2016-01-10 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2016-01-09 Mike Frysinger <vapier@gentoo.org>
* config.in, configure: Regenerate.
2016-01-06 Mike Frysinger <vapier@gentoo.org>
* sim-if.c (sim_open): Mark argv const.
(sim_create_inferior): Mark argv and env const.
2016-01-04 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2016-01-03 Mike Frysinger <vapier@gentoo.org>
* sim-if.c (sim_open): Update sim_parse_args comment.
2016-01-03 Mike Frysinger <vapier@gentoo.org>
* sh64-sim.h (GETTWI, SETTWI): Delete unused defines.
(sh5_devices): Delete.
(struct _device): Delete.
2016-01-03 Mike Frysinger <vapier@gentoo.org>
* sh64.c (count_argc): Delete.
(trap_handler): Change count_argc to countargv.
2016-01-03 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
* configure: Regenerate.
2016-01-02 Mike Frysinger <vapier@gentoo.org>
* arch.h (TARGET_BIG_ENDIAN): Delete.
* configure.ac (SIM_AC_OPTION_ENDIAN): Change BIG_ENDIAN to BIG.
* configure: Regenerate.
2016-01-02 Mike Frysinger <vapier@gentoo.org>
* sim-if.c (sim_open): Delete #if 0 sim_add_option_table call.
2016-01-02 Mike Frysinger <vapier@gentoo.org>
* sim-if.c (current_state): Delete.
(sim_open): Delete current_state assignment.
2015-12-27 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_OBJS): Delete sim-hload.o.
2015-12-26 Mike Frysinger <vapier@gentoo.org>
* config.in, configure: Regenerate.
2015-12-26 Mike Frysinger <vapier@gentoo.org>
* sim-if.c (sim_create_inferior): Replace old #if 0 code with dupargv.
2015-12-25 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_OBJS): Delete sim-model.o.
* tconfig.h: Delete file.
2015-12-25 Mike Frysinger <vapier@gentoo.org>
* arch.c: Rename MACH to SIM_MACH.
* cpuall.h: Likewise.
* sh64.c: Rename MACH to SIM_MACH, MACH_IMP_PROPERTIES to
SIM_MACH_IMP_PROPERTIES, and MODEL to SIM_MODEL.
2015-12-25 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (WITH_SCACHE_PBB): Move from ...
* tconfig.h (WITH_SCACHE_PBB): ... here.
2015-12-24 Mike Frysinger <vapier@gentoo.org>
* tconfig.h (SIM_HANDLES_LMA): Delete.
2015-12-24 Mike Frysinger <vapier@gentoo.org>
* tconfig.h (SIM_HAVE_BREAKPOINTS, SIM_BREAKPOINT,
SIM_BREAKPOINT_SIZE): Delete.
2015-12-24 Mike Frysinger <vapier@gentoo.org>
* tconfig.h (WITH_WATCHPOINTS): Delete.
2015-12-24 Mike Frysinger <vapier@gentoo.org>
* tconfig.h (SIM_HAVE_MEM_SIZE): Delete.
2015-11-15 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_OBJS): Delete sim-reason.o, sim-reg.o, and
sim-stop.o.
2015-11-14 Mike Frysinger <vapier@gentoo.org>
* sim-if.c (sim_close): Delete.
2015-06-23 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-06-12 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-06-12 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-06-12 Mike Frysinger <vapier@gentoo.org>
* decode-compact.c (sh64_compact_decode): Change TRACE_EXTRACT to
CGEN_TRACE_EXTRACT.
* decode-media.c: Likewise.
* mloop-compact.in (execute): Change TRACE_INSN_INIT to
CGEN_TRACE_INSN_INIT, TRACE_INSN to CGEN_TRACE_INSN, and TRACE_INSN_FINI
to CGEN_TRACE_INSN_FINI.
(sh64_compact_pbb_before): Likewise.
(sh64_compact_pbb_after): Change TRACE_INSN_FINI to CGEN_TRACE_INSN_FINI.
* mloop-media.in: Likewise.
* sem-compact.c: Rename TRACE_RESULT to CGEN_TRACE_RESULT.
* sem-compact-switch.c: Likewise.
* sem-media.c: Likewise.
* sem-media-switch.c: Likewise.
2015-04-18 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (USING_SIM_BASE_H): Delete.
2015-04-18 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (_sim_cpu, SIM_CPU): Delete.
2015-04-18 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (CIA_ADDR): Define.
2015-04-17 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (CIA_GET, CIA_SET): Delete.
2015-04-15 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_OBJS): Delete sim-cpu.o.
* sim-main.h (STATE_CPU): Delete.
2015-04-15 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (struct sim_state): Change cpu to an array of pointers.
(STATE_CPU): Handle WITH_SMP.
2015-04-13 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-04-06 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_OBJS): Delete sim-engine.o and sim-hrw.o.
2015-03-31 Mike Frysinger <vapier@gentoo.org>
* config.in, configure: Regenerate.
2015-03-24 Mike Frysinger <vapier@gentoo.org>
* tconfig.h (SIM_HAVE_BIENDIAN): Delete.
2015-03-24 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-03-24 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-03-23 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-03-23 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2015-03-23 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (CONFIG_DEVICES): Delete.
(SIM_OBJS): Delete CONFIG_DEVICES.
2015-03-16 Mike Frysinger <vapier@gentoo.org>
* aclocal.m4, config.in, configure: Regenerate.
* tconfig.in: Rename file ...
* tconfig.h: ... here.
2015-03-15 Mike Frysinger <vapier@gentoo.org>
* tconfig.in [HAVE_DV_SOCKSER]: Delete.
2015-03-14 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_RUN_OBJS): Delete.
2014-08-23 Hans-Peter Nilsson <hp@axis.com>
* configure.ac: Default simulator hardware to off again
without emitting errors when off or dv-sockser.o unavailable.
* configure: Regenerate.
2014-08-19 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
2014-08-15 Roland McGrath <mcgrathr@google.com>
* configure: Regenerate.
* config.in: Regenerate.
2013-09-23 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
2013-06-03 Mike Frysinger <vapier@gentoo.org>
* aclocal.m4, configure: Regenerate.
2013-03-26 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
* configure.ac: Fail if dv-sockser.o not available.
Error when --disable-sim-hardware is specified.
* configure: Regenerated.
2012-06-15 Joel Brobecker <brobecker@adacore.com>
* config.in, configure: Regenerate.
2012-05-18 Nick Clifton <nickc@redhat.com>
PR 14072
* interp.c: Include config.h before system header files.
2012-03-24 Mike Frysinger <vapier@gentoo.org>
* aclocal.m4, config.in, configure: Regenerate.
2011-12-03 Mike Frysinger <vapier@gentoo.org>
* aclocal.m4: New file.
* configure: Regenerate.
2011-10-17 Mike Frysinger <vapier@gentoo.org>
* configure.ac: Change include to common/acinclude.m4.
2011-10-17 Mike Frysinger <vapier@gentoo.org>
* configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
call. Replace common.m4 include with SIM_AC_COMMON.
* configure: Regenerate.
2011-07-05 Mike Frysinger <vapier@gentoo.org>
* sim-if.c (sim_do_command): Delete.
2011-02-14 Mike Frysinger <vapier@gentoo.org>
* sh64.c (trap_handler): Change zfree to free.
2010-10-09 Alan Modra <amodra@gmail.com>
* sh-desc.h: Regenerate.
2010-02-12 Doug Evans <dje@sebabeach.org>
* decode-media.c, * decode-media.h: Regenerate.
2010-02-11 Doug Evans <dje@sebabeach.org>
* decode-compact.c, * decode-media.c, * defs-compact.h, * defs-media.h,
* sem-compact-switch.c, * sem-compact.c, * sem-media-switch.c,
* sem-media.c, * sh-desc.c, * sh-desc.h: Regenerate.
2010-01-24 Doug Evans <dje@sebabeach.org>
* cpu.h: Regenerate.
2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* configure: Regenerate.
2010-01-02 Doug Evans <dje@sebabeach.org>
* arch.c, * arch.h, * cpu.c, * cpu.h, * cpuall.h, * decode-compact.c,
* decode-compact.h, * decode-media.c, * decode-media.h,
* defs-compact.h, * defs-media.h, * sem-compact-switch.c,
* sem-compact.c, * sem-media-switch.c, * sem-media.c, * sh-desc.c,
* sh-desc.h, * sh-opc.h: Regenerate, update copyright year.
2009-11-22 Doug Evans <dje@sebabeach.org>
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode-compact.c: Regenerate.
* decode-compact.h: Regenerate.
* decode-media.c: Regenerate.
* decode-media.h: Regenerate.
* defs-compact.h: Regenerate.
* defs-media.h: Regenerate.
2009-11-03 Doug Evans <dje@sebabeach.org>
* arch.c: Regenerate.
* arch.h: Regenerate.
* cpu.c: Regenerate.
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode-compact.c: Regenerate.
* decode-compact.h: Regenerate.
* decode-media.c: Regenerate.
* decode-media.h: Regenerate.
* defs-compact.h: Regenerate.
* defs-media.h: Regenerate.
* sem-compact-switch.c: Regenerate.
* sem-compact.c: Regenerate.
* sem-media-switch.c: Regenerate.
* sem-media.c: Regenerate.
* sh-desc.c: Regenerate.
* sh-opc.h: Regenerate.
* Makefile.in (SIM_EXTRA_DEPS): Add sh-desc.h sh-opc.h.
(sh-desc.o): New rule.
(sh-desc.h,sh-desc.c,sh-opc.h): Replaces rule for desc.h.
(all generated file rules): Specify generated file with full path.
2009-10-24 Doug Evans <dje@sebabeach.org>
* sh-desc.h: Regenerate.
2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* config.in: Regenerate.
* configure: Likewise.
* configure: Regenerate.
2008-07-11 Hans-Peter Nilsson <hp@axis.com>
* configure: Regenerate to track ../common/common.m4 changes.
* config.in: Ditto.
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
2006-12-21 Hans-Peter Nilsson <hp@axis.com>
* config.in, configure: Regenerate.
2006-10-18 Dave Brolley <brolley@redhat.com>
* Contribute the following changes:
2006-06-14 Dave Brolley <brolley@redhat.com>
* sh64-sim.h (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
(sh64_fpref): New functions.
* sh64.c (sh64_fipr,sh64_fiprs,sh64_fldp,sh64_fstp,sh64_ftrv)
(sh64_fpref): New functions.
(sh_models): Add sh2e, sh2a, sh2a_nofpu, sh4_nofpu, sh4a,
sh4a_nofpu and sh4al.
(sh2e_mach): New MACH.
(sh2a_fpu_mach): New MACH.
(sh2a_nofpu_mach): New MACH.
(sh4_nofpu): New MACH.
(sh4a_mach): New MACH.
(sh4a_nofpu_mach): New MACH.
(sh4al_mach): New MACH.
* Makefile.in (stamp-*): Depend on $(CGEN_CPU_DIR)/sh-sim.cpu. Pass
archfile to CGEN script.
* arch.c: Regenerated.
* arch.h: Regenerated.
* cpu.c: Regenerated.
* cpu.h: Regenerated.
* cpuall.h: Regenerated.
* decode-compact.c: Regenerated.
* decode-compact.h: Regenerated.
* decode-media.c: Regenerated.
* decode-media.h: Regenerated.
* defs-compact.h: Regenerated.
* defs-media.h: Regenerated.
* sem-compact-switch.c: Regenerated.
* sem-compact.c: Regenerated.
* sem-media-switch.c: Regenerated.
* sem-media.c: Regenerated.
* sh-desc.c: Regenerated.
* sh-desc.h: Regenerated.
* sh-opc.h: Regenerated.
2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
* configure: Regenerated.
2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
* configure: Regenerated.
2005-05-02 Corinna Vinschen <vinschen@redhat.com>
* sh-desc.h: Move extern declaration of sh_cgen_ifld_table after
inclusion of cgen.h.
2005-04-15 Corinna Vinschen <vinschen@redhat.com>
* configure.ac: New file.
* configure.in: Remove.
* configure: Regenerate.
* defs-media.h (sem_fields): Add missing sfmt_ldhil member.
* sim-if.c (sim_open): Use struct bfd instead of struct _bfd.
(sim_create_inferior): Ditto.
2004-12-08 Hans-Peter Nilsson <hp@axis.com>
* configure: Regenerate for ../common/aclocal.m4 update.
Fri Feb 21 19:49:45 2003 J"orn Rennecke <joern.rennecke@superh.com>
* sem-media-switch.c, sem-media.c: Regenerate.
2002-06-24 Richard Sandiford <rsandifo@redhat.com>
* sh64.c: Update path of "callback.h".
2002-06-20 Elena Zannoni <ezannoni@redhat.com>
* sh64.c: Include correct file for register numbers.
Fri May 17 14:27:41 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sim-if.c (sh64_disassemble_insn): Use print_insn_sh instead of
print_insn_shl.
2001-07-05 Ben Elliston <bje@redhat.com>
* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
(stamp-desc): Likewise.
(stamp-cpu): Likewise.
(stamp-defs-compact): Likewise.
(stamp-defs-media): Likewise.
(stamp-decode-compact): Likewise.
(stamp-decode-media): Likewise.
2001-03-30 Ben Elliston <bje@redhat.com>
* sim-if.c (sim_open): Set sh64_idesc_{media,compact} to NULL.
* sh64-sim.h (sh64_idesc_{compact,media}): Declare extern.
* sh64.c (sh64_idesc_{compact,media}): Make non-static.
2001-01-30 Ben Elliston <bje@redhat.com>
* sh64.c (SYS_argc, SYS_argn, SYS_argnlen): Define.
(trap_handler): Implement these syscalls.
(count_argc): New function.
2001-01-24 Alexandre Oliva <aoliva@redhat.com>
* sh64.c (trap_handler): Implement time.
* sh64.c (fetch_str): New function.
(trap_handler): Re-implement write, and implement lseek, read,
open and close.
2001-01-18 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
* sh64.c (sh64_fetch_register): When fetching the PC, return the
PC value and set the LSB according to the current ISA.
2001-01-18 Ben Elliston <bje@redhat.com>
* sh64.c (trap_handler): Use sim_engine_halt to indicate a program
has terminated, not exit!
2001-01-12 Ben Elliston <bje@redhat.com>
* sh64.c (sh64_fcnvds): Re-implement.
* sh64.c: Include "bfd.h".
(trap_handler): New function. Consolidate function bodies of
sh64_trapa and sh64_compact_trapa.
(sh64_trapa): Use it.
(sh64_compact_trapa): Likewise.
2001-01-11 Ben Elliston <bje@redhat.com>
* sem-media.c, sem-media-switch.c: Regenerate.
* sem-compact.c, sem-compact-switch.c: Likewise.
* sh64.c (sh64_trapa): Adhere to SH64 sys call conventions.
* cpu.h, sh-desc.c, sh-desc.h, sh-opc.h: Regenerate.
* decode-media.c, decode-media.h, defs-media.h: Likewise.
* sem-compact.c, sem-compact-switch.c: Likewise.
* sem-media.c, sem-media-switch.c: Likewise.
2001-01-10 Ben Elliston <bje@redhat.com>
* sim-main.h (CIA_SET): Encode the current instruction set mode
when setting the cia.
2001-01-08 Ben Elliston <bje@redhat.com>
* sh64.c (sh64_store_register): Do not set insn set mode--allow
sh64_h_pc_set() to do it.
(shmedia_init_cpu): Do not initialise the insn set mode--let the
loader set it based on bit 0 of the executable's starting address.
(shcompact_init_cpu): Likewise.
* mloop-compact.c (sh64_compact_pbb_begin): Emit a warning message
about malformed programs which have illegal insns in delay slots.
(sh64_compact_pbb_cti_chain): Examine the least significant bit of
the new pc, not the current instruction set mode to determine if
the next pbb in the chain will consist of SHmedia instructions.
* mloop-media.c (sh64_media_pbb_cti_chain): Likewise for SHcompact
switches. Set bit 0 when setting the pc for the next SHmedia pbb.
* cpu.c, cpu.h: Regenerate.
* sem-compact.c, sem-compact-switch.c: Likewise.
* sem-media.c, sem-media-switch.c: Likewise.
* sh64.c (sh64_compact_trapa): Use sim_io_write_{stdout,error}(),
not stdio functions to emit output when executing write traps.
2001-01-07 Alexandre Oliva <aoliva@redhat.com>
* sh64.c (sh64_compact_trapa): Support writing to stderr. Flush
output stream after each (compound) write.
2001-01-06 Ben Elliston <bje@redhat.com>
* sem-media.c, sem-media-switch.c: Regenerate.
2001-01-04 Ben Elliston <bje@redhat.com>
* sem-compact.c, sem-compact-switch.c: Regenerate.
* cpu.h: Regenerate.
2001-01-03 Ben Elliston <bje@redhat.com>
* cpu.c, cpu.h: Regenerate.
* sem-media.c, sem-media-switch.c: Likewise.
2001-01-02 Ben Elliston <bje@redhat.com>
* sim-if.c (sh64_disassemble_insn): Set arch and mach fields using
BFD primitives.
* sem-compact.c, sem-compact-switch.c: Regenerate.
2000-12-30 Alexandre Oliva <aoliva@redhat.com>
* sh64.c (sh64_nsb): Re-implement correctly.
2000-12-26 Alexandre Oliva <aoliva@redhat.com>
* sh64.c (sh64_nsb): Re-implement.
2000-12-27 Ben Elliston <bje@redhat.com>
* cpu.c, cpu.h: Regenerate.
* sem-compact.c, sem-compact-switch.c: Likewise.
* sem-media.c, sem-media-switch.c: Likewise.
* sh-desc.c: Likewise.
2000-12-26 Ben Elliston <bje@redhat.com>
* mloop-compact.in, mloop-media.in: Remove.
* mloop-compact.c, mloop-media.c: New files.
* eng-compact.c, eng-media.c: Likewise.
* Makefile.in (mloop-compact.c): Remove target.
(stamp-mloop-compact): Likewise.
(mloop-media.c): Likewise.
(stamp-mloop-media): Likewise.
(sh64-clean): Update.
(stamp-mloop): Remove.
2000-12-23 Ben Elliston <bje@redhat.com>
* sh64.c (sh64_prepare_run): Rename from shmedia_prepare_run.
(shcompact_prepare_run): Remove.
(sh2_mach, sh3_mach, sh3e_mach, sh4_mach, sh5_mach): Update.
2000-12-22 Ben Elliston <bje@redhat.com>
* sh64.c (sh64_idesc_media, sh64_idesc_compact): New variables.
(sh64_dump): Remove.
(sh64_engine_run_full): Only compute idesc tables once.
(sh64_engine_run_fast): Likewise.
(shmedia_prepare_run): Do nothing.
(shcompact_prepare_run): Likewise.
* sem-compact.c, sem-compact-switch.c: Regenerate.
* sem-media.c, sem-media-switch.c: Likewise.
2000-12-19 Ben Elliston <bje@redhat.com>
* sem-media.c, sem-media-switch.c: Regenerate.
2000-12-15 Ben Elliston <bje@redhat.com>
* sh64.c (sh64_store_register): When storing a new PC, set ISA
mode based on the value of bit 0.
* sh64.c: Include "sim-sh64.h" for GDB interfacing.
(sh64_fetch_register): Implement.
(sh64_store_register): Likewise.
* sh64-sim.h (sh64_fmacs): Declare.
(sh64_ftrcdl, sh64_ftrcdq, sh64_ftrcsl): Likewise.
* sem-media.c, sem-media-switch.c: Regenerate.
2000-12-13 Ben Elliston <bje@redhat.com>
* sh64-sim.h (sh64_compact_trapa): Renamed from sh64_trapa.
(sh64_trapa): Renamed from sh64_trap.
* sh64.c (sh64_trapa): Call sh64_compact_trapa for handling.
Apply renaming described above.
* decode-media.c, decode-media.h, defs-media.h: Regenerate.
* sem-media.c sem-media-switch.c: Likewise.
* sh-desc.c, sh-desc.h, sh-opc.h: Likewise.
2000-12-12 Ben Elliston <bje@redhat.com>
* cpu.c, cpu.h, sh-desc.c: Regenerate.
* sem-media.c, sem-media-switch.c: Likewise.
* sem-compact.c, sem-compact-switch.c: Likewise.
* sh64-sim.h (sh64_ftrvs): Declare.
* sh64.c (sh64_ftrvs): Bug fixes.
* sh64.c (sh64_fcmpgtd): Fix order of arguments to sim_fpu_is_gt.
(sh64_fcmpgts): Likewise.
2000-12-11 Ben Elliston <bje@redhat.com>
* decode-media.c, decode-media.h: Regenerate.
* defs-media.h: Likewise.
* sem-media.c, sem-media-switch.c: Likewise.
* sh-desc.c: Likewise.
2000-12-08 Ben Elliston <bje@redhat.com>
* decode-media.c, decode-media.h: Regenerate.
* defs-media.h: Likewise.
* sem-media.c, sem-media-switch.c: Likewise.
2000-12-07 Ben Elliston <bje@redhat.com>
* decode-media.c, decode-media.h: Regenerate.
* sem-media.c, sem-media-switch.c: Likewise.
* defs-media.h: Regenete.
* decode-compact.c, decode-media.c: Likewise.
2000-12-06 Ben Elliston <bje@redhat.com>
* sh64.c (sh64_fcmpund): Return a BI.
(sh64_fcmpuns): Likewise.
(sh64_nsb): Treat source value as unsigned.
(sh64_compact_model_insn_before): New function.
(sh64_media_model_insn_before): Likewise.
(sh64_compact_model_insn_after): Likewise.
(sh64_media_model_insn_after): Likewise.
(sh_models): Use sh5_mach for "sh5".
* sh64-sim.h: Add missing function prototypes.
* cpu.c, cpu.h, defs-media.h, sh-desc.c: Regenerate.
* decode-media.c, decode-media.h: Likewise.
* sem-media.c, sem-media-switch.c: Likewise.
2000-12-05 Ben Elliston <bje@redhat.com>
* mloop-compact.in, mloop-media.in: Use @prefix@.
* Makefile.in (stamp-mloop-compact): Pass -outfile-suffix option
to make generated files safe in the presence of parallel makes.
(stamp-mloop-media): Likewise.
* decode-media.c, defs-media.h: Regenerate.
2000-12-04 Ben Elliston <bje@redhat.com>
* sh64-sim.h: Add function prototypes from sh64.c.
* Makefile.in (SH64_OBJS): Add ISA variant objects.
(SIM_EXTRA_DEPS): Do not depend on opcodes headers.
(SH64_INCLUDE_DEPS): Update for ISA variants.
(stamp-mloop-compact, stamp-mloop-media): New targets.
(decode-compact.o, sem-compact.o): New rules.
(decode-media.o, sem-media.o): Likewise.
(sh64-clean): Update.
(stamp-all, stamp-mloop, stamp-decode, stamp-defs): New targets.
(stamp-desc, stamp-cpu): Likewise.
(stamp-defs-compact, stamp-defs-media): Likewise.
(stamp-decode-compact, stamp-decode-media): Likewise.
* defs-compact.h, defs-media.h: Regenerate.
2000-12-03 Ben Elliston <bje@redhat.com>
* sh64-sim.h (sh64_fcmpeqd, sh64_fcmpeqs): Declare.
(sh64_fcmpged, sh64_fcmpges): Likewise.
(sh64_fcmpgtd, sh64_fcmpgts): Likewise.
* sh64.c (sh64_endian): New function.
(sh64_fcmpeqd, sh64_fcmpeqs): Return a BI.
(sh64_fcmpged, sh64_fcmpges): Likewise.
(sh64_fcmpgtd, sh64_fcmpgts): Likewise.
(sh64_trap): Implement a basic syscall facility.
(sh64_trapa): Exit with return code in R5, not 0.
(sh64_model_sh5_u_exec): Remove.
(sh64_engine_run_full): New function.
(sh64_engine_run_fast): Likewise.
(shmedia_prepare_run): Likewise.
(shcompact_prepare_run): Likewise.
(sh64_get_idata): Likewise.
(sh64_init_cpu): Likewise.
(shmedia_init_cpu): Likewise.
(shcompact_init_cpu): Likewise.
(sh64_model_init): Likewise.
(sh_models): Define.
(sh5_imp_properties): Likewise.
(sh2_mach, sh3_mach, sh4_mach, sh5_mach): Define.
* sem-compact.c, sem-compact-switch.c: Regenerate.
2000-12-01 Ben Elliston <bje@redhat.com>
* sh64-sim.h (sh64_endian): Declare.
* sim-main.h (sim_cia): Use UDI, not USI.
(WITH_PROFILE_MODEL_P): Remove.
* sim-if.c (sim_sh64_disassemble_insn): Remove.
(sh64_disassemble_insn): New function.
(sim_open): Use as this CPU's disassembler.
* eng.h: New file.
* decode.h (WITH_PROFILE_MODEL_P): Undefine.
* decode-compact.c, decode-media.c: Regenerate.
* defs-compact.h, defs-media.h: Likewise.
* sem-compact.c, sem-compact-switch.c: Likewise.
* sh-desc.c, sh-desc.h: Likewise.
* cpu.c, cpu.h, cpuall.h: Likewise.
2000-11-30 Ben Elliston <bje@redhat.com>
* arch.c, sh-desc.c, sh-desc.h: Regenerate.
* tconfig.in (SIM_HAVE_BIENDIAN): Define.
* configure.in (SIM_AC_OPTION_BIGENDIAN): Do not hard-wire a
target byte order, but default to big endian.
* configure: Regenerate.
2000-11-27 Ben Elliston <bje@redhat.com>
* sim-main.h (WITH_PROFILE_MODEL_P): Define.
* sh64-sim.h (ISM_COMPACT, ISM_MEDIA): New enums.
* sh-desc.c, sh-desc.h: Regenerate.
* arch.c, cpu.h, cpuall.h: Regenerate.
* decode.h (WITH_PROFILE_MODEL_P): Remove.
* mloop-compact.in, mloop-media.in: New files.
* decode.h: Likewise.
2000-11-26 Ben Elliston <bje@redhat.com>
* sem-compact.c, sem-compact-switch.c: Generate.
* sem-media.c, sem-media-switch.c: Likewise.
2000-11-25 Ben Elliston <bje@redhat.com>
* sh-desc.c, sh-desc.h, sh-opc.h: Generate.
* arch.c, arch.h, cpuall.h, cpu.c, cpu.h: Generate.
* decode-compact.c, decode-compact.h: Likewise.
* decode-media.c, decode-media.h: Likewise.
* sh64-sim.h: New file.
* sim-main.h: Likewise.
2000-11-22 Ben Elliston <bje@redhat.com>
* sim-if.c: New file.
* sh64.c: Likewise.
2000-11-16 Ben Elliston <bje@redhat.com>
* config.in: New file.
* tconfig.in: Likewise.
* configure.in: Likewise.
* configure: Generate.
* Makefile.in: New file.

150
sim/sh64/Makefile.in
View File

@ -1,150 +0,0 @@
# Makefile template for Configure for the SH64 simulator
# Copyright (C) 2000-2021 Free Software Foundation, Inc.
# Contributed by Red Hat, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
## COMMON_PRE_CONFIG_FRAG
SH64_OBJS = sh64.o cpu.o sh-desc.o \
decode-compact.o sem-compact.o mloop-compact.o \
decode-media.o sem-media.o mloop-media.o
SIM_OBJS = \
$(SIM_NEW_COMMON_OBJS) \
cgen-utils.o cgen-trace.o cgen-scache.o \
cgen-run.o \
sim-if.o arch.o \
$(SH64_OBJS)
# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
$(CGEN_INCLUDE_DEPS) \
arch.h cpuall.h sh64-sim.h sh-desc.h sh-opc.h
SIM_EXTRA_CFLAGS =
SIM_EXTRA_CLEAN = sh64-clean
## COMMON_POST_CONFIG_FRAG
arch = sh
sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
arch.o: arch.c $(SIM_MAIN_DEPS)
sh-desc.o: sh-desc.c $(SIM_MAIN_DEPS)
devices.o: devices.c $(SIM_MAIN_DEPS)
# SH64 objs
SH64_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpu.h decode.h \
decode-compact.h eng-compact.h defs-compact.h \
decode-media.h eng-media.h defs-media.h
sh64.o: sh64.c $(SH64_INCLUDE_DEPS)
mloop-compact.o: mloop-compact.c sem-compact-switch.c $(SH64_INCLUDE_DEPS)
$(CC) -c $(srcdir)/mloop-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
mloop-media.o: mloop-media.c sem-media-switch.c $(SH64_INCLUDE_DEPS)
$(CC) -c $(srcdir)/mloop-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
cpu.o: $(srcdir)/cpu.c $(SH64_INCLUDE_DEPS)
decode-compact.o: decode-compact.c $(SH64_INCLUDE_DEPS)
$(CC) -c $(srcdir)/decode-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
sem-compact.o: sem-compact.c $(SH64_INCLUDE_DEPS)
$(CC) -c $(srcdir)/sem-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
decode-media.o: decode-media.c $(SH64_INCLUDE_DEPS)
$(CC) -c $(srcdir)/decode-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
sem-media.o: sem-media.c $(SH64_INCLUDE_DEPS)
$(CC) -c $(srcdir)/sem-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
sh64-clean:
rm -f tmp-*
rm -f stamp-defs-{compact,media}
rm -f stamp-arch stamp-desc stamp-cpu stamp-decode-{compact,media}
# cgen support, enable with --enable-cgen-maint
CGEN_MAINT = ; @true
# The following line is commented in or out depending upon --enable-cgen-maint.
@CGEN_MAINT@CGEN_MAINT =
# Utility rules for humans.
.PHONY: stamp-all stamp-decode stamp-defs
stamp-all: stamp-arch stamp-desc stamp-cpu stamp-decode stamp-defs
stamp-decode: stamp-decode-compact stamp-decode-media
stamp-defs: stamp-defs-compact stamp-defs-media
# NOTE: Generated source files are specified as full paths,
# e.g. $(srcdir)/arch.c, because make may decide the files live
# in objdir otherwise.
stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu \
FLAGS="with-scache"
touch $@
$(srcdir)/arch.h $(srcdir)/arch.c $(srcdir)/cpuall.h: $(CGEN_MAINT) stamp-arch
@true
stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
$(srcdir)/sh-desc.h $(srcdir)/sh-desc.c $(srcdir)/sh-opc.h: $(CGEN_MAINT) stamp-desc
@true
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache" archfile=$(CGEN_CPU_DIR)/sh.cpu
rm -f $(srcdir)/model.c
touch $@
$(srcdir)/cpu.h $(srcdir)/cpu.c: $(CGEN_MAINT) stamp-cpu
@true
stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
$(srcdir)/defs-compact.h: $(CGEN_MAINT) stamp-defs-compact
@true
stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
$(srcdir)/defs-media.h: $(CGEN_MAINT) stamp-defs-media
stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \
archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
$(srcdir)/sem-compact.c $(srcdir)/sem-compact-switch.c $(srcdir)/decode-compact.c $(srcdir)/decode-compact.h: $(CGEN_MAINT) stamp-decode-compact
@true
stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh-sim.cpu Makefile
$(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" \
archfile=$(CGEN_CPU_DIR)/sh.cpu
touch $@
$(srcdir)/sem-media.c $(srcdir)/sem-media-switch.c $(srcdir)/decode-media.c $(srcdir)/decode-media.h: $(CGEN_MAINT) stamp-decode-media
@true

119
sim/sh64/aclocal.m4 vendored
View File

@ -1,119 +0,0 @@
# generated automatically by aclocal 1.15.1 -*- Autoconf -*-
# Copyright (C) 1996-2017 Free Software Foundation, Inc.
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE.
m4_ifndef([AC_CONFIG_MACRO_DIRS], [m4_defun([_AM_CONFIG_MACRO_DIRS], [])m4_defun([AC_CONFIG_MACRO_DIRS], [_AM_CONFIG_MACRO_DIRS($@)])])
# AM_CONDITIONAL -*- Autoconf -*-
# Copyright (C) 1997-2017 Free Software Foundation, Inc.
#
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# AM_CONDITIONAL(NAME, SHELL-CONDITION)
# -------------------------------------
# Define a conditional.
AC_DEFUN([AM_CONDITIONAL],
[AC_PREREQ([2.52])dnl
m4_if([$1], [TRUE], [AC_FATAL([$0: invalid condition: $1])],
[$1], [FALSE], [AC_FATAL([$0: invalid condition: $1])])dnl
AC_SUBST([$1_TRUE])dnl
AC_SUBST([$1_FALSE])dnl
_AM_SUBST_NOTMAKE([$1_TRUE])dnl
_AM_SUBST_NOTMAKE([$1_FALSE])dnl
m4_define([_AM_COND_VALUE_$1], [$2])dnl
if $2; then
$1_TRUE=
$1_FALSE='#'
else
$1_TRUE='#'
$1_FALSE=
fi
AC_CONFIG_COMMANDS_PRE(
[if test -z "${$1_TRUE}" && test -z "${$1_FALSE}"; then
AC_MSG_ERROR([[conditional "$1" was never defined.
Usually this means the macro was only invoked conditionally.]])
fi])])
# Copyright (C) 2003-2017 Free Software Foundation, Inc.
#
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# Check whether the underlying file-system supports filenames
# with a leading dot. For instance MS-DOS doesn't.
AC_DEFUN([AM_SET_LEADING_DOT],
[rm -rf .tst 2>/dev/null
mkdir .tst 2>/dev/null
if test -d .tst; then
am__leading_dot=.
else
am__leading_dot=_
fi
rmdir .tst 2>/dev/null
AC_SUBST([am__leading_dot])])
# Add --enable-maintainer-mode option to configure. -*- Autoconf -*-
# From Jim Meyering
# Copyright (C) 1996-2017 Free Software Foundation, Inc.
#
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# AM_MAINTAINER_MODE([DEFAULT-MODE])
# ----------------------------------
# Control maintainer-specific portions of Makefiles.
# Default is to disable them, unless 'enable' is passed literally.
# For symmetry, 'disable' may be passed as well. Anyway, the user
# can override the default with the --enable/--disable switch.
AC_DEFUN([AM_MAINTAINER_MODE],
[m4_case(m4_default([$1], [disable]),
[enable], [m4_define([am_maintainer_other], [disable])],
[disable], [m4_define([am_maintainer_other], [enable])],
[m4_define([am_maintainer_other], [enable])
m4_warn([syntax], [unexpected argument to AM@&t@_MAINTAINER_MODE: $1])])
AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles])
dnl maintainer-mode's default is 'disable' unless 'enable' is passed
AC_ARG_ENABLE([maintainer-mode],
[AS_HELP_STRING([--]am_maintainer_other[-maintainer-mode],
am_maintainer_other[ make rules and dependencies not useful
(and sometimes confusing) to the casual installer])],
[USE_MAINTAINER_MODE=$enableval],
[USE_MAINTAINER_MODE=]m4_if(am_maintainer_other, [enable], [no], [yes]))
AC_MSG_RESULT([$USE_MAINTAINER_MODE])
AM_CONDITIONAL([MAINTAINER_MODE], [test $USE_MAINTAINER_MODE = yes])
MAINT=$MAINTAINER_MODE_TRUE
AC_SUBST([MAINT])dnl
]
)
# Copyright (C) 2006-2017 Free Software Foundation, Inc.
#
# This file is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
# _AM_SUBST_NOTMAKE(VARIABLE)
# ---------------------------
# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in.
# This macro is traced by Automake.
AC_DEFUN([_AM_SUBST_NOTMAKE])
# AM_SUBST_NOTMAKE(VARIABLE)
# --------------------------
# Public sister of _AM_SUBST_NOTMAKE.
AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)])

67
sim/sh64/arch.c
View File

@ -1,67 +0,0 @@
/* Simulator support for sh.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "sim-main.h"
#include "bfd.h"
const SIM_MACH *sim_machs[] =
{
#ifdef HAVE_CPU_SH64
& sh2_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh2e_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh2a_fpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh2a_nofpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh3_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh3e_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4_nofpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4a_nofpu_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4a_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh4al_mach,
#endif
#ifdef HAVE_CPU_SH64
& sh5_mach,
#endif
0
};

216
sim/sh64/arch.h
View File

@ -1,216 +0,0 @@
/* Simulator header for sh.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SH_ARCH_H
#define SH_ARCH_H
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_SH2A_NOFPU, MODEL_SH2A_FPU, MODEL_SH4_NOFPU, MODEL_SH4
, MODEL_SH4A_NOFPU, MODEL_SH4A, MODEL_SH4AL, MODEL_SH5
, MODEL_SH5_MEDIA, MODEL_SH2, MODEL_SH2E, MODEL_SH3
, MODEL_SH3E, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
/* Enum declaration for unit types. */
typedef enum unit_type {
UNIT_NONE, UNIT_SH2A_NOFPU_U_MULR_GR, UNIT_SH2A_NOFPU_U_MULR, UNIT_SH2A_NOFPU_U_TRAP
, UNIT_SH2A_NOFPU_U_WRITE_BACK, UNIT_SH2A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_NOFPU_U_SHIFT, UNIT_SH2A_NOFPU_U_TAS
, UNIT_SH2A_NOFPU_U_MULSW, UNIT_SH2A_NOFPU_U_MULL, UNIT_SH2A_NOFPU_U_DMUL, UNIT_SH2A_NOFPU_U_MACL
, UNIT_SH2A_NOFPU_U_MACW, UNIT_SH2A_NOFPU_U_MULTIPLY, UNIT_SH2A_NOFPU_U_SET_MAC, UNIT_SH2A_NOFPU_U_LOAD_MAC
, UNIT_SH2A_NOFPU_U_LOAD_VBR, UNIT_SH2A_NOFPU_U_LOAD_GBR, UNIT_SH2A_NOFPU_U_USE_GR, UNIT_SH2A_NOFPU_U_LOAD_GR
, UNIT_SH2A_NOFPU_U_STC_VBR, UNIT_SH2A_NOFPU_U_LDCL_VBR, UNIT_SH2A_NOFPU_U_LDCL, UNIT_SH2A_NOFPU_U_USE_TBIT
, UNIT_SH2A_NOFPU_U_LDC_GBR, UNIT_SH2A_NOFPU_U_LDC_SR, UNIT_SH2A_NOFPU_U_SET_SR_BIT, UNIT_SH2A_NOFPU_U_USE_PR
, UNIT_SH2A_NOFPU_U_LOAD_PR, UNIT_SH2A_NOFPU_U_STS_PR, UNIT_SH2A_NOFPU_U_LDS_PR, UNIT_SH2A_NOFPU_U_MEMORY_ACCESS
, UNIT_SH2A_NOFPU_U_LOGIC_B, UNIT_SH2A_NOFPU_U_JSR, UNIT_SH2A_NOFPU_U_JMP, UNIT_SH2A_NOFPU_U_BRANCH
, UNIT_SH2A_NOFPU_U_SX, UNIT_SH2A_NOFPU_U_EXEC, UNIT_SH2A_FPU_U_USE_DR, UNIT_SH2A_FPU_U_LOAD_DR
, UNIT_SH2A_FPU_U_SET_DR, UNIT_SH2A_FPU_U_MULR_GR, UNIT_SH2A_FPU_U_MULR, UNIT_SH2A_FPU_U_FCNV
, UNIT_SH2A_FPU_U_FCMP, UNIT_SH2A_FPU_U_FSQRT, UNIT_SH2A_FPU_U_FDIV, UNIT_SH2A_FPU_U_FPU_LOAD_GR
, UNIT_SH2A_FPU_U_USE_FPSCR, UNIT_SH2A_FPU_U_LDSL_FPSCR, UNIT_SH2A_FPU_U_LDS_FPSCR, UNIT_SH2A_FPU_U_USE_FPUL
, UNIT_SH2A_FPU_U_FLDS_FPUL, UNIT_SH2A_FPU_U_LOAD_FPUL, UNIT_SH2A_FPU_U_SET_FPUL, UNIT_SH2A_FPU_U_FPU_MEMORY_ACCESS
, UNIT_SH2A_FPU_U_USE_FR, UNIT_SH2A_FPU_U_SET_FR_0, UNIT_SH2A_FPU_U_SET_FR, UNIT_SH2A_FPU_U_LOAD_FR
, UNIT_SH2A_FPU_U_MAYBE_FPU, UNIT_SH2A_FPU_U_FPU, UNIT_SH2A_FPU_U_TRAP, UNIT_SH2A_FPU_U_WRITE_BACK
, UNIT_SH2A_FPU_U_USE_MULTIPLY_RESULT, UNIT_SH2A_FPU_U_SHIFT, UNIT_SH2A_FPU_U_TAS, UNIT_SH2A_FPU_U_MULSW
, UNIT_SH2A_FPU_U_MULL, UNIT_SH2A_FPU_U_DMUL, UNIT_SH2A_FPU_U_MACL, UNIT_SH2A_FPU_U_MACW
, UNIT_SH2A_FPU_U_MULTIPLY, UNIT_SH2A_FPU_U_SET_MAC, UNIT_SH2A_FPU_U_LOAD_MAC, UNIT_SH2A_FPU_U_LOAD_VBR
, UNIT_SH2A_FPU_U_LOAD_GBR, UNIT_SH2A_FPU_U_USE_GR, UNIT_SH2A_FPU_U_LOAD_GR, UNIT_SH2A_FPU_U_STC_VBR
, UNIT_SH2A_FPU_U_LDCL_VBR, UNIT_SH2A_FPU_U_LDCL, UNIT_SH2A_FPU_U_USE_TBIT, UNIT_SH2A_FPU_U_LDC_GBR
, UNIT_SH2A_FPU_U_LDC_SR, UNIT_SH2A_FPU_U_SET_SR_BIT, UNIT_SH2A_FPU_U_USE_PR, UNIT_SH2A_FPU_U_LOAD_PR
, UNIT_SH2A_FPU_U_STS_PR, UNIT_SH2A_FPU_U_LDS_PR, UNIT_SH2A_FPU_U_MEMORY_ACCESS, UNIT_SH2A_FPU_U_LOGIC_B
, UNIT_SH2A_FPU_U_JSR, UNIT_SH2A_FPU_U_JMP, UNIT_SH2A_FPU_U_BRANCH, UNIT_SH2A_FPU_U_SX
, UNIT_SH2A_FPU_U_EXEC, UNIT_SH4_NOFPU_U_OCB, UNIT_SH4_NOFPU_U_MULR_GR, UNIT_SH4_NOFPU_U_MULR
, UNIT_SH4_NOFPU_U_TRAP, UNIT_SH4_NOFPU_U_WRITE_BACK, UNIT_SH4_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4_NOFPU_U_SHIFT
, UNIT_SH4_NOFPU_U_TAS, UNIT_SH4_NOFPU_U_MULSW, UNIT_SH4_NOFPU_U_MULL, UNIT_SH4_NOFPU_U_DMUL
, UNIT_SH4_NOFPU_U_MACL, UNIT_SH4_NOFPU_U_MACW, UNIT_SH4_NOFPU_U_MULTIPLY, UNIT_SH4_NOFPU_U_SET_MAC
, UNIT_SH4_NOFPU_U_LOAD_MAC, UNIT_SH4_NOFPU_U_LOAD_VBR, UNIT_SH4_NOFPU_U_LOAD_GBR, UNIT_SH4_NOFPU_U_USE_GR
, UNIT_SH4_NOFPU_U_LOAD_GR, UNIT_SH4_NOFPU_U_STC_VBR, UNIT_SH4_NOFPU_U_LDCL_VBR, UNIT_SH4_NOFPU_U_LDCL
, UNIT_SH4_NOFPU_U_USE_TBIT, UNIT_SH4_NOFPU_U_LDC_GBR, UNIT_SH4_NOFPU_U_LDC_SR, UNIT_SH4_NOFPU_U_SET_SR_BIT
, UNIT_SH4_NOFPU_U_USE_PR, UNIT_SH4_NOFPU_U_LOAD_PR, UNIT_SH4_NOFPU_U_STS_PR, UNIT_SH4_NOFPU_U_LDS_PR
, UNIT_SH4_NOFPU_U_MEMORY_ACCESS, UNIT_SH4_NOFPU_U_LOGIC_B, UNIT_SH4_NOFPU_U_JSR, UNIT_SH4_NOFPU_U_JMP
, UNIT_SH4_NOFPU_U_BRANCH, UNIT_SH4_NOFPU_U_SX, UNIT_SH4_NOFPU_U_EXEC, UNIT_SH4_U_FTRV
, UNIT_SH4_U_FIPR, UNIT_SH4_U_OCB, UNIT_SH4_U_MULR_GR, UNIT_SH4_U_MULR
, UNIT_SH4_U_USE_DR, UNIT_SH4_U_LOAD_DR, UNIT_SH4_U_SET_DR, UNIT_SH4_U_FCNV
, UNIT_SH4_U_FCMP, UNIT_SH4_U_FSQRT, UNIT_SH4_U_FDIV, UNIT_SH4_U_FPU_LOAD_GR
, UNIT_SH4_U_USE_FPSCR, UNIT_SH4_U_LDSL_FPSCR, UNIT_SH4_U_LDS_FPSCR, UNIT_SH4_U_USE_FPUL
, UNIT_SH4_U_FLDS_FPUL, UNIT_SH4_U_LOAD_FPUL, UNIT_SH4_U_SET_FPUL, UNIT_SH4_U_FPU_MEMORY_ACCESS
, UNIT_SH4_U_USE_FR, UNIT_SH4_U_SET_FR_0, UNIT_SH4_U_SET_FR, UNIT_SH4_U_LOAD_FR
, UNIT_SH4_U_MAYBE_FPU, UNIT_SH4_U_FPU, UNIT_SH4_U_TRAP, UNIT_SH4_U_WRITE_BACK
, UNIT_SH4_U_USE_MULTIPLY_RESULT, UNIT_SH4_U_SHIFT, UNIT_SH4_U_TAS, UNIT_SH4_U_MULSW
, UNIT_SH4_U_MULL, UNIT_SH4_U_DMUL, UNIT_SH4_U_MACL, UNIT_SH4_U_MACW
, UNIT_SH4_U_MULTIPLY, UNIT_SH4_U_SET_MAC, UNIT_SH4_U_LOAD_MAC, UNIT_SH4_U_LOAD_VBR
, UNIT_SH4_U_LOAD_GBR, UNIT_SH4_U_USE_GR, UNIT_SH4_U_LOAD_GR, UNIT_SH4_U_STC_VBR
, UNIT_SH4_U_LDCL_VBR, UNIT_SH4_U_LDCL, UNIT_SH4_U_USE_TBIT, UNIT_SH4_U_LDC_GBR
, UNIT_SH4_U_LDC_SR, UNIT_SH4_U_SET_SR_BIT, UNIT_SH4_U_USE_PR, UNIT_SH4_U_LOAD_PR
, UNIT_SH4_U_STS_PR, UNIT_SH4_U_LDS_PR, UNIT_SH4_U_MEMORY_ACCESS, UNIT_SH4_U_LOGIC_B
, UNIT_SH4_U_JSR, UNIT_SH4_U_JMP, UNIT_SH4_U_BRANCH, UNIT_SH4_U_SX
, UNIT_SH4_U_EXEC, UNIT_SH4A_NOFPU_U_OCB, UNIT_SH4A_NOFPU_U_MULR_GR, UNIT_SH4A_NOFPU_U_MULR
, UNIT_SH4A_NOFPU_U_FCNV, UNIT_SH4A_NOFPU_U_FCMP, UNIT_SH4A_NOFPU_U_FSQRT, UNIT_SH4A_NOFPU_U_FDIV
, UNIT_SH4A_NOFPU_U_FPU_LOAD_GR, UNIT_SH4A_NOFPU_U_USE_FPSCR, UNIT_SH4A_NOFPU_U_LDSL_FPSCR, UNIT_SH4A_NOFPU_U_LDS_FPSCR
, UNIT_SH4A_NOFPU_U_USE_FPUL, UNIT_SH4A_NOFPU_U_FLDS_FPUL, UNIT_SH4A_NOFPU_U_LOAD_FPUL, UNIT_SH4A_NOFPU_U_SET_FPUL
, UNIT_SH4A_NOFPU_U_FPU_MEMORY_ACCESS, UNIT_SH4A_NOFPU_U_USE_FR, UNIT_SH4A_NOFPU_U_SET_FR_0, UNIT_SH4A_NOFPU_U_SET_FR
, UNIT_SH4A_NOFPU_U_LOAD_FR, UNIT_SH4A_NOFPU_U_MAYBE_FPU, UNIT_SH4A_NOFPU_U_FPU, UNIT_SH4A_NOFPU_U_TRAP
, UNIT_SH4A_NOFPU_U_WRITE_BACK, UNIT_SH4A_NOFPU_U_USE_MULTIPLY_RESULT, UNIT_SH4A_NOFPU_U_SHIFT, UNIT_SH4A_NOFPU_U_TAS
, UNIT_SH4A_NOFPU_U_MULSW, UNIT_SH4A_NOFPU_U_MULL, UNIT_SH4A_NOFPU_U_DMUL, UNIT_SH4A_NOFPU_U_MACL
, UNIT_SH4A_NOFPU_U_MACW, UNIT_SH4A_NOFPU_U_MULTIPLY, UNIT_SH4A_NOFPU_U_SET_MAC, UNIT_SH4A_NOFPU_U_LOAD_MAC
, UNIT_SH4A_NOFPU_U_LOAD_VBR, UNIT_SH4A_NOFPU_U_LOAD_GBR, UNIT_SH4A_NOFPU_U_USE_GR, UNIT_SH4A_NOFPU_U_LOAD_GR
, UNIT_SH4A_NOFPU_U_STC_VBR, UNIT_SH4A_NOFPU_U_LDCL_VBR, UNIT_SH4A_NOFPU_U_LDCL, UNIT_SH4A_NOFPU_U_USE_TBIT
, UNIT_SH4A_NOFPU_U_LDC_GBR, UNIT_SH4A_NOFPU_U_LDC_SR, UNIT_SH4A_NOFPU_U_SET_SR_BIT, UNIT_SH4A_NOFPU_U_USE_PR
, UNIT_SH4A_NOFPU_U_LOAD_PR, UNIT_SH4A_NOFPU_U_STS_PR, UNIT_SH4A_NOFPU_U_LDS_PR, UNIT_SH4A_NOFPU_U_MEMORY_ACCESS
, UNIT_SH4A_NOFPU_U_LOGIC_B, UNIT_SH4A_NOFPU_U_JSR, UNIT_SH4A_NOFPU_U_JMP, UNIT_SH4A_NOFPU_U_BRANCH
, UNIT_SH4A_NOFPU_U_SX, UNIT_SH4A_NOFPU_U_EXEC, UNIT_SH4A_U_FTRV, UNIT_SH4A_U_FIPR
, UNIT_SH4A_U_OCB, UNIT_SH4A_U_MULR_GR, UNIT_SH4A_U_MULR, UNIT_SH4A_U_FCNV
, UNIT_SH4A_U_FCMP, UNIT_SH4A_U_FSQRT, UNIT_SH4A_U_FDIV, UNIT_SH4A_U_FPU_LOAD_GR
, UNIT_SH4A_U_USE_FPSCR, UNIT_SH4A_U_LDSL_FPSCR, UNIT_SH4A_U_LDS_FPSCR, UNIT_SH4A_U_USE_FPUL
, UNIT_SH4A_U_FLDS_FPUL, UNIT_SH4A_U_LOAD_FPUL, UNIT_SH4A_U_SET_FPUL, UNIT_SH4A_U_FPU_MEMORY_ACCESS
, UNIT_SH4A_U_USE_FR, UNIT_SH4A_U_SET_FR_0, UNIT_SH4A_U_SET_FR, UNIT_SH4A_U_LOAD_FR
, UNIT_SH4A_U_MAYBE_FPU, UNIT_SH4A_U_FPU, UNIT_SH4A_U_TRAP, UNIT_SH4A_U_WRITE_BACK
, UNIT_SH4A_U_USE_MULTIPLY_RESULT, UNIT_SH4A_U_SHIFT, UNIT_SH4A_U_TAS, UNIT_SH4A_U_MULSW
, UNIT_SH4A_U_MULL, UNIT_SH4A_U_DMUL, UNIT_SH4A_U_MACL, UNIT_SH4A_U_MACW
, UNIT_SH4A_U_MULTIPLY, UNIT_SH4A_U_SET_MAC, UNIT_SH4A_U_LOAD_MAC, UNIT_SH4A_U_LOAD_VBR
, UNIT_SH4A_U_LOAD_GBR, UNIT_SH4A_U_USE_GR, UNIT_SH4A_U_LOAD_GR, UNIT_SH4A_U_STC_VBR
, UNIT_SH4A_U_LDCL_VBR, UNIT_SH4A_U_LDCL, UNIT_SH4A_U_USE_TBIT, UNIT_SH4A_U_LDC_GBR
, UNIT_SH4A_U_LDC_SR, UNIT_SH4A_U_SET_SR_BIT, UNIT_SH4A_U_USE_PR, UNIT_SH4A_U_LOAD_PR
, UNIT_SH4A_U_STS_PR, UNIT_SH4A_U_LDS_PR, UNIT_SH4A_U_MEMORY_ACCESS, UNIT_SH4A_U_LOGIC_B
, UNIT_SH4A_U_JSR, UNIT_SH4A_U_JMP, UNIT_SH4A_U_BRANCH, UNIT_SH4A_U_SX
, UNIT_SH4A_U_EXEC, UNIT_SH4AL_U_OCB, UNIT_SH4AL_U_MULR_GR, UNIT_SH4AL_U_MULR
, UNIT_SH4AL_U_FCNV, UNIT_SH4AL_U_FCMP, UNIT_SH4AL_U_FSQRT, UNIT_SH4AL_U_FDIV
, UNIT_SH4AL_U_FPU_LOAD_GR, UNIT_SH4AL_U_USE_FPSCR, UNIT_SH4AL_U_LDSL_FPSCR, UNIT_SH4AL_U_LDS_FPSCR
, UNIT_SH4AL_U_USE_FPUL, UNIT_SH4AL_U_FLDS_FPUL, UNIT_SH4AL_U_LOAD_FPUL, UNIT_SH4AL_U_SET_FPUL
, UNIT_SH4AL_U_FPU_MEMORY_ACCESS, UNIT_SH4AL_U_USE_FR, UNIT_SH4AL_U_SET_FR_0, UNIT_SH4AL_U_SET_FR
, UNIT_SH4AL_U_LOAD_FR, UNIT_SH4AL_U_MAYBE_FPU, UNIT_SH4AL_U_FPU, UNIT_SH4AL_U_TRAP
, UNIT_SH4AL_U_WRITE_BACK, UNIT_SH4AL_U_USE_MULTIPLY_RESULT, UNIT_SH4AL_U_SHIFT, UNIT_SH4AL_U_TAS
, UNIT_SH4AL_U_MULSW, UNIT_SH4AL_U_MULL, UNIT_SH4AL_U_DMUL, UNIT_SH4AL_U_MACL
, UNIT_SH4AL_U_MACW, UNIT_SH4AL_U_MULTIPLY, UNIT_SH4AL_U_SET_MAC, UNIT_SH4AL_U_LOAD_MAC
, UNIT_SH4AL_U_LOAD_VBR, UNIT_SH4AL_U_LOAD_GBR, UNIT_SH4AL_U_USE_GR, UNIT_SH4AL_U_LOAD_GR
, UNIT_SH4AL_U_STC_VBR, UNIT_SH4AL_U_LDCL_VBR, UNIT_SH4AL_U_LDCL, UNIT_SH4AL_U_USE_TBIT
, UNIT_SH4AL_U_LDC_GBR, UNIT_SH4AL_U_LDC_SR, UNIT_SH4AL_U_SET_SR_BIT, UNIT_SH4AL_U_USE_PR
, UNIT_SH4AL_U_LOAD_PR, UNIT_SH4AL_U_STS_PR, UNIT_SH4AL_U_LDS_PR, UNIT_SH4AL_U_MEMORY_ACCESS
, UNIT_SH4AL_U_LOGIC_B, UNIT_SH4AL_U_JSR, UNIT_SH4AL_U_JMP, UNIT_SH4AL_U_BRANCH
, UNIT_SH4AL_U_SX, UNIT_SH4AL_U_EXEC, UNIT_SH5_U_FTRV, UNIT_SH5_U_FIPR
, UNIT_SH5_U_OCB, UNIT_SH5_U_MULR_GR, UNIT_SH5_U_MULR, UNIT_SH5_U_USE_DR
, UNIT_SH5_U_LOAD_DR, UNIT_SH5_U_SET_DR, UNIT_SH5_U_FCNV, UNIT_SH5_U_FCMP
, UNIT_SH5_U_FSQRT, UNIT_SH5_U_FDIV, UNIT_SH5_U_FPU_LOAD_GR, UNIT_SH5_U_USE_FPSCR
, UNIT_SH5_U_LDSL_FPSCR, UNIT_SH5_U_LDS_FPSCR, UNIT_SH5_U_USE_FPUL, UNIT_SH5_U_FLDS_FPUL
, UNIT_SH5_U_LOAD_FPUL, UNIT_SH5_U_SET_FPUL, UNIT_SH5_U_FPU_MEMORY_ACCESS, UNIT_SH5_U_USE_FR
, UNIT_SH5_U_SET_FR_0, UNIT_SH5_U_SET_FR, UNIT_SH5_U_LOAD_FR, UNIT_SH5_U_MAYBE_FPU
, UNIT_SH5_U_FPU, UNIT_SH5_U_TRAP, UNIT_SH5_U_WRITE_BACK, UNIT_SH5_U_USE_MULTIPLY_RESULT
, UNIT_SH5_U_SHIFT, UNIT_SH5_U_TAS, UNIT_SH5_U_MULSW, UNIT_SH5_U_MULL
, UNIT_SH5_U_DMUL, UNIT_SH5_U_MACL, UNIT_SH5_U_MACW, UNIT_SH5_U_MULTIPLY
, UNIT_SH5_U_SET_MAC, UNIT_SH5_U_LOAD_MAC, UNIT_SH5_U_LOAD_VBR, UNIT_SH5_U_LOAD_GBR
, UNIT_SH5_U_USE_GR, UNIT_SH5_U_LOAD_GR, UNIT_SH5_U_STC_VBR, UNIT_SH5_U_LDCL_VBR
, UNIT_SH5_U_LDCL, UNIT_SH5_U_USE_TBIT, UNIT_SH5_U_LDC_GBR, UNIT_SH5_U_LDC_SR
, UNIT_SH5_U_SET_SR_BIT, UNIT_SH5_U_USE_PR, UNIT_SH5_U_LOAD_PR, UNIT_SH5_U_STS_PR
, UNIT_SH5_U_LDS_PR, UNIT_SH5_U_MEMORY_ACCESS, UNIT_SH5_U_LOGIC_B, UNIT_SH5_U_JSR
, UNIT_SH5_U_JMP, UNIT_SH5_U_BRANCH, UNIT_SH5_U_SX, UNIT_SH5_U_EXEC
, UNIT_SH5_MEDIA_U_PUTCFG, UNIT_SH5_MEDIA_U_GETCFG, UNIT_SH5_MEDIA_U_PT, UNIT_SH5_MEDIA_U_FTRVS
, UNIT_SH5_MEDIA_U_FSQRTD, UNIT_SH5_MEDIA_U_FDIVD, UNIT_SH5_MEDIA_U_COND_BRANCH, UNIT_SH5_MEDIA_U_BLINK
, UNIT_SH5_MEDIA_U_USE_TR, UNIT_SH5_MEDIA_U_USE_MTRX, UNIT_SH5_MEDIA_U_USE_FV, UNIT_SH5_MEDIA_U_USE_FP
, UNIT_SH5_MEDIA_U_LOAD_MTRX, UNIT_SH5_MEDIA_U_LOAD_FV, UNIT_SH5_MEDIA_U_LOAD_FP, UNIT_SH5_MEDIA_U_SET_MTRX
, UNIT_SH5_MEDIA_U_SET_FV, UNIT_SH5_MEDIA_U_SET_FP, UNIT_SH5_MEDIA_U_SET_GR, UNIT_SH5_MEDIA_U_FTRV
, UNIT_SH5_MEDIA_U_FIPR, UNIT_SH5_MEDIA_U_OCB, UNIT_SH5_MEDIA_U_MULR_GR, UNIT_SH5_MEDIA_U_MULR
, UNIT_SH5_MEDIA_U_USE_DR, UNIT_SH5_MEDIA_U_LOAD_DR, UNIT_SH5_MEDIA_U_SET_DR, UNIT_SH5_MEDIA_U_FCNV
, UNIT_SH5_MEDIA_U_FCMP, UNIT_SH5_MEDIA_U_FSQRT, UNIT_SH5_MEDIA_U_FDIV, UNIT_SH5_MEDIA_U_FPU_LOAD_GR
, UNIT_SH5_MEDIA_U_USE_FPSCR, UNIT_SH5_MEDIA_U_LDSL_FPSCR, UNIT_SH5_MEDIA_U_LDS_FPSCR, UNIT_SH5_MEDIA_U_USE_FPUL
, UNIT_SH5_MEDIA_U_FLDS_FPUL, UNIT_SH5_MEDIA_U_LOAD_FPUL, UNIT_SH5_MEDIA_U_SET_FPUL, UNIT_SH5_MEDIA_U_FPU_MEMORY_ACCESS
, UNIT_SH5_MEDIA_U_USE_FR, UNIT_SH5_MEDIA_U_SET_FR_0, UNIT_SH5_MEDIA_U_SET_FR, UNIT_SH5_MEDIA_U_LOAD_FR
, UNIT_SH5_MEDIA_U_MAYBE_FPU, UNIT_SH5_MEDIA_U_FPU, UNIT_SH5_MEDIA_U_TRAP, UNIT_SH5_MEDIA_U_WRITE_BACK
, UNIT_SH5_MEDIA_U_USE_MULTIPLY_RESULT, UNIT_SH5_MEDIA_U_SHIFT, UNIT_SH5_MEDIA_U_TAS, UNIT_SH5_MEDIA_U_MULSW
, UNIT_SH5_MEDIA_U_MULL, UNIT_SH5_MEDIA_U_DMUL, UNIT_SH5_MEDIA_U_MACL, UNIT_SH5_MEDIA_U_MACW
, UNIT_SH5_MEDIA_U_MULTIPLY, UNIT_SH5_MEDIA_U_SET_MAC, UNIT_SH5_MEDIA_U_LOAD_MAC, UNIT_SH5_MEDIA_U_LOAD_VBR
, UNIT_SH5_MEDIA_U_LOAD_GBR, UNIT_SH5_MEDIA_U_USE_GR, UNIT_SH5_MEDIA_U_LOAD_GR, UNIT_SH5_MEDIA_U_STC_VBR
, UNIT_SH5_MEDIA_U_LDCL_VBR, UNIT_SH5_MEDIA_U_LDCL, UNIT_SH5_MEDIA_U_USE_TBIT, UNIT_SH5_MEDIA_U_LDC_GBR
, UNIT_SH5_MEDIA_U_LDC_SR, UNIT_SH5_MEDIA_U_SET_SR_BIT, UNIT_SH5_MEDIA_U_USE_PR, UNIT_SH5_MEDIA_U_LOAD_PR
, UNIT_SH5_MEDIA_U_STS_PR, UNIT_SH5_MEDIA_U_LDS_PR, UNIT_SH5_MEDIA_U_MEMORY_ACCESS, UNIT_SH5_MEDIA_U_LOGIC_B
, UNIT_SH5_MEDIA_U_JSR, UNIT_SH5_MEDIA_U_JMP, UNIT_SH5_MEDIA_U_BRANCH, UNIT_SH5_MEDIA_U_SX
, UNIT_SH5_MEDIA_U_EXEC, UNIT_SH2_U_TRAP, UNIT_SH2_U_WRITE_BACK, UNIT_SH2_U_USE_MULTIPLY_RESULT
, UNIT_SH2_U_SHIFT, UNIT_SH2_U_TAS, UNIT_SH2_U_MULSW, UNIT_SH2_U_MULL
, UNIT_SH2_U_DMUL, UNIT_SH2_U_MACL, UNIT_SH2_U_MACW, UNIT_SH2_U_MULTIPLY
, UNIT_SH2_U_SET_MAC, UNIT_SH2_U_LOAD_MAC, UNIT_SH2_U_LOAD_VBR, UNIT_SH2_U_LOAD_GBR
, UNIT_SH2_U_USE_GR, UNIT_SH2_U_LOAD_GR, UNIT_SH2_U_STC_VBR, UNIT_SH2_U_LDCL_VBR
, UNIT_SH2_U_LDCL, UNIT_SH2_U_USE_TBIT, UNIT_SH2_U_LDC_GBR, UNIT_SH2_U_LDC_SR
, UNIT_SH2_U_SET_SR_BIT, UNIT_SH2_U_USE_PR, UNIT_SH2_U_LOAD_PR, UNIT_SH2_U_STS_PR
, UNIT_SH2_U_LDS_PR, UNIT_SH2_U_MEMORY_ACCESS, UNIT_SH2_U_LOGIC_B, UNIT_SH2_U_JSR
, UNIT_SH2_U_JMP, UNIT_SH2_U_BRANCH, UNIT_SH2_U_SX, UNIT_SH2_U_EXEC
, UNIT_SH2E_U_FCNV, UNIT_SH2E_U_FCMP, UNIT_SH2E_U_FSQRT, UNIT_SH2E_U_FDIV
, UNIT_SH2E_U_FPU_LOAD_GR, UNIT_SH2E_U_USE_FPSCR, UNIT_SH2E_U_LDSL_FPSCR, UNIT_SH2E_U_LDS_FPSCR
, UNIT_SH2E_U_USE_FPUL, UNIT_SH2E_U_FLDS_FPUL, UNIT_SH2E_U_LOAD_FPUL, UNIT_SH2E_U_SET_FPUL
, UNIT_SH2E_U_FPU_MEMORY_ACCESS, UNIT_SH2E_U_USE_FR, UNIT_SH2E_U_SET_FR_0, UNIT_SH2E_U_SET_FR
, UNIT_SH2E_U_LOAD_FR, UNIT_SH2E_U_MAYBE_FPU, UNIT_SH2E_U_FPU, UNIT_SH2E_U_TRAP
, UNIT_SH2E_U_WRITE_BACK, UNIT_SH2E_U_USE_MULTIPLY_RESULT, UNIT_SH2E_U_SHIFT, UNIT_SH2E_U_TAS
, UNIT_SH2E_U_MULSW, UNIT_SH2E_U_MULL, UNIT_SH2E_U_DMUL, UNIT_SH2E_U_MACL
, UNIT_SH2E_U_MACW, UNIT_SH2E_U_MULTIPLY, UNIT_SH2E_U_SET_MAC, UNIT_SH2E_U_LOAD_MAC
, UNIT_SH2E_U_LOAD_VBR, UNIT_SH2E_U_LOAD_GBR, UNIT_SH2E_U_USE_GR, UNIT_SH2E_U_LOAD_GR
, UNIT_SH2E_U_STC_VBR, UNIT_SH2E_U_LDCL_VBR, UNIT_SH2E_U_LDCL, UNIT_SH2E_U_USE_TBIT
, UNIT_SH2E_U_LDC_GBR, UNIT_SH2E_U_LDC_SR, UNIT_SH2E_U_SET_SR_BIT, UNIT_SH2E_U_USE_PR
, UNIT_SH2E_U_LOAD_PR, UNIT_SH2E_U_STS_PR, UNIT_SH2E_U_LDS_PR, UNIT_SH2E_U_MEMORY_ACCESS
, UNIT_SH2E_U_LOGIC_B, UNIT_SH2E_U_JSR, UNIT_SH2E_U_JMP, UNIT_SH2E_U_BRANCH
, UNIT_SH2E_U_SX, UNIT_SH2E_U_EXEC, UNIT_SH3_U_TRAP, UNIT_SH3_U_WRITE_BACK
, UNIT_SH3_U_USE_MULTIPLY_RESULT, UNIT_SH3_U_SHIFT, UNIT_SH3_U_TAS, UNIT_SH3_U_MULSW
, UNIT_SH3_U_MULL, UNIT_SH3_U_DMUL, UNIT_SH3_U_MACL, UNIT_SH3_U_MACW
, UNIT_SH3_U_MULTIPLY, UNIT_SH3_U_SET_MAC, UNIT_SH3_U_LOAD_MAC, UNIT_SH3_U_LOAD_VBR
, UNIT_SH3_U_LOAD_GBR, UNIT_SH3_U_USE_GR, UNIT_SH3_U_LOAD_GR, UNIT_SH3_U_STC_VBR
, UNIT_SH3_U_LDCL_VBR, UNIT_SH3_U_LDCL, UNIT_SH3_U_USE_TBIT, UNIT_SH3_U_LDC_GBR
, UNIT_SH3_U_LDC_SR, UNIT_SH3_U_SET_SR_BIT, UNIT_SH3_U_USE_PR, UNIT_SH3_U_LOAD_PR
, UNIT_SH3_U_STS_PR, UNIT_SH3_U_LDS_PR, UNIT_SH3_U_MEMORY_ACCESS, UNIT_SH3_U_LOGIC_B
, UNIT_SH3_U_JSR, UNIT_SH3_U_JMP, UNIT_SH3_U_BRANCH, UNIT_SH3_U_SX
, UNIT_SH3_U_EXEC, UNIT_SH3E_U_FCNV, UNIT_SH3E_U_FCMP, UNIT_SH3E_U_FSQRT
, UNIT_SH3E_U_FDIV, UNIT_SH3E_U_FPU_LOAD_GR, UNIT_SH3E_U_USE_FPSCR, UNIT_SH3E_U_LDSL_FPSCR
, UNIT_SH3E_U_LDS_FPSCR, UNIT_SH3E_U_USE_FPUL, UNIT_SH3E_U_FLDS_FPUL, UNIT_SH3E_U_LOAD_FPUL
, UNIT_SH3E_U_SET_FPUL, UNIT_SH3E_U_FPU_MEMORY_ACCESS, UNIT_SH3E_U_USE_FR, UNIT_SH3E_U_SET_FR_0
, UNIT_SH3E_U_SET_FR, UNIT_SH3E_U_LOAD_FR, UNIT_SH3E_U_MAYBE_FPU, UNIT_SH3E_U_FPU
, UNIT_SH3E_U_TRAP, UNIT_SH3E_U_WRITE_BACK, UNIT_SH3E_U_USE_MULTIPLY_RESULT, UNIT_SH3E_U_SHIFT
, UNIT_SH3E_U_TAS, UNIT_SH3E_U_MULSW, UNIT_SH3E_U_MULL, UNIT_SH3E_U_DMUL
, UNIT_SH3E_U_MACL, UNIT_SH3E_U_MACW, UNIT_SH3E_U_MULTIPLY, UNIT_SH3E_U_SET_MAC
, UNIT_SH3E_U_LOAD_MAC, UNIT_SH3E_U_LOAD_VBR, UNIT_SH3E_U_LOAD_GBR, UNIT_SH3E_U_USE_GR
, UNIT_SH3E_U_LOAD_GR, UNIT_SH3E_U_STC_VBR, UNIT_SH3E_U_LDCL_VBR, UNIT_SH3E_U_LDCL
, UNIT_SH3E_U_USE_TBIT, UNIT_SH3E_U_LDC_GBR, UNIT_SH3E_U_LDC_SR, UNIT_SH3E_U_SET_SR_BIT
, UNIT_SH3E_U_USE_PR, UNIT_SH3E_U_LOAD_PR, UNIT_SH3E_U_STS_PR, UNIT_SH3E_U_LDS_PR
, UNIT_SH3E_U_MEMORY_ACCESS, UNIT_SH3E_U_LOGIC_B, UNIT_SH3E_U_JSR, UNIT_SH3E_U_JMP
, UNIT_SH3E_U_BRANCH, UNIT_SH3E_U_SX, UNIT_SH3E_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (9)
#endif /* SH_ARCH_H */

254
sim/sh64/config.in
View File

@ -1,254 +0,0 @@
/* config.in. Generated from configure.ac by autoheader. */
/* Define if building universal (internal helper macro) */
#undef AC_APPLE_UNIVERSAL_BUILD
/* Sim debug setting */
#undef DEBUG
/* Define to 1 if translation of program messages to the user's native
language is requested. */
#undef ENABLE_NLS
/* Define to 1 if you have the <dlfcn.h> header file. */
#undef HAVE_DLFCN_H
/* Define if dv-sockser is usable. */
#undef HAVE_DV_SOCKSER
/* Define to 1 if you have the <errno.h> header file. */
#undef HAVE_ERRNO_H
/* Define to 1 if you have the <fcntl.h> header file. */
#undef HAVE_FCNTL_H
/* Define to 1 if you have the <fpu_control.h> header file. */
#undef HAVE_FPU_CONTROL_H
/* Define to 1 if you have the `ftruncate' function. */
#undef HAVE_FTRUNCATE
/* Define to 1 if you have the `getrusage' function. */
#undef HAVE_GETRUSAGE
/* Define to 1 if you have the <inttypes.h> header file. */
#undef HAVE_INTTYPES_H
/* Define to 1 if you have the `m' library (-lm). */
#undef HAVE_LIBM
/* Define to 1 if you have the `nsl' library (-lnsl). */
#undef HAVE_LIBNSL
/* Define to 1 if you have the `socket' library (-lsocket). */
#undef HAVE_LIBSOCKET
/* Define to 1 if you have the `lstat' function. */
#undef HAVE_LSTAT
/* Define to 1 if you have the <memory.h> header file. */
#undef HAVE_MEMORY_H
/* Define to 1 if you have the `mmap' function. */
#undef HAVE_MMAP
/* Define to 1 if you have the `munmap' function. */
#undef HAVE_MUNMAP
/* Define to 1 if you have the `posix_fallocate' function. */
#undef HAVE_POSIX_FALLOCATE
/* Define to 1 if you have the `sigaction' function. */
#undef HAVE_SIGACTION
/* Define to 1 if the system has the type `socklen_t'. */
#undef HAVE_SOCKLEN_T
/* Define to 1 if you have the <stdint.h> header file. */
#undef HAVE_STDINT_H
/* Define to 1 if you have the <stdlib.h> header file. */
#undef HAVE_STDLIB_H
/* Define to 1 if you have the <strings.h> header file. */
#undef HAVE_STRINGS_H
/* Define to 1 if you have the <string.h> header file. */
#undef HAVE_STRING_H
/* Define to 1 if `st_atime' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_ATIME
/* Define to 1 if `st_blksize' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_BLKSIZE
/* Define to 1 if `st_blocks' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_BLOCKS
/* Define to 1 if `st_ctime' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_CTIME
/* Define to 1 if `st_dev' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_DEV
/* Define to 1 if `st_gid' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_GID
/* Define to 1 if `st_ino' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_INO
/* Define to 1 if `st_mode' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_MODE
/* Define to 1 if `st_mtime' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_MTIME
/* Define to 1 if `st_nlink' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_NLINK
/* Define to 1 if `st_rdev' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_RDEV
/* Define to 1 if `st_size' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_SIZE
/* Define to 1 if `st_uid' is a member of `struct stat'. */
#undef HAVE_STRUCT_STAT_ST_UID
/* Define to 1 if you have the <sys/mman.h> header file. */
#undef HAVE_SYS_MMAN_H
/* Define to 1 if you have the <sys/resource.h> header file. */
#undef HAVE_SYS_RESOURCE_H
/* Define to 1 if you have the <sys/stat.h> header file. */
#undef HAVE_SYS_STAT_H
/* Define to 1 if you have the <sys/times.h> header file. */
#undef HAVE_SYS_TIMES_H
/* Define to 1 if you have the <sys/time.h> header file. */
#undef HAVE_SYS_TIME_H
/* Define to 1 if you have the <sys/types.h> header file. */
#undef HAVE_SYS_TYPES_H
/* Define to 1 if you have the `time' function. */
#undef HAVE_TIME
/* Define to 1 if you have the <time.h> header file. */
#undef HAVE_TIME_H
/* Define to 1 if you have the `truncate' function. */
#undef HAVE_TRUNCATE
/* Define to 1 if you have the <unistd.h> header file. */
#undef HAVE_UNISTD_H
/* Define to 1 if you have the <windows.h> header file. */
#undef HAVE_WINDOWS_H
/* Define to 1 if you have the `__setfpucw' function. */
#undef HAVE___SETFPUCW
/* Define to the sub-directory in which libtool stores uninstalled libraries.
*/
#undef LT_OBJDIR
/* Name of this package. */
#undef PACKAGE
/* Define to the address where bug reports for this package should be sent. */
#undef PACKAGE_BUGREPORT
/* Define to the full name of this package. */
#undef PACKAGE_NAME
/* Define to the full name and version of this package. */
#undef PACKAGE_STRING
/* Define to the one symbol short name of this package. */
#undef PACKAGE_TARNAME
/* Define to the home page for this package. */
#undef PACKAGE_URL
/* Define to the version of this package. */
#undef PACKAGE_VERSION
/* Additional package description */
#undef PKGVERSION
/* Sim profile settings */
#undef PROFILE
/* Bug reporting address */
#undef REPORT_BUGS_TO
/* Define as the return type of signal handlers (`int' or `void'). */
#undef RETSIGTYPE
/* Define to 1 if you have the ANSI C header files. */
#undef STDC_HEADERS
/* Enable extensions on AIX 3, Interix. */
#ifndef _ALL_SOURCE
# undef _ALL_SOURCE
#endif
/* Enable GNU extensions on systems that have them. */
#ifndef _GNU_SOURCE
# undef _GNU_SOURCE
#endif
/* Enable threading extensions on Solaris. */
#ifndef _POSIX_PTHREAD_SEMANTICS
# undef _POSIX_PTHREAD_SEMANTICS
#endif
/* Enable extensions on HP NonStop. */
#ifndef _TANDEM_SOURCE
# undef _TANDEM_SOURCE
#endif
/* Enable general extensions on Solaris. */
#ifndef __EXTENSIONS__
# undef __EXTENSIONS__
#endif
/* Sim assert settings */
#undef WITH_ASSERT
/* Sim debug setting */
#undef WITH_DEBUG
/* Sim default environment */
#undef WITH_ENVIRONMENT
/* Sim profile settings */
#undef WITH_PROFILE
/* How to route I/O */
#undef WITH_STDIO
/* Sim trace settings */
#undef WITH_TRACE
/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
significant byte first (like Motorola and SPARC, unlike Intel). */
#if defined AC_APPLE_UNIVERSAL_BUILD
# if defined __BIG_ENDIAN__
# define WORDS_BIGENDIAN 1
# endif
#else
# ifndef WORDS_BIGENDIAN
# undef WORDS_BIGENDIAN
# endif
#endif
/* Define to 1 if on MINIX. */
#undef _MINIX
/* Define to 2 if the system does not provide POSIX.1 features except with
this defined. */
#undef _POSIX_1_SOURCE
/* Define to 1 if you need to in order for `stat' and other things to work. */
#undef _POSIX_SOURCE

16082
sim/sh64/configure vendored
View File

File diff suppressed because it is too large Load Diff

15
sim/sh64/configure.ac
View File

@ -1,15 +0,0 @@
dnl Process this file with autoconf to produce a configure script.
AC_INIT(Makefile.in)
sinclude(../common/acinclude.m4)
SIM_AC_COMMON
SIM_AC_OPTION_ENDIAN([], BIG)
SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
SIM_AC_OPTION_SCACHE(16384)
SIM_AC_OPTION_DEFAULT_MODEL(sh5)
SIM_AC_OPTION_CGEN_MAINT
SIM_AC_OPTION_HARDWARE(yes,"","")
SIM_AC_OUTPUT

564
sim/sh64/cpu.c
View File

@ -1,564 +0,0 @@
/* Misc. support for CPU family sh64.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#define WANT_CPU sh64
#define WANT_CPU_SH64
#include "sim-main.h"
#include "cgen-ops.h"
/* Get the value of h-pc. */
UDI
sh64_h_pc_get (SIM_CPU *current_cpu)
{
return GET_H_PC ();
}
/* Set a value for h-pc. */
void
sh64_h_pc_set (SIM_CPU *current_cpu, UDI newval)
{
SET_H_PC (newval);
}
/* Get the value of h-gr. */
DI
sh64_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_GR (regno);
}
/* Set a value for h-gr. */
void
sh64_h_gr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_GR (regno, newval);
}
/* Get the value of h-grc. */
SI
sh64_h_grc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_GRC (regno);
}
/* Set a value for h-grc. */
void
sh64_h_grc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
SET_H_GRC (regno, newval);
}
/* Get the value of h-cr. */
DI
sh64_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_CR (regno);
}
/* Set a value for h-cr. */
void
sh64_h_cr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_CR (regno, newval);
}
/* Get the value of h-sr. */
SI
sh64_h_sr_get (SIM_CPU *current_cpu)
{
return CPU (h_sr);
}
/* Set a value for h-sr. */
void
sh64_h_sr_set (SIM_CPU *current_cpu, SI newval)
{
CPU (h_sr) = newval;
}
/* Get the value of h-fpscr. */
SI
sh64_h_fpscr_get (SIM_CPU *current_cpu)
{
return CPU (h_fpscr);
}
/* Set a value for h-fpscr. */
void
sh64_h_fpscr_set (SIM_CPU *current_cpu, SI newval)
{
CPU (h_fpscr) = newval;
}
/* Get the value of h-frbit. */
BI
sh64_h_frbit_get (SIM_CPU *current_cpu)
{
return GET_H_FRBIT ();
}
/* Set a value for h-frbit. */
void
sh64_h_frbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_FRBIT (newval);
}
/* Get the value of h-szbit. */
BI
sh64_h_szbit_get (SIM_CPU *current_cpu)
{
return GET_H_SZBIT ();
}
/* Set a value for h-szbit. */
void
sh64_h_szbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_SZBIT (newval);
}
/* Get the value of h-prbit. */
BI
sh64_h_prbit_get (SIM_CPU *current_cpu)
{
return GET_H_PRBIT ();
}
/* Set a value for h-prbit. */
void
sh64_h_prbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_PRBIT (newval);
}
/* Get the value of h-sbit. */
BI
sh64_h_sbit_get (SIM_CPU *current_cpu)
{
return GET_H_SBIT ();
}
/* Set a value for h-sbit. */
void
sh64_h_sbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_SBIT (newval);
}
/* Get the value of h-mbit. */
BI
sh64_h_mbit_get (SIM_CPU *current_cpu)
{
return GET_H_MBIT ();
}
/* Set a value for h-mbit. */
void
sh64_h_mbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_MBIT (newval);
}
/* Get the value of h-qbit. */
BI
sh64_h_qbit_get (SIM_CPU *current_cpu)
{
return GET_H_QBIT ();
}
/* Set a value for h-qbit. */
void
sh64_h_qbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_QBIT (newval);
}
/* Get the value of h-fr. */
SF
sh64_h_fr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_fr[regno]);
}
/* Set a value for h-fr. */
void
sh64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
CPU (h_fr[regno]) = newval;
}
/* Get the value of h-fp. */
SF
sh64_h_fp_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FP (regno);
}
/* Set a value for h-fp. */
void
sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FP (regno, newval);
}
/* Get the value of h-fv. */
SF
sh64_h_fv_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FV (regno);
}
/* Set a value for h-fv. */
void
sh64_h_fv_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FV (regno, newval);
}
/* Get the value of h-fmtx. */
SF
sh64_h_fmtx_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FMTX (regno);
}
/* Set a value for h-fmtx. */
void
sh64_h_fmtx_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FMTX (regno, newval);
}
/* Get the value of h-dr. */
DF
sh64_h_dr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_DR (regno);
}
/* Set a value for h-dr. */
void
sh64_h_dr_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_DR (regno, newval);
}
/* Get the value of h-fsd. */
DF
sh64_h_fsd_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FSD (regno);
}
/* Set a value for h-fsd. */
void
sh64_h_fsd_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_FSD (regno, newval);
}
/* Get the value of h-fmov. */
DF
sh64_h_fmov_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FMOV (regno);
}
/* Set a value for h-fmov. */
void
sh64_h_fmov_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_FMOV (regno, newval);
}
/* Get the value of h-tr. */
DI
sh64_h_tr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_tr[regno]);
}
/* Set a value for h-tr. */
void
sh64_h_tr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
CPU (h_tr[regno]) = newval;
}
/* Get the value of h-endian. */
BI
sh64_h_endian_get (SIM_CPU *current_cpu)
{
return GET_H_ENDIAN ();
}
/* Set a value for h-endian. */
void
sh64_h_endian_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_ENDIAN (newval);
}
/* Get the value of h-ism. */
BI
sh64_h_ism_get (SIM_CPU *current_cpu)
{
return GET_H_ISM ();
}
/* Set a value for h-ism. */
void
sh64_h_ism_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_ISM (newval);
}
/* Get the value of h-frc. */
SF
sh64_h_frc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FRC (regno);
}
/* Set a value for h-frc. */
void
sh64_h_frc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FRC (regno, newval);
}
/* Get the value of h-drc. */
DF
sh64_h_drc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_DRC (regno);
}
/* Set a value for h-drc. */
void
sh64_h_drc_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_DRC (regno, newval);
}
/* Get the value of h-xf. */
SF
sh64_h_xf_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_XF (regno);
}
/* Set a value for h-xf. */
void
sh64_h_xf_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_XF (regno, newval);
}
/* Get the value of h-xd. */
DF
sh64_h_xd_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_XD (regno);
}
/* Set a value for h-xd. */
void
sh64_h_xd_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_XD (regno, newval);
}
/* Get the value of h-fvc. */
SF
sh64_h_fvc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FVC (regno);
}
/* Set a value for h-fvc. */
void
sh64_h_fvc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FVC (regno, newval);
}
/* Get the value of h-gbr. */
SI
sh64_h_gbr_get (SIM_CPU *current_cpu)
{
return GET_H_GBR ();
}
/* Set a value for h-gbr. */
void
sh64_h_gbr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_GBR (newval);
}
/* Get the value of h-vbr. */
SI
sh64_h_vbr_get (SIM_CPU *current_cpu)
{
return GET_H_VBR ();
}
/* Set a value for h-vbr. */
void
sh64_h_vbr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_VBR (newval);
}
/* Get the value of h-pr. */
SI
sh64_h_pr_get (SIM_CPU *current_cpu)
{
return GET_H_PR ();
}
/* Set a value for h-pr. */
void
sh64_h_pr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_PR (newval);
}
/* Get the value of h-macl. */
SI
sh64_h_macl_get (SIM_CPU *current_cpu)
{
return GET_H_MACL ();
}
/* Set a value for h-macl. */
void
sh64_h_macl_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_MACL (newval);
}
/* Get the value of h-mach. */
SI
sh64_h_mach_get (SIM_CPU *current_cpu)
{
return GET_H_MACH ();
}
/* Set a value for h-mach. */
void
sh64_h_mach_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_MACH (newval);
}
/* Get the value of h-tbit. */
BI
sh64_h_tbit_get (SIM_CPU *current_cpu)
{
return GET_H_TBIT ();
}
/* Set a value for h-tbit. */
void
sh64_h_tbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_TBIT (newval);
}
/* Record trace results for INSN. */
void
sh64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
int *indices, TRACE_RECORD *tr)
{
}

341
sim/sh64/cpu.h
View File

@ -1,341 +0,0 @@
/* CPU family header for sh64.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CPU_SH64_H
#define CPU_SH64_H
/* Maximum number of instructions that are fetched at a time.
This is for LIW type instructions sets (e.g. m32r). */
#define MAX_LIW_INSNS 1
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* The size of an "int" needed to hold an instruction word.
This is usually 32 bits, but some architectures needs 64 bits. */
typedef CGEN_INSN_INT CGEN_INSN_WORD;
#include "cgen-engine.h"
/* CPU state information. */
typedef struct {
/* Hardware elements. */
struct {
/* Program counter */
UDI h_pc;
#define GET_H_PC() CPU (h_pc)
#define SET_H_PC(x) \
do { \
{\
CPU (h_ism) = ANDDI ((x), 1);\
CPU (h_pc) = ANDDI ((x), INVDI (1));\
}\
;} while (0)
/* General purpose integer registers */
DI h_gr[64];
#define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index])))
#define SET_H_GR(index, x) \
do { \
if ((((index)) != (63))) {\
CPU (h_gr[(index)]) = (x);\
} else {\
((void) 0); /*nop*/\
}\
;} while (0)
/* Control registers */
DI h_cr[64];
#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
#define SET_H_CR(index, x) \
do { \
if ((((index)) == (0))) {\
CPU (h_sr) = (x);\
} else {\
CPU (h_cr[(index)]) = (x);\
}\
;} while (0)
/* Status register */
SI h_sr;
#define GET_H_SR() CPU (h_sr)
#define SET_H_SR(x) (CPU (h_sr) = (x))
/* Floating point status and control register */
SI h_fpscr;
#define GET_H_FPSCR() CPU (h_fpscr)
#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
/* Single precision floating point registers */
SF h_fr[64];
#define GET_H_FR(a1) CPU (h_fr)[a1]
#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
/* Single/Double precision floating point registers */
DF h_fsd[16];
#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, CPU (h_fr[index]))))
#define SET_H_FSD(index, x) \
do { \
if (GET_H_PRBIT ()) {\
SET_H_DRC ((index), (x));\
} else {\
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\
}\
;} while (0)
/* floating point registers for fmov */
DF h_fmov[16];
#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
#define SET_H_FMOV(index, x) \
do { \
if (NOTBI (GET_H_SZBIT ())) {\
SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\
} else {\
if ((((((index)) & (1))) == (1))) {\
SET_H_XD ((((index)) & ((~ (1)))), (x));\
} else {\
SET_H_DR ((index), (x));\
}\
}\
;} while (0)
/* Branch target registers */
DI h_tr[8];
#define GET_H_TR(a1) CPU (h_tr)[a1]
#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
/* Current instruction set mode */
BI h_ism;
#define GET_H_ISM() CPU (h_ism)
#define SET_H_ISM(x) \
do { \
cgen_rtx_error (current_cpu, "cannot set ism directly");\
;} while (0)
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} SH64_CPU_DATA;
/* Virtual regs. */
#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
#define SET_H_GRC(index, x) \
do { \
CPU (h_gr[(index)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1)
#define SET_H_FRBIT(x) \
do { \
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\
;} while (0)
#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1)
#define SET_H_SZBIT(x) \
do { \
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\
;} while (0)
#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1)
#define SET_H_PRBIT(x) \
do { \
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\
;} while (0)
#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
#define SET_H_SBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
;} while (0)
#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
#define SET_H_MBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
;} while (0)
#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
#define SET_H_QBIT(x) \
do { \
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
;} while (0)
#define GET_H_FP(index) CPU (h_fr[index])
#define SET_H_FP(index, x) \
do { \
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_FV(index) CPU (h_fr[index])
#define SET_H_FV(index, x) \
do { \
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_FMTX(index) CPU (h_fr[index])
#define SET_H_FMTX(index, x) \
do { \
CPU (h_fr[(index)]) = (x);\
;} while (0)
#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
#define SET_H_DR(index, x) \
do { \
{\
CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
}\
;} while (0)
#define GET_H_ENDIAN() sh64_endian (current_cpu)
#define SET_H_ENDIAN(x) \
do { \
cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
;} while (0)
#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
#define SET_H_FRC(index, x) \
do { \
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
#define SET_H_DRC(index, x) \
do { \
SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
;} while (0)
#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
#define SET_H_XF(index, x) \
do { \
CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
#define SET_H_XD(index, x) \
do { \
SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
;} while (0)
#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
#define SET_H_FVC(index, x) \
do { \
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
;} while (0)
#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
#define SET_H_GBR(x) \
do { \
CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1)
#define SET_H_VBR(x) \
do { \
CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
#define SET_H_PR(x) \
do { \
CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
;} while (0)
#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
#define SET_H_MACL(x) \
do { \
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
;} while (0)
#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
#define SET_H_MACH(x) \
do { \
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
;} while (0)
#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
#define SET_H_TBIT(x) \
do { \
CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
;} while (0)
/* Cover fns for register access. */
UDI sh64_h_pc_get (SIM_CPU *);
void sh64_h_pc_set (SIM_CPU *, UDI);
DI sh64_h_gr_get (SIM_CPU *, UINT);
void sh64_h_gr_set (SIM_CPU *, UINT, DI);
SI sh64_h_grc_get (SIM_CPU *, UINT);
void sh64_h_grc_set (SIM_CPU *, UINT, SI);
DI sh64_h_cr_get (SIM_CPU *, UINT);
void sh64_h_cr_set (SIM_CPU *, UINT, DI);
SI sh64_h_sr_get (SIM_CPU *);
void sh64_h_sr_set (SIM_CPU *, SI);
SI sh64_h_fpscr_get (SIM_CPU *);
void sh64_h_fpscr_set (SIM_CPU *, SI);
BI sh64_h_frbit_get (SIM_CPU *);
void sh64_h_frbit_set (SIM_CPU *, BI);
BI sh64_h_szbit_get (SIM_CPU *);
void sh64_h_szbit_set (SIM_CPU *, BI);
BI sh64_h_prbit_get (SIM_CPU *);
void sh64_h_prbit_set (SIM_CPU *, BI);
BI sh64_h_sbit_get (SIM_CPU *);
void sh64_h_sbit_set (SIM_CPU *, BI);
BI sh64_h_mbit_get (SIM_CPU *);
void sh64_h_mbit_set (SIM_CPU *, BI);
BI sh64_h_qbit_get (SIM_CPU *);
void sh64_h_qbit_set (SIM_CPU *, BI);
SF sh64_h_fr_get (SIM_CPU *, UINT);
void sh64_h_fr_set (SIM_CPU *, UINT, SF);
SF sh64_h_fp_get (SIM_CPU *, UINT);
void sh64_h_fp_set (SIM_CPU *, UINT, SF);
SF sh64_h_fv_get (SIM_CPU *, UINT);
void sh64_h_fv_set (SIM_CPU *, UINT, SF);
SF sh64_h_fmtx_get (SIM_CPU *, UINT);
void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
DF sh64_h_dr_get (SIM_CPU *, UINT);
void sh64_h_dr_set (SIM_CPU *, UINT, DF);
DF sh64_h_fsd_get (SIM_CPU *, UINT);
void sh64_h_fsd_set (SIM_CPU *, UINT, DF);
DF sh64_h_fmov_get (SIM_CPU *, UINT);
void sh64_h_fmov_set (SIM_CPU *, UINT, DF);
DI sh64_h_tr_get (SIM_CPU *, UINT);
void sh64_h_tr_set (SIM_CPU *, UINT, DI);
BI sh64_h_endian_get (SIM_CPU *);
void sh64_h_endian_set (SIM_CPU *, BI);
BI sh64_h_ism_get (SIM_CPU *);
void sh64_h_ism_set (SIM_CPU *, BI);
SF sh64_h_frc_get (SIM_CPU *, UINT);
void sh64_h_frc_set (SIM_CPU *, UINT, SF);
DF sh64_h_drc_get (SIM_CPU *, UINT);
void sh64_h_drc_set (SIM_CPU *, UINT, DF);
SF sh64_h_xf_get (SIM_CPU *, UINT);
void sh64_h_xf_set (SIM_CPU *, UINT, SF);
DF sh64_h_xd_get (SIM_CPU *, UINT);
void sh64_h_xd_set (SIM_CPU *, UINT, DF);
SF sh64_h_fvc_get (SIM_CPU *, UINT);
void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
SI sh64_h_gbr_get (SIM_CPU *);
void sh64_h_gbr_set (SIM_CPU *, SI);
SI sh64_h_vbr_get (SIM_CPU *);
void sh64_h_vbr_set (SIM_CPU *, SI);
SI sh64_h_pr_get (SIM_CPU *);
void sh64_h_pr_set (SIM_CPU *, SI);
SI sh64_h_macl_get (SIM_CPU *);
void sh64_h_macl_set (SIM_CPU *, SI);
SI sh64_h_mach_get (SIM_CPU *);
void sh64_h_mach_set (SIM_CPU *, SI);
BI sh64_h_tbit_get (SIM_CPU *);
void sh64_h_tbit_set (SIM_CPU *, BI);
/* These must be hand-written. */
extern CPUREG_FETCH_FN sh64_fetch_register;
extern CPUREG_STORE_FN sh64_store_register;
typedef struct {
int empty;
} MODEL_SH4_DATA;
typedef struct {
int empty;
} MODEL_SH5_DATA;
typedef struct {
int empty;
} MODEL_SH5_MEDIA_DATA;
/* Collection of various things for the trace handler to use. */
typedef struct trace_record {
IADDR pc;
/* FIXME:wip */
} TRACE_RECORD;
#endif /* CPU_SH64_H */

75
sim/sh64/cpuall.h
View File

@ -1,75 +0,0 @@
/* Simulator CPU header for sh.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SH_CPUALL_H
#define SH_CPUALL_H
/* Include files for each cpu family. */
#ifdef WANT_CPU_SH64
#include "eng.h"
#include "cpu.h"
#include "decode.h"
#endif
extern const SIM_MACH sh2_mach;
extern const SIM_MACH sh2e_mach;
extern const SIM_MACH sh2a_fpu_mach;
extern const SIM_MACH sh2a_nofpu_mach;
extern const SIM_MACH sh3_mach;
extern const SIM_MACH sh3e_mach;
extern const SIM_MACH sh4_nofpu_mach;
extern const SIM_MACH sh4_mach;
extern const SIM_MACH sh4a_nofpu_mach;
extern const SIM_MACH sh4a_mach;
extern const SIM_MACH sh4al_mach;
extern const SIM_MACH sh5_mach;
#ifndef WANT_CPU
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
IADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* ??? Temporary hack for skip insns. */
char skip_count;
char unused;
/* cpu specific data follows */
};
#endif
#ifndef WANT_CPU
/* A cached insn.
??? SCACHE used to contain more than just argbuf. We could delete the
type entirely and always just use ARGBUF, but for future concerns and as
a level of abstraction it is left in. */
struct scache {
struct argbuf argbuf;
};
#endif
#endif /* SH_CPUALL_H */

6134
sim/sh64/decode-compact.c
View File

File diff suppressed because it is too large Load Diff

279
sim/sh64/decode-compact.h
View File

@ -1,279 +0,0 @@
/* Decode header for sh64_compact.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SH64_COMPACT_DECODE_H
#define SH64_COMPACT_DECODE_H
extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void sh64_compact_init_idesc_table (SIM_CPU *);
extern void sh64_compact_sem_init_idesc_table (SIM_CPU *);
extern void sh64_compact_semf_init_idesc_table (SIM_CPU *);
/* Enum declaration for instructions in cpu family sh64. */
typedef enum sh64_compact_insn_type {
SH64_COMPACT_INSN_X_INVALID, SH64_COMPACT_INSN_X_AFTER, SH64_COMPACT_INSN_X_BEFORE, SH64_COMPACT_INSN_X_CTI_CHAIN
, SH64_COMPACT_INSN_X_CHAIN, SH64_COMPACT_INSN_X_BEGIN, SH64_COMPACT_INSN_ADD_COMPACT, SH64_COMPACT_INSN_ADDI_COMPACT
, SH64_COMPACT_INSN_ADDC_COMPACT, SH64_COMPACT_INSN_ADDV_COMPACT, SH64_COMPACT_INSN_AND_COMPACT, SH64_COMPACT_INSN_ANDI_COMPACT
, SH64_COMPACT_INSN_ANDB_COMPACT, SH64_COMPACT_INSN_BF_COMPACT, SH64_COMPACT_INSN_BFS_COMPACT, SH64_COMPACT_INSN_BRA_COMPACT
, SH64_COMPACT_INSN_BRAF_COMPACT, SH64_COMPACT_INSN_BRK_COMPACT, SH64_COMPACT_INSN_BSR_COMPACT, SH64_COMPACT_INSN_BSRF_COMPACT
, SH64_COMPACT_INSN_BT_COMPACT, SH64_COMPACT_INSN_BTS_COMPACT, SH64_COMPACT_INSN_CLRMAC_COMPACT, SH64_COMPACT_INSN_CLRS_COMPACT
, SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CMPEQ_COMPACT, SH64_COMPACT_INSN_CMPEQI_COMPACT, SH64_COMPACT_INSN_CMPGE_COMPACT
, SH64_COMPACT_INSN_CMPGT_COMPACT, SH64_COMPACT_INSN_CMPHI_COMPACT, SH64_COMPACT_INSN_CMPHS_COMPACT, SH64_COMPACT_INSN_CMPPL_COMPACT
, SH64_COMPACT_INSN_CMPPZ_COMPACT, SH64_COMPACT_INSN_CMPSTR_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT
, SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DIVU_COMPACT, SH64_COMPACT_INSN_MULR_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT
, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DT_COMPACT, SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT
, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT, SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT
, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT, SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT
, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT, SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT
, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT, SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT
, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT, SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT
, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT, SH64_COMPACT_INSN_FMOV8_COMPACT, SH64_COMPACT_INSN_FMOV9_COMPACT
, SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FSCHG_COMPACT
, SH64_COMPACT_INSN_FSQRT_COMPACT, SH64_COMPACT_INSN_FSTS_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT
, SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_INSN_LDC_GBR_COMPACT
, SH64_COMPACT_INSN_LDC_VBR_COMPACT, SH64_COMPACT_INSN_LDC_SR_COMPACT, SH64_COMPACT_INSN_LDCL_GBR_COMPACT, SH64_COMPACT_INSN_LDCL_VBR_COMPACT
, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_INSN_LDSL_FPUL_COMPACT
, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT, SH64_COMPACT_INSN_LDSL_MACL_COMPACT
, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT, SH64_COMPACT_INSN_MACW_COMPACT
, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVI20_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT
, SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB4_COMPACT, SH64_COMPACT_INSN_MOVB5_COMPACT
, SH64_COMPACT_INSN_MOVB6_COMPACT, SH64_COMPACT_INSN_MOVB7_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT
, SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT
, SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT
, SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT
, SH64_COMPACT_INSN_MOVL12_COMPACT, SH64_COMPACT_INSN_MOVL13_COMPACT, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT
, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT, SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT
, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT, SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT
, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT, SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVCOL_COMPACT
, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MOVUAL_COMPACT, SH64_COMPACT_INSN_MOVUAL2_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT
, SH64_COMPACT_INSN_MULSW_COMPACT, SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT
, SH64_COMPACT_INSN_NOP_COMPACT, SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT
, SH64_COMPACT_INSN_OCBWB_COMPACT, SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT
, SH64_COMPACT_INSN_PREF_COMPACT, SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT
, SH64_COMPACT_INSN_ROTR_COMPACT, SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT
, SH64_COMPACT_INSN_SHAD_COMPACT, SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT
, SH64_COMPACT_INSN_SHLL_COMPACT, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT
, SH64_COMPACT_INSN_SHLR_COMPACT, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT
, SH64_COMPACT_INSN_STC_GBR_COMPACT, SH64_COMPACT_INSN_STC_VBR_COMPACT, SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STCL_VBR_COMPACT
, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT, SH64_COMPACT_INSN_STSL_FPUL_COMPACT
, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT, SH64_COMPACT_INSN_STSL_MACL_COMPACT
, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT, SH64_COMPACT_INSN_SUBC_COMPACT
, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT, SH64_COMPACT_INSN_TASB_COMPACT
, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT, SH64_COMPACT_INSN_TSTB_COMPACT
, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT, SH64_COMPACT_INSN_XTRCT_COMPACT
, SH64_COMPACT_INSN__MAX
} SH64_COMPACT_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family sh64. */
typedef enum sh64_compact_sfmt_type {
SH64_COMPACT_SFMT_EMPTY, SH64_COMPACT_SFMT_ADD_COMPACT, SH64_COMPACT_SFMT_ADDI_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT
, SH64_COMPACT_SFMT_ADDV_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT
, SH64_COMPACT_SFMT_BF_COMPACT, SH64_COMPACT_SFMT_BFS_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT
, SH64_COMPACT_SFMT_BRK_COMPACT, SH64_COMPACT_SFMT_BSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT
, SH64_COMPACT_SFMT_CLRS_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT
, SH64_COMPACT_SFMT_CMPPL_COMPACT, SH64_COMPACT_SFMT_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT
, SH64_COMPACT_SFMT_DIVU_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT
, SH64_COMPACT_SFMT_FABS_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT, SH64_COMPACT_SFMT_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT
, SH64_COMPACT_SFMT_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT, SH64_COMPACT_SFMT_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT
, SH64_COMPACT_SFMT_FLOAT_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT, SH64_COMPACT_SFMT_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT
, SH64_COMPACT_SFMT_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT, SH64_COMPACT_SFMT_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT
, SH64_COMPACT_SFMT_FMOV7_COMPACT, SH64_COMPACT_SFMT_FMOV8_COMPACT, SH64_COMPACT_SFMT_FMOV9_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT
, SH64_COMPACT_SFMT_FSCHG_COMPACT, SH64_COMPACT_SFMT_FSTS_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT
, SH64_COMPACT_SFMT_LDC_GBR_COMPACT, SH64_COMPACT_SFMT_LDC_VBR_COMPACT, SH64_COMPACT_SFMT_LDC_SR_COMPACT, SH64_COMPACT_SFMT_LDCL_GBR_COMPACT
, SH64_COMPACT_SFMT_LDCL_VBR_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT
, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT, SH64_COMPACT_SFMT_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT
, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT, SH64_COMPACT_SFMT_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT
, SH64_COMPACT_SFMT_MACW_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT, SH64_COMPACT_SFMT_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVI20_COMPACT
, SH64_COMPACT_SFMT_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT, SH64_COMPACT_SFMT_MOVB4_COMPACT
, SH64_COMPACT_SFMT_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT
, SH64_COMPACT_SFMT_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVL1_COMPACT, SH64_COMPACT_SFMT_MOVL2_COMPACT
, SH64_COMPACT_SFMT_MOVL3_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT, SH64_COMPACT_SFMT_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL6_COMPACT
, SH64_COMPACT_SFMT_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL8_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT
, SH64_COMPACT_SFMT_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVL12_COMPACT, SH64_COMPACT_SFMT_MOVL13_COMPACT, SH64_COMPACT_SFMT_MOVW1_COMPACT
, SH64_COMPACT_SFMT_MOVW2_COMPACT, SH64_COMPACT_SFMT_MOVW3_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT
, SH64_COMPACT_SFMT_MOVW6_COMPACT, SH64_COMPACT_SFMT_MOVW7_COMPACT, SH64_COMPACT_SFMT_MOVW8_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT
, SH64_COMPACT_SFMT_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT
, SH64_COMPACT_SFMT_MOVCOL_COMPACT, SH64_COMPACT_SFMT_MOVT_COMPACT, SH64_COMPACT_SFMT_MOVUAL_COMPACT, SH64_COMPACT_SFMT_MOVUAL2_COMPACT
, SH64_COMPACT_SFMT_MULL_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT, SH64_COMPACT_SFMT_PREF_COMPACT
, SH64_COMPACT_SFMT_ROTCL_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT, SH64_COMPACT_SFMT_STC_GBR_COMPACT
, SH64_COMPACT_SFMT_STC_VBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_VBR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT
, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT
, SH64_COMPACT_SFMT_STSL_MACH_COMPACT, SH64_COMPACT_SFMT_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT
, SH64_COMPACT_SFMT_STSL_PR_COMPACT, SH64_COMPACT_SFMT_TASB_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT
, SH64_COMPACT_SFMT_TSTB_COMPACT
} SH64_COMPACT_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_putcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_getcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_pt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_ftrvs (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fsqrtd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdivd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_cond_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_blink (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_use_tr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/* Profiling before/after handlers (user written) */
extern void sh64_model_insn_before (SIM_CPU *, int /*first_p*/);
extern void sh64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
#endif /* SH64_COMPACT_DECODE_H */

4100
sim/sh64/decode-media.c
View File

File diff suppressed because it is too large Load Diff

269
sim/sh64/decode-media.h
View File

@ -1,269 +0,0 @@
/* Decode header for sh64_media.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SH64_MEDIA_DECODE_H
#define SH64_MEDIA_DECODE_H
extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void sh64_media_init_idesc_table (SIM_CPU *);
extern void sh64_media_sem_init_idesc_table (SIM_CPU *);
extern void sh64_media_semf_init_idesc_table (SIM_CPU *);
/* Enum declaration for instructions in cpu family sh64. */
typedef enum sh64_media_insn_type {
SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_INSN_X_AFTER, SH64_MEDIA_INSN_X_BEFORE, SH64_MEDIA_INSN_X_CTI_CHAIN
, SH64_MEDIA_INSN_X_CHAIN, SH64_MEDIA_INSN_X_BEGIN, SH64_MEDIA_INSN_ADD, SH64_MEDIA_INSN_ADDL
, SH64_MEDIA_INSN_ADDI, SH64_MEDIA_INSN_ADDIL, SH64_MEDIA_INSN_ADDZL, SH64_MEDIA_INSN_ALLOCO
, SH64_MEDIA_INSN_AND, SH64_MEDIA_INSN_ANDC, SH64_MEDIA_INSN_ANDI, SH64_MEDIA_INSN_BEQ
, SH64_MEDIA_INSN_BEQI, SH64_MEDIA_INSN_BGE, SH64_MEDIA_INSN_BGEU, SH64_MEDIA_INSN_BGT
, SH64_MEDIA_INSN_BGTU, SH64_MEDIA_INSN_BLINK, SH64_MEDIA_INSN_BNE, SH64_MEDIA_INSN_BNEI
, SH64_MEDIA_INSN_BRK, SH64_MEDIA_INSN_BYTEREV, SH64_MEDIA_INSN_CMPEQ, SH64_MEDIA_INSN_CMPGT
, SH64_MEDIA_INSN_CMPGTU, SH64_MEDIA_INSN_CMVEQ, SH64_MEDIA_INSN_CMVNE, SH64_MEDIA_INSN_FABSD
, SH64_MEDIA_INSN_FABSS, SH64_MEDIA_INSN_FADDD, SH64_MEDIA_INSN_FADDS, SH64_MEDIA_INSN_FCMPEQD
, SH64_MEDIA_INSN_FCMPEQS, SH64_MEDIA_INSN_FCMPGED, SH64_MEDIA_INSN_FCMPGES, SH64_MEDIA_INSN_FCMPGTD
, SH64_MEDIA_INSN_FCMPGTS, SH64_MEDIA_INSN_FCMPUND, SH64_MEDIA_INSN_FCMPUNS, SH64_MEDIA_INSN_FCNVDS
, SH64_MEDIA_INSN_FCNVSD, SH64_MEDIA_INSN_FDIVD, SH64_MEDIA_INSN_FDIVS, SH64_MEDIA_INSN_FGETSCR
, SH64_MEDIA_INSN_FIPRS, SH64_MEDIA_INSN_FLDD, SH64_MEDIA_INSN_FLDP, SH64_MEDIA_INSN_FLDS
, SH64_MEDIA_INSN_FLDXD, SH64_MEDIA_INSN_FLDXP, SH64_MEDIA_INSN_FLDXS, SH64_MEDIA_INSN_FLOATLD
, SH64_MEDIA_INSN_FLOATLS, SH64_MEDIA_INSN_FLOATQD, SH64_MEDIA_INSN_FLOATQS, SH64_MEDIA_INSN_FMACS
, SH64_MEDIA_INSN_FMOVD, SH64_MEDIA_INSN_FMOVDQ, SH64_MEDIA_INSN_FMOVLS, SH64_MEDIA_INSN_FMOVQD
, SH64_MEDIA_INSN_FMOVS, SH64_MEDIA_INSN_FMOVSL, SH64_MEDIA_INSN_FMULD, SH64_MEDIA_INSN_FMULS
, SH64_MEDIA_INSN_FNEGD, SH64_MEDIA_INSN_FNEGS, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_INSN_FSQRTD
, SH64_MEDIA_INSN_FSQRTS, SH64_MEDIA_INSN_FSTD, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_INSN_FSTS
, SH64_MEDIA_INSN_FSTXD, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_INSN_FSTXS, SH64_MEDIA_INSN_FSUBD
, SH64_MEDIA_INSN_FSUBS, SH64_MEDIA_INSN_FTRCDL, SH64_MEDIA_INSN_FTRCSL, SH64_MEDIA_INSN_FTRCDQ
, SH64_MEDIA_INSN_FTRCSQ, SH64_MEDIA_INSN_FTRVS, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_INSN_GETCON
, SH64_MEDIA_INSN_GETTR, SH64_MEDIA_INSN_ICBI, SH64_MEDIA_INSN_LDB, SH64_MEDIA_INSN_LDL
, SH64_MEDIA_INSN_LDQ, SH64_MEDIA_INSN_LDUB, SH64_MEDIA_INSN_LDUW, SH64_MEDIA_INSN_LDW
, SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_INSN_LDLOQ
, SH64_MEDIA_INSN_LDXB, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_INSN_LDXUB
, SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_INSN_MABSL, SH64_MEDIA_INSN_MABSW
, SH64_MEDIA_INSN_MADDL, SH64_MEDIA_INSN_MADDW, SH64_MEDIA_INSN_MADDSL, SH64_MEDIA_INSN_MADDSUB
, SH64_MEDIA_INSN_MADDSW, SH64_MEDIA_INSN_MCMPEQB, SH64_MEDIA_INSN_MCMPEQL, SH64_MEDIA_INSN_MCMPEQW
, SH64_MEDIA_INSN_MCMPGTL, SH64_MEDIA_INSN_MCMPGTUB, SH64_MEDIA_INSN_MCMPGTW, SH64_MEDIA_INSN_MCMV
, SH64_MEDIA_INSN_MCNVSLW, SH64_MEDIA_INSN_MCNVSWB, SH64_MEDIA_INSN_MCNVSWUB, SH64_MEDIA_INSN_MEXTR1
, SH64_MEDIA_INSN_MEXTR2, SH64_MEDIA_INSN_MEXTR3, SH64_MEDIA_INSN_MEXTR4, SH64_MEDIA_INSN_MEXTR5
, SH64_MEDIA_INSN_MEXTR6, SH64_MEDIA_INSN_MEXTR7, SH64_MEDIA_INSN_MMACFXWL, SH64_MEDIA_INSN_MMACNFX_WL
, SH64_MEDIA_INSN_MMULL, SH64_MEDIA_INSN_MMULW, SH64_MEDIA_INSN_MMULFXL, SH64_MEDIA_INSN_MMULFXW
, SH64_MEDIA_INSN_MMULFXRPW, SH64_MEDIA_INSN_MMULHIWL, SH64_MEDIA_INSN_MMULLOWL, SH64_MEDIA_INSN_MMULSUMWQ
, SH64_MEDIA_INSN_MOVI, SH64_MEDIA_INSN_MPERMW, SH64_MEDIA_INSN_MSADUBQ, SH64_MEDIA_INSN_MSHALDSL
, SH64_MEDIA_INSN_MSHALDSW, SH64_MEDIA_INSN_MSHARDL, SH64_MEDIA_INSN_MSHARDW, SH64_MEDIA_INSN_MSHARDSQ
, SH64_MEDIA_INSN_MSHFHIB, SH64_MEDIA_INSN_MSHFHIL, SH64_MEDIA_INSN_MSHFHIW, SH64_MEDIA_INSN_MSHFLOB
, SH64_MEDIA_INSN_MSHFLOL, SH64_MEDIA_INSN_MSHFLOW, SH64_MEDIA_INSN_MSHLLDL, SH64_MEDIA_INSN_MSHLLDW
, SH64_MEDIA_INSN_MSHLRDL, SH64_MEDIA_INSN_MSHLRDW, SH64_MEDIA_INSN_MSUBL, SH64_MEDIA_INSN_MSUBW
, SH64_MEDIA_INSN_MSUBSL, SH64_MEDIA_INSN_MSUBSUB, SH64_MEDIA_INSN_MSUBSW, SH64_MEDIA_INSN_MULSL
, SH64_MEDIA_INSN_MULUL, SH64_MEDIA_INSN_NOP, SH64_MEDIA_INSN_NSB, SH64_MEDIA_INSN_OCBI
, SH64_MEDIA_INSN_OCBP, SH64_MEDIA_INSN_OCBWB, SH64_MEDIA_INSN_OR, SH64_MEDIA_INSN_ORI
, SH64_MEDIA_INSN_PREFI, SH64_MEDIA_INSN_PTA, SH64_MEDIA_INSN_PTABS, SH64_MEDIA_INSN_PTB
, SH64_MEDIA_INSN_PTREL, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCON, SH64_MEDIA_INSN_RTE
, SH64_MEDIA_INSN_SHARD, SH64_MEDIA_INSN_SHARDL, SH64_MEDIA_INSN_SHARI, SH64_MEDIA_INSN_SHARIL
, SH64_MEDIA_INSN_SHLLD, SH64_MEDIA_INSN_SHLLDL, SH64_MEDIA_INSN_SHLLI, SH64_MEDIA_INSN_SHLLIL
, SH64_MEDIA_INSN_SHLRD, SH64_MEDIA_INSN_SHLRDL, SH64_MEDIA_INSN_SHLRI, SH64_MEDIA_INSN_SHLRIL
, SH64_MEDIA_INSN_SHORI, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_INSN_STB, SH64_MEDIA_INSN_STL
, SH64_MEDIA_INSN_STQ, SH64_MEDIA_INSN_STW, SH64_MEDIA_INSN_STHIL, SH64_MEDIA_INSN_STHIQ
, SH64_MEDIA_INSN_STLOL, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_INSN_STXB, SH64_MEDIA_INSN_STXL
, SH64_MEDIA_INSN_STXQ, SH64_MEDIA_INSN_STXW, SH64_MEDIA_INSN_SUB, SH64_MEDIA_INSN_SUBL
, SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_INSN_TRAPA
, SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN__MAX
} SH64_MEDIA_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family sh64. */
typedef enum sh64_media_sfmt_type {
SH64_MEDIA_SFMT_EMPTY, SH64_MEDIA_SFMT_ADD, SH64_MEDIA_SFMT_ADDI, SH64_MEDIA_SFMT_ALLOCO
, SH64_MEDIA_SFMT_BEQ, SH64_MEDIA_SFMT_BEQI, SH64_MEDIA_SFMT_BLINK, SH64_MEDIA_SFMT_BNEI
, SH64_MEDIA_SFMT_BRK, SH64_MEDIA_SFMT_BYTEREV, SH64_MEDIA_SFMT_CMVEQ, SH64_MEDIA_SFMT_FABSD
, SH64_MEDIA_SFMT_FABSS, SH64_MEDIA_SFMT_FADDD, SH64_MEDIA_SFMT_FADDS, SH64_MEDIA_SFMT_FCMPEQD
, SH64_MEDIA_SFMT_FCMPEQS, SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FGETSCR
, SH64_MEDIA_SFMT_FIPRS, SH64_MEDIA_SFMT_FLDD, SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS
, SH64_MEDIA_SFMT_FLDXD, SH64_MEDIA_SFMT_FLDXP, SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS
, SH64_MEDIA_SFMT_FMOVDQ, SH64_MEDIA_SFMT_FMOVLS, SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL
, SH64_MEDIA_SFMT_FPUTSCR, SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD
, SH64_MEDIA_SFMT_FSTXS, SH64_MEDIA_SFMT_FSUBD, SH64_MEDIA_SFMT_FTRCDQ, SH64_MEDIA_SFMT_FTRVS
, SH64_MEDIA_SFMT_GETCFG, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR, SH64_MEDIA_SFMT_LDB
, SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW, SH64_MEDIA_SFMT_LDHIL
, SH64_MEDIA_SFMT_LDHIQ, SH64_MEDIA_SFMT_LDLOL, SH64_MEDIA_SFMT_LDLOQ, SH64_MEDIA_SFMT_LDXB
, SH64_MEDIA_SFMT_LDXL, SH64_MEDIA_SFMT_LDXQ, SH64_MEDIA_SFMT_LDXUB, SH64_MEDIA_SFMT_LDXUW
, SH64_MEDIA_SFMT_LDXW, SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MMACNFX_WL, SH64_MEDIA_SFMT_MOVI
, SH64_MEDIA_SFMT_NOP, SH64_MEDIA_SFMT_ORI, SH64_MEDIA_SFMT_PREFI, SH64_MEDIA_SFMT_PTA
, SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCFG, SH64_MEDIA_SFMT_PUTCON
, SH64_MEDIA_SFMT_SHARI, SH64_MEDIA_SFMT_SHORI, SH64_MEDIA_SFMT_STB, SH64_MEDIA_SFMT_STL
, SH64_MEDIA_SFMT_STQ, SH64_MEDIA_SFMT_STW, SH64_MEDIA_SFMT_STHIL, SH64_MEDIA_SFMT_STHIQ
, SH64_MEDIA_SFMT_STLOL, SH64_MEDIA_SFMT_STLOQ, SH64_MEDIA_SFMT_STXB, SH64_MEDIA_SFMT_STXL
, SH64_MEDIA_SFMT_STXQ, SH64_MEDIA_SFMT_STXW, SH64_MEDIA_SFMT_SWAPQ, SH64_MEDIA_SFMT_TRAPA
, SH64_MEDIA_SFMT_XORI
} SH64_MEDIA_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_putcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_getcfg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_pt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_ftrvs (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fsqrtd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdivd (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_cond_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_blink (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*targetreg*/);
extern int sh64_model_sh5_media_u_use_tr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_use_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_mtrx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
extern int sh64_model_sh5_media_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fcnv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fcmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fsqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fdiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_fpu_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_use_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldsl_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_fpscr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_flds_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_fpul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_set_fr_0 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_set_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_load_fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_maybe_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_fpu (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_write_back (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_multiply_result (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_shift (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_tas (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mulsw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_mull (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_dmul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_macw (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
extern int sh64_model_sh5_media_u_load_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
extern int sh64_model_sh5_media_u_stc_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl_vbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldcl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_tbit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_gbr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_ldc_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_set_sr_bit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_use_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_load_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sts_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_lds_pr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_memory_access (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_logic_b (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jsr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_jmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_sx (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int sh64_model_sh5_media_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/* Profiling before/after handlers (user written) */
extern void sh64_model_insn_before (SIM_CPU *, int /*first_p*/);
extern void sh64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
#endif /* SH64_MEDIA_DECODE_H */

16
sim/sh64/decode.h
View File

@ -1,16 +0,0 @@
#ifndef DECODE_H
#define DECODE_H
#undef WITH_PROFILE_MODEL_P
#ifdef WANT_ISA_COMPACT
#include "decode-compact.h"
#include "defs-compact.h"
#endif /* WANT_ISA_COMPACT */
#ifdef WANT_ISA_MEDIA
#include "decode-media.h"
#include "defs-media.h"
#endif /* WANT_ISA_MEDIA */
#endif /* DECODE_H */

509
sim/sh64/defs-compact.h
View File

@ -1,509 +0,0 @@
/* ISA definitions header for compact.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DEFS_SH64_COMPACT_H
#define DEFS_SH64_COMPACT_H
/* Instruction argument buffer. */
union sem_fields {
struct { /* no operands */
int empty;
} sfmt_empty;
struct { /* */
IADDR i_disp12;
} sfmt_bra_compact;
struct { /* */
IADDR i_disp8;
} sfmt_bf_compact;
struct { /* */
SI f_imm8x2;
UINT f_rn;
} sfmt_movw10_compact;
struct { /* */
SI f_imm4x2;
UINT f_rm;
} sfmt_movw5_compact;
struct { /* */
SI f_imm8x4;
UINT f_rn;
} sfmt_movl10_compact;
struct { /* */
UINT f_imm4;
UINT f_rm;
} sfmt_movb5_compact;
struct { /* */
INT f_imm20;
UINT f_rn;
} sfmt_movi20_compact;
struct { /* */
SI f_vm;
SI f_vn;
} sfmt_fipr_compact;
struct { /* */
UINT f_imm8;
UINT f_rn;
} sfmt_addi_compact;
struct { /* */
SI f_imm12x4;
UINT f_rm;
UINT f_rn;
} sfmt_movl12_compact;
struct { /* */
SI f_imm4x4;
UINT f_rm;
UINT f_rn;
} sfmt_movl5_compact;
struct { /* */
SI f_dm;
SI f_imm12x8;
UINT f_rn;
} sfmt_fmov9_compact;
struct { /* */
SI f_dn;
SI f_imm12x8;
UINT f_rm;
} sfmt_fmov8_compact;
#if WITH_SCACHE_PBB
/* Writeback handler. */
struct {
/* Pointer to argbuf entry for insn whose results need writing back. */
const struct argbuf *abuf;
} write;
/* x-before handler */
struct {
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
int first_p;
} before;
/* x-after handler */
struct {
int empty;
} after;
/* This entry is used to terminate each pbb. */
struct {
/* Number of insns in pbb. */
int insn_count;
/* Next pbb to execute. */
SCACHE *next;
SCACHE *branch_target;
} chain;
#endif
};
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
IADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* ??? Temporary hack for skip insns. */
char skip_count;
char unused;
/* cpu specific data follows */
union sem semantic;
int written;
union sem_fields fields;
};
/* A cached insn.
??? SCACHE used to contain more than just argbuf. We could delete the
type entirely and always just use ARGBUF, but for future concerns and as
a level of abstraction it is left in. */
struct scache {
struct argbuf argbuf;
};
/* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */
#define EXTRACT_IFMT_EMPTY_VARS \
unsigned int length;
#define EXTRACT_IFMT_EMPTY_CODE \
length = 0; \
#define EXTRACT_IFMT_ADD_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_ADD_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_ADDI_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_imm8; \
unsigned int length;
#define EXTRACT_IFMT_ADDI_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_AND_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_AND_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_ANDI_COMPACT_VARS \
UINT f_op8; \
UINT f_imm8; \
unsigned int length;
#define EXTRACT_IFMT_ANDI_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_ANDB_COMPACT_VARS \
UINT f_op8; \
UINT f_imm8; \
unsigned int length;
#define EXTRACT_IFMT_ANDB_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_BF_COMPACT_VARS \
UINT f_op8; \
SI f_disp8; \
unsigned int length;
#define EXTRACT_IFMT_BF_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (1))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BRA_COMPACT_VARS \
UINT f_op4; \
SI f_disp12; \
unsigned int length;
#define EXTRACT_IFMT_BRA_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_disp12 = ((((EXTRACT_MSB0_SINT (insn, 16, 4, 12)) << (1))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BRAF_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_sub8; \
unsigned int length;
#define EXTRACT_IFMT_BRAF_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_BRK_COMPACT_VARS \
UINT f_op16; \
unsigned int length;
#define EXTRACT_IFMT_BRK_COMPACT_CODE \
length = 2; \
f_op16 = EXTRACT_MSB0_UINT (insn, 16, 0, 16); \
#define EXTRACT_IFMT_FABS_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_sub8; \
unsigned int length;
#define EXTRACT_IFMT_FABS_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FADD_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_FADD_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FCNVDS_COMPACT_VARS \
UINT f_op4; \
SI f_dn; \
UINT f_7_1; \
UINT f_sub8; \
unsigned int length;
#define EXTRACT_IFMT_FCNVDS_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_dn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 3)) << (1)); \
f_7_1 = EXTRACT_MSB0_UINT (insn, 16, 7, 1); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FIPR_COMPACT_VARS \
UINT f_op4; \
SI f_vn; \
SI f_vm; \
UINT f_sub8; \
unsigned int length;
#define EXTRACT_IFMT_FIPR_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); \
f_vm = ((EXTRACT_MSB0_UINT (insn, 16, 6, 2)) << (2)); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FLDS_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_sub8; \
unsigned int length;
#define EXTRACT_IFMT_FLDS_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_sub8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_FMAC_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_FMAC_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV1_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_FMOV1_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV2_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_FMOV2_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV5_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_FMOV5_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_FMOV8_COMPACT_VARS \
UINT f_op4; \
SI f_dn; \
UINT f_7_1; \
UINT f_rm; \
UINT f_sub4; \
UINT f_16_4; \
SI f_imm12x8; \
unsigned int length;
#define EXTRACT_IFMT_FMOV8_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_dn = ((EXTRACT_MSB0_UINT (insn, 32, 4, 3)) << (1)); \
f_7_1 = EXTRACT_MSB0_UINT (insn, 32, 7, 1); \
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \
f_imm12x8 = ((EXTRACT_MSB0_SINT (insn, 32, 20, 12)) << (3)); \
#define EXTRACT_IFMT_FMOV9_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
SI f_dm; \
UINT f_11_1; \
UINT f_sub4; \
UINT f_16_4; \
SI f_imm12x8; \
unsigned int length;
#define EXTRACT_IFMT_FMOV9_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_dm = ((EXTRACT_MSB0_UINT (insn, 32, 8, 3)) << (1)); \
f_11_1 = EXTRACT_MSB0_UINT (insn, 32, 11, 1); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \
f_imm12x8 = ((EXTRACT_MSB0_SINT (insn, 32, 20, 12)) << (3)); \
#define EXTRACT_IFMT_FTRV_COMPACT_VARS \
UINT f_op4; \
SI f_vn; \
UINT f_sub10; \
unsigned int length;
#define EXTRACT_IFMT_FTRV_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_vn = ((EXTRACT_MSB0_UINT (insn, 16, 4, 2)) << (2)); \
f_sub10 = EXTRACT_MSB0_UINT (insn, 16, 6, 10); \
#define EXTRACT_IFMT_MOVI20_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
INT f_imm20_hi; \
UINT f_imm20_lo; \
INT f_imm20; \
UINT f_sub4; \
unsigned int length;
#define EXTRACT_IFMT_MOVI20_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_imm20_hi = EXTRACT_MSB0_SINT (insn, 32, 8, 4); \
f_imm20_lo = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
f_imm20 = ((((f_imm20_hi) << (16))) | (f_imm20_lo));\
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
#define EXTRACT_IFMT_MOVB5_COMPACT_VARS \
UINT f_op8; \
UINT f_rm; \
UINT f_imm4; \
unsigned int length;
#define EXTRACT_IFMT_MOVB5_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_imm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_MOVL4_COMPACT_VARS \
UINT f_op8; \
SI f_imm8x4; \
unsigned int length;
#define EXTRACT_IFMT_MOVL4_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
#define EXTRACT_IFMT_MOVL5_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
SI f_imm4x4; \
unsigned int length;
#define EXTRACT_IFMT_MOVL5_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_imm4x4 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (2)); \
#define EXTRACT_IFMT_MOVL10_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
SI f_imm8x4; \
unsigned int length;
#define EXTRACT_IFMT_MOVL10_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_imm8x4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
#define EXTRACT_IFMT_MOVL12_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
UINT f_rm; \
UINT f_sub4; \
UINT f_16_4; \
SI f_imm12x4; \
unsigned int length;
#define EXTRACT_IFMT_MOVL12_COMPACT_CODE \
length = 4; \
f_op4 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_rm = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_sub4 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_16_4 = EXTRACT_MSB0_UINT (insn, 32, 16, 4); \
f_imm12x4 = ((EXTRACT_MSB0_SINT (insn, 32, 20, 12)) << (2)); \
#define EXTRACT_IFMT_MOVW4_COMPACT_VARS \
UINT f_op8; \
SI f_imm8x2; \
unsigned int length;
#define EXTRACT_IFMT_MOVW4_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
#define EXTRACT_IFMT_MOVW5_COMPACT_VARS \
UINT f_op8; \
UINT f_rm; \
SI f_imm4x2; \
unsigned int length;
#define EXTRACT_IFMT_MOVW5_COMPACT_CODE \
length = 2; \
f_op8 = EXTRACT_MSB0_UINT (insn, 16, 0, 8); \
f_rm = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_imm4x2 = ((EXTRACT_MSB0_UINT (insn, 16, 12, 4)) << (1)); \
#define EXTRACT_IFMT_MOVW10_COMPACT_VARS \
UINT f_op4; \
UINT f_rn; \
SI f_imm8x2; \
unsigned int length;
#define EXTRACT_IFMT_MOVW10_COMPACT_CODE \
length = 2; \
f_op4 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_rn = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_imm8x2 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
#endif /* DEFS_SH64_COMPACT_H */

920
sim/sh64/defs-media.h
View File

@ -1,920 +0,0 @@
/* ISA definitions header for media.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DEFS_SH64_MEDIA_H
#define DEFS_SH64_MEDIA_H
/* Instruction argument buffer. */
union sem_fields {
struct { /* no operands */
int empty;
} sfmt_empty;
struct { /* */
UINT f_dest;
UINT f_uimm16;
} sfmt_shori;
struct { /* */
DI f_disp16;
UINT f_tra;
} sfmt_pta;
struct { /* */
INT f_imm16;
UINT f_dest;
} sfmt_movi;
struct { /* */
UINT f_dest;
UINT f_left_right;
} sfmt_fabsd;
struct { /* */
UINT f_dest;
UINT f_trb;
} sfmt_blink;
struct { /* */
INT f_imm6;
UINT f_dest;
UINT f_left;
} sfmt_xori;
struct { /* */
UINT f_dest;
UINT f_left;
UINT f_uimm6;
} sfmt_shari;
struct { /* */
INT f_imm10;
UINT f_dest;
UINT f_left;
} sfmt_ori;
struct { /* */
SI f_disp10x2;
UINT f_dest;
UINT f_left;
} sfmt_lduw;
struct { /* */
INT f_disp6;
UINT f_dest;
UINT f_left;
} sfmt_getcfg;
struct { /* */
SI f_disp10x4;
UINT f_dest;
UINT f_left;
} sfmt_flds;
struct { /* */
SI f_disp10x8;
UINT f_dest;
UINT f_left;
} sfmt_fldd;
struct { /* */
INT f_imm6;
UINT f_left;
UINT f_tra;
} sfmt_beqi;
struct { /* */
UINT f_left;
UINT f_right;
UINT f_tra;
} sfmt_beq;
struct { /* */
INT f_disp10;
UINT f_dest;
UINT f_left;
} sfmt_addi;
struct { /* */
UINT f_dest;
UINT f_left;
UINT f_right;
} sfmt_add;
#if WITH_SCACHE_PBB
/* Writeback handler. */
struct {
/* Pointer to argbuf entry for insn whose results need writing back. */
const struct argbuf *abuf;
} write;
/* x-before handler */
struct {
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
int first_p;
} before;
/* x-after handler */
struct {
int empty;
} after;
/* This entry is used to terminate each pbb. */
struct {
/* Number of insns in pbb. */
int insn_count;
/* Next pbb to execute. */
SCACHE *next;
SCACHE *branch_target;
} chain;
#endif
};
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
IADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* ??? Temporary hack for skip insns. */
char skip_count;
char unused;
/* cpu specific data follows */
union sem semantic;
int written;
union sem_fields fields;
};
/* A cached insn.
??? SCACHE used to contain more than just argbuf. We could delete the
type entirely and always just use ARGBUF, but for future concerns and as
a level of abstraction it is left in. */
struct scache {
struct argbuf argbuf;
};
/* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */
#define EXTRACT_IFMT_EMPTY_VARS \
unsigned int length;
#define EXTRACT_IFMT_EMPTY_CODE \
length = 0; \
#define EXTRACT_IFMT_ADD_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_ADD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_ADDI_VARS \
UINT f_op; \
UINT f_left; \
INT f_disp10; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_ADDI_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10 = EXTRACT_MSB0_SINT (insn, 32, 12, 10); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_ALLOCO_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
SI f_disp6x32; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_ALLOCO_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp6x32 = ((EXTRACT_MSB0_SINT (insn, 32, 16, 6)) << (5)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_likely; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_BEQ_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BEQI_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
INT f_imm6; \
UINT f_likely; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_BEQI_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_imm6 = EXTRACT_MSB0_SINT (insn, 32, 16, 6); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BLINK_VARS \
UINT f_op; \
UINT f_6_3; \
UINT f_trb; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_BLINK_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_6_3 = EXTRACT_MSB0_UINT (insn, 32, 6, 3); \
f_trb = EXTRACT_MSB0_UINT (insn, 32, 9, 3); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BRK_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_BRK_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_BYTEREV_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_BYTEREV_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FABSD_VARS \
UINT f_op; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FABSD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FABSS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FABSS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FADDD_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FADDD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FADDS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FADDS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCMPEQD_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FCMPEQD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCMPEQS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FCMPEQS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCNVDS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FCNVDS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FCNVSD_VARS \
UINT f_op; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FCNVSD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FGETSCR_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FGETSCR_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FIPRS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FIPRS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDD_VARS \
UINT f_op; \
UINT f_left; \
SI f_disp10x8; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FLDD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x8 = ((EXTRACT_MSB0_SINT (insn, 32, 12, 10)) << (3)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDP_VARS \
UINT f_op; \
UINT f_left; \
SI f_disp10x8; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FLDP_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x8 = ((EXTRACT_MSB0_SINT (insn, 32, 12, 10)) << (3)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDS_VARS \
UINT f_op; \
UINT f_left; \
SI f_disp10x4; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FLDS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x4 = ((EXTRACT_MSB0_SINT (insn, 32, 12, 10)) << (2)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDXD_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FLDXD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FLDXP_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FLDXP_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FMOVDQ_VARS \
UINT f_op; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FMOVDQ_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FMOVLS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FMOVLS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FMOVSL_VARS \
UINT f_op; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FMOVSL_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FPUTSCR_VARS \
UINT f_op; \
UINT f_left; \
UINT f_right; \
UINT f_left_right; \
UINT f_ext; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FPUTSCR_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_left_right = f_left;\
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FSTXD_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FSTXD_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_FTRVS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_FTRVS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_GETCFG_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
INT f_disp6; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_GETCFG_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp6 = EXTRACT_MSB0_SINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_GETCON_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_GETCON_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_LDL_VARS \
UINT f_op; \
UINT f_left; \
SI f_disp10x4; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_LDL_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x4 = ((EXTRACT_MSB0_SINT (insn, 32, 12, 10)) << (2)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_LDQ_VARS \
UINT f_op; \
UINT f_left; \
SI f_disp10x8; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_LDQ_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x8 = ((EXTRACT_MSB0_SINT (insn, 32, 12, 10)) << (3)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_MMACNFX_WL_VARS \
UINT f_op; \
UINT f_ext; \
UINT f_right; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_MMACNFX_WL_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_MOVI_VARS \
UINT f_op; \
INT f_imm16; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_MOVI_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_imm16 = EXTRACT_MSB0_SINT (insn, 32, 6, 16); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_ORI_VARS \
UINT f_op; \
UINT f_left; \
INT f_imm10; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_ORI_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_imm10 = EXTRACT_MSB0_SINT (insn, 32, 12, 10); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PREFI_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
SI f_disp6x32; \
UINT f_right; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_PREFI_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp6x32 = ((EXTRACT_MSB0_SINT (insn, 32, 16, 6)) << (5)); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PTA_VARS \
UINT f_op; \
DI f_disp16; \
UINT f_likely; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_PTA_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 6, 16)) << (2))) + (pc)); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PTABS_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_likely; \
UINT f_23_2; \
UINT f_tra; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_PTABS_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_likely = EXTRACT_MSB0_UINT (insn, 32, 22, 1); \
f_23_2 = EXTRACT_MSB0_UINT (insn, 32, 23, 2); \
f_tra = EXTRACT_MSB0_UINT (insn, 32, 25, 3); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_PUTCON_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_PUTCON_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_SHARI_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_uimm6; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_SHARI_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_uimm6 = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_SHORI_VARS \
UINT f_op; \
UINT f_uimm16; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_SHORI_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 6, 16); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_STW_VARS \
UINT f_op; \
UINT f_left; \
SI f_disp10x2; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_STW_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_disp10x2 = ((EXTRACT_MSB0_SINT (insn, 32, 12, 10)) << (1)); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#define EXTRACT_IFMT_TRAPA_VARS \
UINT f_op; \
UINT f_left; \
UINT f_ext; \
UINT f_right; \
UINT f_dest; \
UINT f_rsvd; \
unsigned int length;
#define EXTRACT_IFMT_TRAPA_CODE \
length = 4; \
f_op = EXTRACT_MSB0_UINT (insn, 32, 0, 6); \
f_left = EXTRACT_MSB0_UINT (insn, 32, 6, 6); \
f_ext = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_right = EXTRACT_MSB0_UINT (insn, 32, 16, 6); \
f_dest = EXTRACT_MSB0_UINT (insn, 32, 22, 6); \
f_rsvd = EXTRACT_MSB0_UINT (insn, 32, 28, 4); \
#endif /* DEFS_SH64_MEDIA_H */

34
sim/sh64/eng-compact.h
View File

@ -1,34 +0,0 @@
/* engine configuration for sh64 */
/* WITH_FAST: non-zero if a fast version of the engine is available
in addition to the full-featured version. */
#define WITH_FAST 1
/* WITH_SCACHE_PBB_SH64_COMPACT: non-zero if the pbb engine was selected. */
#define WITH_SCACHE_PBB_SH64_COMPACT 1
/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */
#define HAVE_PARALLEL_INSNS 0
#define WITH_PARALLEL_READ 0
#define WITH_PARALLEL_WRITE 0
#define WITH_PARALLEL_GENWRITE 0
/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is
implemented as a switch(). */
#define WITH_SEM_SWITCH_FULL 0
/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is
implemented as a switch(). */
#define WITH_SEM_SWITCH_FAST 1
/* Functions defined in the generated mainloop.c file
(which doesn't necessarily have that file name). */
extern ENGINE_FN sh64_compact_engine_run_full;
extern ENGINE_FN sh64_compact_engine_run_fast;
extern SEM_PC sh64_compact_pbb_begin (SIM_CPU *, int);
extern SEM_PC sh64_compact_pbb_chain (SIM_CPU *, SEM_ARG);
extern SEM_PC sh64_compact_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
extern void sh64_compact_pbb_before (SIM_CPU *, SCACHE *);
extern void sh64_compact_pbb_after (SIM_CPU *, SCACHE *);

34
sim/sh64/eng-media.h
View File

@ -1,34 +0,0 @@
/* engine configuration for sh64 */
/* WITH_FAST: non-zero if a fast version of the engine is available
in addition to the full-featured version. */
#define WITH_FAST 1
/* WITH_SCACHE_PBB_SH64_MEDIA: non-zero if the pbb engine was selected. */
#define WITH_SCACHE_PBB_SH64_MEDIA 1
/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */
#define HAVE_PARALLEL_INSNS 0
#define WITH_PARALLEL_READ 0
#define WITH_PARALLEL_WRITE 0
#define WITH_PARALLEL_GENWRITE 0
/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is
implemented as a switch(). */
#define WITH_SEM_SWITCH_FULL 0
/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is
implemented as a switch(). */
#define WITH_SEM_SWITCH_FAST 1
/* Functions defined in the generated mainloop.c file
(which doesn't necessarily have that file name). */
extern ENGINE_FN sh64_media_engine_run_full;
extern ENGINE_FN sh64_media_engine_run_fast;
extern SEM_PC sh64_media_pbb_begin (SIM_CPU *, int);
extern SEM_PC sh64_media_pbb_chain (SIM_CPU *, SEM_ARG);
extern SEM_PC sh64_media_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
extern void sh64_media_pbb_before (SIM_CPU *, SCACHE *);
extern void sh64_media_pbb_after (SIM_CPU *, SCACHE *);

23
sim/sh64/eng.h
View File

@ -1,23 +0,0 @@
/* Engine declarations.
Copyright (C) 2000-2021 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Include declarations for SHmedia and SHcompact ISAs. */
#include "eng-compact.h"
#include "eng-media.h"

635
sim/sh64/mloop-compact.c
View File

@ -1,635 +0,0 @@
/* This file is generated by the genmloop script. DO NOT EDIT! */
/* Enable switch() support in cgen headers. */
#define SEM_IN_SWITCH
#define WANT_CPU sh64
#define WANT_CPU_SH64
#include "sim-main.h"
#include "bfd.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
#include "sim-assert.h"
/* Fill in the administrative ARGBUF fields required by all insns,
virtual and real. */
static INLINE void
sh64_compact_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
PCADDR pc, int fast_p)
{
#if WITH_SCACHE
SEM_SET_CODE (abuf, idesc, fast_p);
ARGBUF_ADDR (abuf) = pc;
#endif
ARGBUF_IDESC (abuf) = idesc;
}
/* Fill in tracing/profiling fields of an ARGBUF. */
static INLINE void
sh64_compact_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
int trace_p, int profile_p)
{
ARGBUF_TRACE_P (abuf) = trace_p;
ARGBUF_PROFILE_P (abuf) = profile_p;
}
#if WITH_SCACHE_PBB
/* Emit the "x-before" handler.
x-before is emitted before each insn (serial or parallel).
This is as opposed to x-after which is only emitted at the end of a group
of parallel insns. */
static INLINE void
sh64_compact_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
{
ARGBUF *abuf = &sc[0].argbuf;
const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEFORE];
abuf->fields.before.first_p = first_p;
sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
/* no need to set trace_p,profile_p */
}
/* Emit the "x-after" handler.
x-after is emitted after a serial insn or at the end of a group of
parallel insns. */
static INLINE void
sh64_compact_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
{
ARGBUF *abuf = &sc[0].argbuf;
const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_AFTER];
sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
/* no need to set trace_p,profile_p */
}
#endif /* WITH_SCACHE_PBB */
static INLINE const IDESC *
extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
int fast_p)
{
const IDESC *id = sh64_compact_decode (current_cpu, pc, insn, insn, abuf);
sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
if (! fast_p)
{
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
sh64_compact_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
}
return id;
}
static INLINE SEM_PC
execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
{
SEM_PC vpc;
if (fast_p)
{
#if ! WITH_SEM_SWITCH_FAST
#if WITH_SCACHE
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
#else
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
#endif
#else
abort ();
#endif /* WITH_SEM_SWITCH_FAST */
}
else
{
#if ! WITH_SEM_SWITCH_FULL
ARGBUF *abuf = &sc->argbuf;
const IDESC *idesc = abuf->idesc;
#if WITH_SCACHE_PBB
int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
#else
int virtual_p = 0;
#endif
if (! virtual_p)
{
/* FIXME: call x-before */
if (ARGBUF_PROFILE_P (abuf))
PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (abuf))
sh64_compact_model_insn_before (current_cpu, 1 /*first_p*/);
CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
CGEN_TRACE_INSN (current_cpu, idesc->idata,
(const struct argbuf *) abuf, abuf->addr);
}
#if WITH_SCACHE
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
#else
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
#endif
if (! virtual_p)
{
/* FIXME: call x-after */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (abuf))
{
int cycles;
cycles = (*idesc->timing->model_fn) (current_cpu, sc);
sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
}
CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
}
#else
abort ();
#endif /* WITH_SEM_SWITCH_FULL */
}
return vpc;
}
/* Record address of cti terminating a pbb. */
#define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
/* Record number of [real] insns in pbb. */
#define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
/* Fetch and extract a pseudo-basic-block.
FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
INLINE SEM_PC
sh64_compact_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
{
SEM_PC new_vpc;
PCADDR pc;
SCACHE *sc;
int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
pc = GET_H_PC ();
new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
if (! new_vpc)
{
/* Leading '_' to avoid collision with mainloop.in. */
int _insn_count = 0;
SCACHE *orig_sc = sc;
SCACHE *_cti_sc = NULL;
int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
/* First figure out how many instructions to compile.
MAX_INSNS is the size of the allocated buffer, which includes space
for before/after handlers if they're being used.
SLICE_INSNS is the maxinum number of real insns that can be
executed. Zero means "as many as we want". */
/* ??? max_insns is serving two incompatible roles.
1) Number of slots available in scache buffer.
2) Number of real insns to execute.
They're incompatible because there are virtual insns emitted too
(chain,cti-chain,before,after handlers). */
if (slice_insns == 1)
{
/* No need to worry about extra slots required for virtual insns
and parallel exec support because MAX_CHAIN_LENGTH is
guaranteed to be big enough to execute at least 1 insn! */
max_insns = 1;
}
else
{
/* Allow enough slop so that while compiling insns, if max_insns > 0
then there's guaranteed to be enough space to emit one real insn.
MAX_CHAIN_LENGTH is typically much longer than
the normal number of insns between cti's anyway. */
max_insns -= (1 /* one for the trailing chain insn */
+ (FAST_P
? 0
: (1 + MAX_PARALLEL_INSNS) /* before+after */)
+ (MAX_PARALLEL_INSNS > 1
? (MAX_PARALLEL_INSNS * 2)
: 0));
/* Account for before/after handlers. */
if (! FAST_P)
slice_insns *= 3;
if (slice_insns > 0
&& slice_insns < max_insns)
max_insns = slice_insns;
}
new_vpc = sc;
/* SC,PC must be updated to point passed the last entry used.
SET_CTI_VPC must be called if pbb is terminated by a cti.
SET_INSN_COUNT must be called to record number of real insns in
pbb [could be computed by us of course, extra cpu but perhaps
negligible enough]. */
/* begin extract-pbb */
{
const IDESC *idesc;
int icount = 0;
while (max_insns > 0)
{
UHI insn = GETIMEMUHI (current_cpu, pc);
idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
SEM_SKIP_COMPILE (current_cpu, sc, 1);
++sc;
--max_insns;
++icount;
pc += idesc->length;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
{
USI insn = GETIMEMUHI (current_cpu, pc);
idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
if (IDESC_CTI_P (idesc) ||
CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_ILLSLOT))
{
SIM_DESC sd = CPU_STATE (current_cpu);
sim_io_eprintf (CPU_STATE (current_cpu),
"malformed program, `%s' insn in delay slot\n",
CGEN_INSN_NAME (idesc->idata));
sim_engine_halt (sd, current_cpu, NULL, pc,
sim_stopped, SIM_SIGILL);
}
else
{
++sc;
--max_insns;
++icount;
pc += idesc->length;
}
}
break;
}
}
Finish:
SET_INSN_COUNT (icount);
}
/* end extract-pbb */
/* The last one is a pseudo-insn to link to the next chain.
It is also used to record the insn count for this chain. */
{
const IDESC *id;
/* Was pbb terminated by a cti? */
if (_cti_sc)
{
id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CTI_CHAIN];
}
else
{
id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CHAIN];
}
SEM_SET_CODE (&sc->argbuf, id, FAST_P);
sc->argbuf.idesc = id;
sc->argbuf.addr = pc;
sc->argbuf.fields.chain.insn_count = _insn_count;
sc->argbuf.fields.chain.next = 0;
sc->argbuf.fields.chain.branch_target = 0;
++sc;
}
/* Update the pointer to the next free entry, may not have used as
many entries as was asked for. */
CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
/* Record length of chain if profiling.
This includes virtual insns since they count against
max_insns too. */
if (! FAST_P)
PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
}
return new_vpc;
}
/* Chain to the next block from a non-cti terminated previous block. */
INLINE SEM_PC
sh64_compact_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
SET_H_PC (abuf->addr);
/* If not running forever, exit back to main loop. */
if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
/* Also exit back to main loop if there's an event.
Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
at the "right" time, but then that was what was asked for.
There is no silver bullet for simulator engines.
??? Clearly this needs a cleaner interface.
At present it's just so Ctrl-C works. */
|| STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
CPU_RUNNING_P (current_cpu) = 0;
/* If chained to next block, go straight to it. */
if (abuf->fields.chain.next)
return abuf->fields.chain.next;
/* See if next block has already been compiled. */
abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
if (abuf->fields.chain.next)
return abuf->fields.chain.next;
/* Nope, so next insn is a virtual insn to invoke the compiler
(begin a pbb). */
return CPU_SCACHE_PBB_BEGIN (current_cpu);
}
/* Chain to the next block from a cti terminated previous block.
BR_TYPE indicates whether the branch was taken and whether we can cache
the vpc of the branch target.
NEW_PC is the target's branch address, and is only valid if
BR_TYPE != SEM_BRANCH_UNTAKEN. */
INLINE SEM_PC
sh64_compact_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
SEM_BRANCH_TYPE br_type, PCADDR new_pc)
{
SEM_PC *new_vpc_ptr;
PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
/* If we have switched ISAs, exit back to main loop.
Set idesc to 0 to cause the engine to point to the right insn table. */
if (new_pc & 1)
{
/* Switch to SHmedia. */
CPU_IDESC_SEM_INIT_P (current_cpu) = 0;
CPU_RUNNING_P (current_cpu) = 0;
}
/* If not running forever, exit back to main loop. */
if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
/* Also exit back to main loop if there's an event.
Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
at the "right" time, but then that was what was asked for.
There is no silver bullet for simulator engines.
??? Clearly this needs a cleaner interface.
At present it's just so Ctrl-C works. */
|| STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
CPU_RUNNING_P (current_cpu) = 0;
/* Restart compiler if we branched to an uncacheable address
(e.g. "j reg"). */
if (br_type == SEM_BRANCH_UNCACHEABLE)
{
SET_H_PC (new_pc);
return CPU_SCACHE_PBB_BEGIN (current_cpu);
}
/* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
next chain ptr. */
if (br_type == SEM_BRANCH_UNTAKEN)
{
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
new_pc = abuf->addr;
SET_H_PC (new_pc);
new_vpc_ptr = &abuf->fields.chain.next;
}
else
{
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
SET_H_PC (new_pc);
new_vpc_ptr = &abuf->fields.chain.branch_target;
}
/* If chained to next block, go straight to it. */
if (*new_vpc_ptr)
return *new_vpc_ptr;
/* See if next block has already been compiled. */
*new_vpc_ptr = scache_lookup (current_cpu, new_pc);
if (*new_vpc_ptr)
return *new_vpc_ptr;
/* Nope, so next insn is a virtual insn to invoke the compiler
(begin a pbb). */
return CPU_SCACHE_PBB_BEGIN (current_cpu);
}
/* x-before handler.
This is called before each insn. */
void
sh64_compact_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
{
SEM_ARG sem_arg = sc;
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int first_p = abuf->fields.before.first_p;
const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
const IDESC *cur_idesc = cur_abuf->idesc;
PCADDR pc = cur_abuf->addr;
if (ARGBUF_PROFILE_P (cur_abuf))
PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
/* If this isn't the first insn, finish up the previous one. */
if (! first_p)
{
if (PROFILE_MODEL_P (current_cpu))
{
const SEM_ARG prev_sem_arg = sc - 1;
const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
const IDESC *prev_idesc = prev_abuf->idesc;
int cycles;
/* ??? May want to measure all insns if doing insn tracing. */
if (ARGBUF_PROFILE_P (prev_abuf))
{
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
sh64_compact_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
}
}
CGEN_TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
}
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (cur_abuf))
sh64_compact_model_insn_before (current_cpu, first_p);
CGEN_TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
CGEN_TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
}
/* x-after handler.
This is called after a serial insn or at the end of a group of parallel
insns. */
void
sh64_compact_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
{
SEM_ARG sem_arg = sc;
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
const SEM_ARG prev_sem_arg = sc - 1;
const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
/* ??? May want to measure all insns if doing insn tracing. */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (prev_abuf))
{
const IDESC *prev_idesc = prev_abuf->idesc;
int cycles;
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
}
CGEN_TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
}
#define FAST_P 0
void
sh64_compact_engine_run_full (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
/* virtual program counter */
SEM_PC vpc;
#if WITH_SEM_SWITCH_FULL
/* For communication between cti's and cti-chain. */
SEM_BRANCH_TYPE pbb_br_type;
PCADDR pbb_br_npc;
#endif
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
{
/* ??? 'twould be nice to move this up a level and only call it once.
On the other hand, in the "let's go fast" case the test is only done
once per pbb (since we only return to the main loop at the end of
a pbb). And in the "let's run until we're done" case we don't return
until the program exits. */
#if WITH_SEM_SWITCH_FULL
#if defined (__GNUC__)
/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
#define DEFINE_LABELS
#include "sem-compact-switch.c"
#endif
#else
sh64_compact_sem_init_idesc_table (current_cpu);
#endif
/* Initialize the "begin (compile) a pbb" virtual insn. */
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
& CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
CPU_RUNNING_P (current_cpu) = 1;
/* ??? In the case where we're returning to the main loop after every
pbb we don't want to call pbb_begin each time (which hashes on the pc
and does a table lookup). A way to speed this up is to save vpc
between calls. */
vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
do
{
/* begin full-exec-pbb */
{
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
#define DEFINE_SWITCH
#include "sem-compact-switch.c"
#else
vpc = execute (current_cpu, vpc, FAST_P);
#endif
}
/* end full-exec-pbb */
}
while (CPU_RUNNING_P (current_cpu));
}
#undef FAST_P
#define FAST_P 1
void
sh64_compact_engine_run_fast (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
/* virtual program counter */
SEM_PC vpc;
#if WITH_SEM_SWITCH_FAST
/* For communication between cti's and cti-chain. */
SEM_BRANCH_TYPE pbb_br_type;
PCADDR pbb_br_npc;
#endif
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
{
/* ??? 'twould be nice to move this up a level and only call it once.
On the other hand, in the "let's go fast" case the test is only done
once per pbb (since we only return to the main loop at the end of
a pbb). And in the "let's run until we're done" case we don't return
until the program exits. */
#if WITH_SEM_SWITCH_FAST
#if defined (__GNUC__)
/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
#define DEFINE_LABELS
#include "sem-compact-switch.c"
#endif
#else
sh64_compact_semf_init_idesc_table (current_cpu);
#endif
/* Initialize the "begin (compile) a pbb" virtual insn. */
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
& CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
CPU_RUNNING_P (current_cpu) = 1;
/* ??? In the case where we're returning to the main loop after every
pbb we don't want to call pbb_begin each time (which hashes on the pc
and does a table lookup). A way to speed this up is to save vpc
between calls. */
vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
do
{
/* begin fast-exec-pbb */
{
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
#define DEFINE_SWITCH
#include "sem-compact-switch.c"
#else
vpc = execute (current_cpu, vpc, FAST_P);
#endif
}
/* end fast-exec-pbb */
}
while (CPU_RUNNING_P (current_cpu));
}
#undef FAST_P

624
sim/sh64/mloop-media.c
View File

@ -1,624 +0,0 @@
/* This file is generated by the genmloop script. DO NOT EDIT! */
/* Enable switch() support in cgen headers. */
#define SEM_IN_SWITCH
#define WANT_CPU sh64
#define WANT_CPU_SH64
#include "sim-main.h"
#include "bfd.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
#include "sim-assert.h"
/* Fill in the administrative ARGBUF fields required by all insns,
virtual and real. */
static INLINE void
sh64_media_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
PCADDR pc, int fast_p)
{
#if WITH_SCACHE
SEM_SET_CODE (abuf, idesc, fast_p);
ARGBUF_ADDR (abuf) = pc;
#endif
ARGBUF_IDESC (abuf) = idesc;
}
/* Fill in tracing/profiling fields of an ARGBUF. */
static INLINE void
sh64_media_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
int trace_p, int profile_p)
{
ARGBUF_TRACE_P (abuf) = trace_p;
ARGBUF_PROFILE_P (abuf) = profile_p;
}
#if WITH_SCACHE_PBB
/* Emit the "x-before" handler.
x-before is emitted before each insn (serial or parallel).
This is as opposed to x-after which is only emitted at the end of a group
of parallel insns. */
static INLINE void
sh64_media_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
{
ARGBUF *abuf = &sc[0].argbuf;
const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEFORE];
abuf->fields.before.first_p = first_p;
sh64_media_fill_argbuf (current_cpu, abuf, id, pc, 0);
/* no need to set trace_p,profile_p */
}
/* Emit the "x-after" handler.
x-after is emitted after a serial insn or at the end of a group of
parallel insns. */
static INLINE void
sh64_media_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
{
ARGBUF *abuf = &sc[0].argbuf;
const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_AFTER];
sh64_media_fill_argbuf (current_cpu, abuf, id, pc, 0);
/* no need to set trace_p,profile_p */
}
#endif /* WITH_SCACHE_PBB */
static INLINE const IDESC *
extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
int fast_p)
{
const IDESC *id = sh64_media_decode (current_cpu, pc, insn, insn, abuf);
sh64_media_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
if (! fast_p)
{
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
sh64_media_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
}
return id;
}
static INLINE SEM_PC
execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
{
SEM_PC vpc;
if (fast_p)
{
#if ! WITH_SEM_SWITCH_FAST
#if WITH_SCACHE
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
#else
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
#endif
#else
abort ();
#endif /* WITH_SEM_SWITCH_FAST */
}
else
{
#if ! WITH_SEM_SWITCH_FULL
ARGBUF *abuf = &sc->argbuf;
const IDESC *idesc = abuf->idesc;
#if WITH_SCACHE_PBB
int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
#else
int virtual_p = 0;
#endif
if (! virtual_p)
{
/* FIXME: call x-before */
if (ARGBUF_PROFILE_P (abuf))
PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (abuf))
sh64_media_model_insn_before (current_cpu, 1 /*first_p*/);
CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
CGEN_TRACE_INSN (current_cpu, idesc->idata,
(const struct argbuf *) abuf, abuf->addr);
}
#if WITH_SCACHE
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
#else
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
#endif
if (! virtual_p)
{
/* FIXME: call x-after */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (abuf))
{
int cycles;
cycles = (*idesc->timing->model_fn) (current_cpu, sc);
sh64_media_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
}
CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
}
#else
abort ();
#endif /* WITH_SEM_SWITCH_FULL */
}
return vpc;
}
/* Record address of cti terminating a pbb. */
#define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
/* Record number of [real] insns in pbb. */
#define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
/* Fetch and extract a pseudo-basic-block.
FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
INLINE SEM_PC
sh64_media_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
{
SEM_PC new_vpc;
PCADDR pc;
SCACHE *sc;
int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
pc = GET_H_PC ();
new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
if (! new_vpc)
{
/* Leading '_' to avoid collision with mainloop.in. */
int _insn_count = 0;
SCACHE *orig_sc = sc;
SCACHE *_cti_sc = NULL;
int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
/* First figure out how many instructions to compile.
MAX_INSNS is the size of the allocated buffer, which includes space
for before/after handlers if they're being used.
SLICE_INSNS is the maxinum number of real insns that can be
executed. Zero means "as many as we want". */
/* ??? max_insns is serving two incompatible roles.
1) Number of slots available in scache buffer.
2) Number of real insns to execute.
They're incompatible because there are virtual insns emitted too
(chain,cti-chain,before,after handlers). */
if (slice_insns == 1)
{
/* No need to worry about extra slots required for virtual insns
and parallel exec support because MAX_CHAIN_LENGTH is
guaranteed to be big enough to execute at least 1 insn! */
max_insns = 1;
}
else
{
/* Allow enough slop so that while compiling insns, if max_insns > 0
then there's guaranteed to be enough space to emit one real insn.
MAX_CHAIN_LENGTH is typically much longer than
the normal number of insns between cti's anyway. */
max_insns -= (1 /* one for the trailing chain insn */
+ (FAST_P
? 0
: (1 + MAX_PARALLEL_INSNS) /* before+after */)
+ (MAX_PARALLEL_INSNS > 1
? (MAX_PARALLEL_INSNS * 2)
: 0));
/* Account for before/after handlers. */
if (! FAST_P)
slice_insns *= 3;
if (slice_insns > 0
&& slice_insns < max_insns)
max_insns = slice_insns;
}
new_vpc = sc;
/* SC,PC must be updated to point passed the last entry used.
SET_CTI_VPC must be called if pbb is terminated by a cti.
SET_INSN_COUNT must be called to record number of real insns in
pbb [could be computed by us of course, extra cpu but perhaps
negligible enough]. */
/* begin extract-pbb */
{
const IDESC *idesc;
int icount = 0;
while (max_insns > 0)
{
USI insn = GETIMEMUSI (current_cpu, pc);
idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
SEM_SKIP_COMPILE (current_cpu, sc, 1);
++sc;
--max_insns;
++icount;
pc += idesc->length;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
{
USI insn = GETIMEMUSI (current_cpu, pc);
idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
++sc;
--max_insns;
++icount;
pc += idesc->length;
}
break;
}
}
Finish:
SET_INSN_COUNT (icount);
}
/* end extract-pbb */
/* The last one is a pseudo-insn to link to the next chain.
It is also used to record the insn count for this chain. */
{
const IDESC *id;
/* Was pbb terminated by a cti? */
if (_cti_sc)
{
id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_CTI_CHAIN];
}
else
{
id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_CHAIN];
}
SEM_SET_CODE (&sc->argbuf, id, FAST_P);
sc->argbuf.idesc = id;
sc->argbuf.addr = pc;
sc->argbuf.fields.chain.insn_count = _insn_count;
sc->argbuf.fields.chain.next = 0;
sc->argbuf.fields.chain.branch_target = 0;
++sc;
}
/* Update the pointer to the next free entry, may not have used as
many entries as was asked for. */
CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
/* Record length of chain if profiling.
This includes virtual insns since they count against
max_insns too. */
if (! FAST_P)
PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
}
return new_vpc;
}
/* Chain to the next block from a non-cti terminated previous block. */
INLINE SEM_PC
sh64_media_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
SET_H_PC (abuf->addr | 1);
/* If not running forever, exit back to main loop. */
if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
/* Also exit back to main loop if there's an event.
Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
at the "right" time, but then that was what was asked for.
There is no silver bullet for simulator engines.
??? Clearly this needs a cleaner interface.
At present it's just so Ctrl-C works. */
|| STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
CPU_RUNNING_P (current_cpu) = 0;
/* If chained to next block, go straight to it. */
if (abuf->fields.chain.next)
return abuf->fields.chain.next;
/* See if next block has already been compiled. */
abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
if (abuf->fields.chain.next)
return abuf->fields.chain.next;
/* Nope, so next insn is a virtual insn to invoke the compiler
(begin a pbb). */
return CPU_SCACHE_PBB_BEGIN (current_cpu);
}
/* Chain to the next block from a cti terminated previous block.
BR_TYPE indicates whether the branch was taken and whether we can cache
the vpc of the branch target.
NEW_PC is the target's branch address, and is only valid if
BR_TYPE != SEM_BRANCH_UNTAKEN. */
INLINE SEM_PC
sh64_media_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
SEM_BRANCH_TYPE br_type, PCADDR new_pc)
{
SEM_PC *new_vpc_ptr;
PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
/* If we have switched ISAs, exit back to main loop.
Set idesc to 0 to cause the engine to point to the right insn table. */
if ((new_pc & 1) == 0)
{
/* Switch to SHcompact. */
CPU_IDESC_SEM_INIT_P (current_cpu) = 0;
CPU_RUNNING_P (current_cpu) = 0;
}
/* If not running forever, exit back to main loop. */
if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
/* Also exit back to main loop if there's an event.
Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
at the "right" time, but then that was what was asked for.
There is no silver bullet for simulator engines.
??? Clearly this needs a cleaner interface.
At present it's just so Ctrl-C works. */
|| STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
CPU_RUNNING_P (current_cpu) = 0;
/* Restart compiler if we branched to an uncacheable address
(e.g. "j reg"). */
if (br_type == SEM_BRANCH_UNCACHEABLE)
{
SET_H_PC (new_pc);
return CPU_SCACHE_PBB_BEGIN (current_cpu);
}
/* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
next chain ptr. */
if (br_type == SEM_BRANCH_UNTAKEN)
{
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
new_pc = abuf->addr;
/* Set bit 0 to stay in SHmedia mode. */
SET_H_PC (new_pc | 1);
new_vpc_ptr = &abuf->fields.chain.next;
}
else
{
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
SET_H_PC (new_pc);
new_vpc_ptr = &abuf->fields.chain.branch_target;
}
/* If chained to next block, go straight to it. */
if (*new_vpc_ptr)
return *new_vpc_ptr;
/* See if next block has already been compiled. */
*new_vpc_ptr = scache_lookup (current_cpu, new_pc);
if (*new_vpc_ptr)
return *new_vpc_ptr;
/* Nope, so next insn is a virtual insn to invoke the compiler
(begin a pbb). */
return CPU_SCACHE_PBB_BEGIN (current_cpu);
}
/* x-before handler.
This is called before each insn. */
void
sh64_media_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
{
SEM_ARG sem_arg = sc;
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int first_p = abuf->fields.before.first_p;
const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
const IDESC *cur_idesc = cur_abuf->idesc;
PCADDR pc = cur_abuf->addr;
if (ARGBUF_PROFILE_P (cur_abuf))
PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
/* If this isn't the first insn, finish up the previous one. */
if (! first_p)
{
if (PROFILE_MODEL_P (current_cpu))
{
const SEM_ARG prev_sem_arg = sc - 1;
const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
const IDESC *prev_idesc = prev_abuf->idesc;
int cycles;
/* ??? May want to measure all insns if doing insn tracing. */
if (ARGBUF_PROFILE_P (prev_abuf))
{
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
sh64_media_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
}
}
CGEN_TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
}
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (cur_abuf))
sh64_media_model_insn_before (current_cpu, first_p);
CGEN_TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
CGEN_TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
}
/* x-after handler.
This is called after a serial insn or at the end of a group of parallel
insns. */
void
sh64_media_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
{
SEM_ARG sem_arg = sc;
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
const SEM_ARG prev_sem_arg = sc - 1;
const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
/* ??? May want to measure all insns if doing insn tracing. */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (prev_abuf))
{
const IDESC *prev_idesc = prev_abuf->idesc;
int cycles;
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
sh64_media_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
}
CGEN_TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
}
#define FAST_P 0
void
sh64_media_engine_run_full (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
/* virtual program counter */
SEM_PC vpc;
#if WITH_SEM_SWITCH_FULL
/* For communication between cti's and cti-chain. */
SEM_BRANCH_TYPE pbb_br_type;
PCADDR pbb_br_npc;
#endif
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
{
/* ??? 'twould be nice to move this up a level and only call it once.
On the other hand, in the "let's go fast" case the test is only done
once per pbb (since we only return to the main loop at the end of
a pbb). And in the "let's run until we're done" case we don't return
until the program exits. */
#if WITH_SEM_SWITCH_FULL
#if defined (__GNUC__)
/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
#define DEFINE_LABELS
#include "sem-media-switch.c"
#endif
#else
sh64_media_sem_init_idesc_table (current_cpu);
#endif
/* Initialize the "begin (compile) a pbb" virtual insn. */
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
& CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN]);
vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN];
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
CPU_RUNNING_P (current_cpu) = 1;
/* ??? In the case where we're returning to the main loop after every
pbb we don't want to call pbb_begin each time (which hashes on the pc
and does a table lookup). A way to speed this up is to save vpc
between calls. */
vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
do
{
/* begin full-exec-pbb */
{
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
#define DEFINE_SWITCH
#define WITH_ISA_COMPACT
#include "sem-media-switch.c"
#else
vpc = execute (current_cpu, vpc, FAST_P);
#endif
}
/* end full-exec-pbb */
}
while (CPU_RUNNING_P (current_cpu));
}
#undef FAST_P
#define FAST_P 1
void
sh64_media_engine_run_fast (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
/* virtual program counter */
SEM_PC vpc;
#if WITH_SEM_SWITCH_FAST
/* For communication between cti's and cti-chain. */
SEM_BRANCH_TYPE pbb_br_type;
PCADDR pbb_br_npc;
#endif
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
{
/* ??? 'twould be nice to move this up a level and only call it once.
On the other hand, in the "let's go fast" case the test is only done
once per pbb (since we only return to the main loop at the end of
a pbb). And in the "let's run until we're done" case we don't return
until the program exits. */
#if WITH_SEM_SWITCH_FAST
#if defined (__GNUC__)
/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
#define DEFINE_LABELS
#include "sem-media-switch.c"
#endif
#else
sh64_media_semf_init_idesc_table (current_cpu);
#endif
/* Initialize the "begin (compile) a pbb" virtual insn. */
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
& CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN]);
vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN];
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
CPU_RUNNING_P (current_cpu) = 1;
/* ??? In the case where we're returning to the main loop after every
pbb we don't want to call pbb_begin each time (which hashes on the pc
and does a table lookup). A way to speed this up is to save vpc
between calls. */
vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
do
{
/* begin fast-exec-pbb */
{
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
#define DEFINE_SWITCH
#define WITH_ISA_COMPACT
#include "sem-media-switch.c"
#else
vpc = execute (current_cpu, vpc, FAST_P);
#endif
}
/* end fast-exec-pbb */
}
while (CPU_RUNNING_P (current_cpu));
}
#undef FAST_P

5210
sim/sh64/sem-compact-switch.c
View File

File diff suppressed because it is too large Load Diff

5589
sim/sh64/sem-compact.c
View File

File diff suppressed because it is too large Load Diff

5656
sim/sh64/sem-media-switch.c
View File

File diff suppressed because it is too large Load Diff

6063
sim/sh64/sem-media.c
View File

File diff suppressed because it is too large Load Diff

3562
sim/sh64/sh-desc.c
View File

File diff suppressed because it is too large Load Diff

315
sim/sh64/sh-desc.h
View File

@ -1,315 +0,0 @@
/* CPU data header for sh.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SH_CPU_H
#define SH_CPU_H
#define CGEN_ARCH sh
/* Given symbol S, return sh_cgen_<S>. */
#define CGEN_SYM(s) sh##_cgen_##s
/* Selected cpu families. */
#define HAVE_CPU_SH64
#define CGEN_INSN_LSB0_P 0
/* Minimum size of any insn (in bytes). */
#define CGEN_MIN_INSN_SIZE 2
/* Maximum size of any insn (in bytes). */
#define CGEN_MAX_INSN_SIZE 4
#define CGEN_INT_INSN_P 1
/* Maximum number of syntax elements in an instruction. */
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
we can't hash on everything up to the space. */
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of fields in an instruction. */
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
/* Enums. */
/* Enum declaration for . */
typedef enum frc_names {
H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
, H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
, H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
, H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
} FRC_NAMES;
/* Enum declaration for . */
typedef enum drc_names {
H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
, H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
} DRC_NAMES;
/* Enum declaration for . */
typedef enum xf_names {
H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
, H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
, H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
, H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
} XF_NAMES;
/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU
, MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU
, MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL
, MACH_SH5, MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
ISA_COMPACT, ISA_MEDIA, ISA_MAX
} ISA_ATTR;
/* Enum declaration for sh4 insn groups. */
typedef enum sh4_group_attr {
SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR
, SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX
} SH4_GROUP_ATTR;
/* Enum declaration for sh4a insn groups. */
typedef enum sh4a_group_attr {
SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR
, SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX
} SH4A_GROUP_ATTR;
/* Number of architecture variants. */
#define MAX_ISAS ((int) ISA_MAX)
#define MAX_MACHS ((int) MACH_MAX)
/* Ifield support. */
/* Ifield attribute indices. */
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
, CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;
/* Number of non-boolean elements in cgen_ifld_attr. */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
/* cgen_ifld attribute accessor macros. */
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
/* Enum declaration for sh ifield types. */
typedef enum ifield_type {
SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
, SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
, SH_F_RN, SH_F_RM, SH_F_7_1, SH_F_11_1
, SH_F_16_4, SH_F_DISP8, SH_F_DISP12, SH_F_IMM8
, SH_F_IMM4, SH_F_IMM4X2, SH_F_IMM4X4, SH_F_IMM8X2
, SH_F_IMM8X4, SH_F_IMM12X4, SH_F_IMM12X8, SH_F_DN
, SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
, SH_F_XM, SH_F_IMM20_HI, SH_F_IMM20_LO, SH_F_IMM20
, SH_F_OP, SH_F_EXT, SH_F_RSVD, SH_F_LEFT
, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT, SH_F_TRA
, SH_F_TRB, SH_F_LIKELY, SH_F_6_3, SH_F_23_2
, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16, SH_F_UIMM6
, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32, SH_F_DISP10
, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2, SH_F_DISP16
, SH_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) SH_F_MAX)
/* Hardware attribute indices. */
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA
, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;
/* Number of non-boolean elements in cgen_hw_attr. */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
/* cgen_hw attribute accessor macros. */
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
/* Enum declaration for sh hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
, HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
, HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
, HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
, HW_H_FMTX, HW_H_DR, HW_H_FSD, HW_H_FMOV
, HW_H_TR, HW_H_ENDIAN, HW_H_ISM, HW_H_FRC
, HW_H_DRC, HW_H_XF, HW_H_XD, HW_H_FVC
, HW_H_GBR, HW_H_VBR, HW_H_PR, HW_H_MACL
, HW_H_MACH, HW_H_TBIT, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
/* Operand attribute indices. */
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
, CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand_attr. */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
/* cgen_operand attribute accessor macros. */
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
/* Enum declaration for sh operand types. */
typedef enum cgen_operand_type {
SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
, SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
, SH_OPERAND_FR0, SH_OPERAND_FMOVN, SH_OPERAND_FMOVM, SH_OPERAND_FVN
, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM, SH_OPERAND_IMM4
, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM20, SH_OPERAND_IMM4X2
, SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
, SH_OPERAND_DISP12, SH_OPERAND_IMM12X4, SH_OPERAND_IMM12X8, SH_OPERAND_RM64
, SH_OPERAND_RN64, SH_OPERAND_GBR, SH_OPERAND_VBR, SH_OPERAND_PR
, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT, SH_OPERAND_MBIT
, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT, SH_OPERAND_SZBIT
, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH, SH_OPERAND_FSDM
, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG, SH_OPERAND_FRH
, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF, SH_OPERAND_FVG
, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG, SH_OPERAND_DRG
, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH, SH_OPERAND_CRJ
, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB, SH_OPERAND_DISP6
, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2, SH_OPERAND_DISP10X4
, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6, SH_OPERAND_IMM10
, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16, SH_OPERAND_LIKELY
, SH_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 79
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
/* Insn attribute indices. */
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
, CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
, CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
/* cgen_insn attribute accessor macros. */
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_INSN_SH4_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_SH4A_GROUP_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SH4A_GROUP-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
#define CGEN_ATTR_CGEN_INSN_ILLSLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ILLSLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_FP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_FP_INSN)) != 0)
#define CGEN_ATTR_CGEN_INSN_32_BIT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_32_BIT_INSN)) != 0)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
extern const struct cgen_ifld sh_cgen_ifld_table[];
/* Attributes. */
extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];
/* Hardware decls. */
extern CGEN_KEYWORD sh_cgen_opval_h_gr;
extern CGEN_KEYWORD sh_cgen_opval_h_grc;
extern CGEN_KEYWORD sh_cgen_opval_h_cr;
extern CGEN_KEYWORD sh_cgen_opval_h_fr;
extern CGEN_KEYWORD sh_cgen_opval_h_fp;
extern CGEN_KEYWORD sh_cgen_opval_h_fv;
extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
extern CGEN_KEYWORD sh_cgen_opval_h_dr;
extern CGEN_KEYWORD sh_cgen_opval_h_fsd;
extern CGEN_KEYWORD sh_cgen_opval_h_fmov;
extern CGEN_KEYWORD sh_cgen_opval_h_tr;
extern CGEN_KEYWORD sh_cgen_opval_frc_names;
extern CGEN_KEYWORD sh_cgen_opval_drc_names;
extern CGEN_KEYWORD sh_cgen_opval_xf_names;
extern CGEN_KEYWORD sh_cgen_opval_frc_names;
extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
extern const CGEN_HW_ENTRY sh_cgen_hw_table[];
#endif /* SH_CPU_H */

214
sim/sh64/sh-opc.h
View File

@ -1,214 +0,0 @@
/* Instruction opcode header for sh.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SH_OPC_H
#define SH_OPC_H
/* Enum declaration for sh instruction types. */
typedef enum cgen_insn_type {
SH_INSN_INVALID, SH_INSN_ADD_COMPACT, SH_INSN_ADDI_COMPACT, SH_INSN_ADDC_COMPACT
, SH_INSN_ADDV_COMPACT, SH_INSN_AND_COMPACT, SH_INSN_ANDI_COMPACT, SH_INSN_ANDB_COMPACT
, SH_INSN_BF_COMPACT, SH_INSN_BFS_COMPACT, SH_INSN_BRA_COMPACT, SH_INSN_BRAF_COMPACT
, SH_INSN_BRK_COMPACT, SH_INSN_BSR_COMPACT, SH_INSN_BSRF_COMPACT, SH_INSN_BT_COMPACT
, SH_INSN_BTS_COMPACT, SH_INSN_CLRMAC_COMPACT, SH_INSN_CLRS_COMPACT, SH_INSN_CLRT_COMPACT
, SH_INSN_CMPEQ_COMPACT, SH_INSN_CMPEQI_COMPACT, SH_INSN_CMPGE_COMPACT, SH_INSN_CMPGT_COMPACT
, SH_INSN_CMPHI_COMPACT, SH_INSN_CMPHS_COMPACT, SH_INSN_CMPPL_COMPACT, SH_INSN_CMPPZ_COMPACT
, SH_INSN_CMPSTR_COMPACT, SH_INSN_DIV0S_COMPACT, SH_INSN_DIV0U_COMPACT, SH_INSN_DIV1_COMPACT
, SH_INSN_DIVU_COMPACT, SH_INSN_MULR_COMPACT, SH_INSN_DMULSL_COMPACT, SH_INSN_DMULUL_COMPACT
, SH_INSN_DT_COMPACT, SH_INSN_EXTSB_COMPACT, SH_INSN_EXTSW_COMPACT, SH_INSN_EXTUB_COMPACT
, SH_INSN_EXTUW_COMPACT, SH_INSN_FABS_COMPACT, SH_INSN_FADD_COMPACT, SH_INSN_FCMPEQ_COMPACT
, SH_INSN_FCMPGT_COMPACT, SH_INSN_FCNVDS_COMPACT, SH_INSN_FCNVSD_COMPACT, SH_INSN_FDIV_COMPACT
, SH_INSN_FIPR_COMPACT, SH_INSN_FLDS_COMPACT, SH_INSN_FLDI0_COMPACT, SH_INSN_FLDI1_COMPACT
, SH_INSN_FLOAT_COMPACT, SH_INSN_FMAC_COMPACT, SH_INSN_FMOV1_COMPACT, SH_INSN_FMOV2_COMPACT
, SH_INSN_FMOV3_COMPACT, SH_INSN_FMOV4_COMPACT, SH_INSN_FMOV5_COMPACT, SH_INSN_FMOV6_COMPACT
, SH_INSN_FMOV7_COMPACT, SH_INSN_FMOV8_COMPACT, SH_INSN_FMOV9_COMPACT, SH_INSN_FMUL_COMPACT
, SH_INSN_FNEG_COMPACT, SH_INSN_FRCHG_COMPACT, SH_INSN_FSCHG_COMPACT, SH_INSN_FSQRT_COMPACT
, SH_INSN_FSTS_COMPACT, SH_INSN_FSUB_COMPACT, SH_INSN_FTRC_COMPACT, SH_INSN_FTRV_COMPACT
, SH_INSN_JMP_COMPACT, SH_INSN_JSR_COMPACT, SH_INSN_LDC_GBR_COMPACT, SH_INSN_LDC_VBR_COMPACT
, SH_INSN_LDC_SR_COMPACT, SH_INSN_LDCL_GBR_COMPACT, SH_INSN_LDCL_VBR_COMPACT, SH_INSN_LDS_FPSCR_COMPACT
, SH_INSN_LDSL_FPSCR_COMPACT, SH_INSN_LDS_FPUL_COMPACT, SH_INSN_LDSL_FPUL_COMPACT, SH_INSN_LDS_MACH_COMPACT
, SH_INSN_LDSL_MACH_COMPACT, SH_INSN_LDS_MACL_COMPACT, SH_INSN_LDSL_MACL_COMPACT, SH_INSN_LDS_PR_COMPACT
, SH_INSN_LDSL_PR_COMPACT, SH_INSN_MACL_COMPACT, SH_INSN_MACW_COMPACT, SH_INSN_MOV_COMPACT
, SH_INSN_MOVI_COMPACT, SH_INSN_MOVI20_COMPACT, SH_INSN_MOVB1_COMPACT, SH_INSN_MOVB2_COMPACT
, SH_INSN_MOVB3_COMPACT, SH_INSN_MOVB4_COMPACT, SH_INSN_MOVB5_COMPACT, SH_INSN_MOVB6_COMPACT
, SH_INSN_MOVB7_COMPACT, SH_INSN_MOVB8_COMPACT, SH_INSN_MOVB9_COMPACT, SH_INSN_MOVB10_COMPACT
, SH_INSN_MOVL1_COMPACT, SH_INSN_MOVL2_COMPACT, SH_INSN_MOVL3_COMPACT, SH_INSN_MOVL4_COMPACT
, SH_INSN_MOVL5_COMPACT, SH_INSN_MOVL6_COMPACT, SH_INSN_MOVL7_COMPACT, SH_INSN_MOVL8_COMPACT
, SH_INSN_MOVL9_COMPACT, SH_INSN_MOVL10_COMPACT, SH_INSN_MOVL11_COMPACT, SH_INSN_MOVL12_COMPACT
, SH_INSN_MOVL13_COMPACT, SH_INSN_MOVW1_COMPACT, SH_INSN_MOVW2_COMPACT, SH_INSN_MOVW3_COMPACT
, SH_INSN_MOVW4_COMPACT, SH_INSN_MOVW5_COMPACT, SH_INSN_MOVW6_COMPACT, SH_INSN_MOVW7_COMPACT
, SH_INSN_MOVW8_COMPACT, SH_INSN_MOVW9_COMPACT, SH_INSN_MOVW10_COMPACT, SH_INSN_MOVW11_COMPACT
, SH_INSN_MOVA_COMPACT, SH_INSN_MOVCAL_COMPACT, SH_INSN_MOVCOL_COMPACT, SH_INSN_MOVT_COMPACT
, SH_INSN_MOVUAL_COMPACT, SH_INSN_MOVUAL2_COMPACT, SH_INSN_MULL_COMPACT, SH_INSN_MULSW_COMPACT
, SH_INSN_MULUW_COMPACT, SH_INSN_NEG_COMPACT, SH_INSN_NEGC_COMPACT, SH_INSN_NOP_COMPACT
, SH_INSN_NOT_COMPACT, SH_INSN_OCBI_COMPACT, SH_INSN_OCBP_COMPACT, SH_INSN_OCBWB_COMPACT
, SH_INSN_OR_COMPACT, SH_INSN_ORI_COMPACT, SH_INSN_ORB_COMPACT, SH_INSN_PREF_COMPACT
, SH_INSN_ROTCL_COMPACT, SH_INSN_ROTCR_COMPACT, SH_INSN_ROTL_COMPACT, SH_INSN_ROTR_COMPACT
, SH_INSN_RTS_COMPACT, SH_INSN_SETS_COMPACT, SH_INSN_SETT_COMPACT, SH_INSN_SHAD_COMPACT
, SH_INSN_SHAL_COMPACT, SH_INSN_SHAR_COMPACT, SH_INSN_SHLD_COMPACT, SH_INSN_SHLL_COMPACT
, SH_INSN_SHLL2_COMPACT, SH_INSN_SHLL8_COMPACT, SH_INSN_SHLL16_COMPACT, SH_INSN_SHLR_COMPACT
, SH_INSN_SHLR2_COMPACT, SH_INSN_SHLR8_COMPACT, SH_INSN_SHLR16_COMPACT, SH_INSN_STC_GBR_COMPACT
, SH_INSN_STC_VBR_COMPACT, SH_INSN_STCL_GBR_COMPACT, SH_INSN_STCL_VBR_COMPACT, SH_INSN_STS_FPSCR_COMPACT
, SH_INSN_STSL_FPSCR_COMPACT, SH_INSN_STS_FPUL_COMPACT, SH_INSN_STSL_FPUL_COMPACT, SH_INSN_STS_MACH_COMPACT
, SH_INSN_STSL_MACH_COMPACT, SH_INSN_STS_MACL_COMPACT, SH_INSN_STSL_MACL_COMPACT, SH_INSN_STS_PR_COMPACT
, SH_INSN_STSL_PR_COMPACT, SH_INSN_SUB_COMPACT, SH_INSN_SUBC_COMPACT, SH_INSN_SUBV_COMPACT
, SH_INSN_SWAPB_COMPACT, SH_INSN_SWAPW_COMPACT, SH_INSN_TASB_COMPACT, SH_INSN_TRAPA_COMPACT
, SH_INSN_TST_COMPACT, SH_INSN_TSTI_COMPACT, SH_INSN_TSTB_COMPACT, SH_INSN_XOR_COMPACT
, SH_INSN_XORI_COMPACT, SH_INSN_XORB_COMPACT, SH_INSN_XTRCT_COMPACT, SH_INSN_ADD
, SH_INSN_ADDL, SH_INSN_ADDI, SH_INSN_ADDIL, SH_INSN_ADDZL
, SH_INSN_ALLOCO, SH_INSN_AND, SH_INSN_ANDC, SH_INSN_ANDI
, SH_INSN_BEQ, SH_INSN_BEQI, SH_INSN_BGE, SH_INSN_BGEU
, SH_INSN_BGT, SH_INSN_BGTU, SH_INSN_BLINK, SH_INSN_BNE
, SH_INSN_BNEI, SH_INSN_BRK, SH_INSN_BYTEREV, SH_INSN_CMPEQ
, SH_INSN_CMPGT, SH_INSN_CMPGTU, SH_INSN_CMVEQ, SH_INSN_CMVNE
, SH_INSN_FABSD, SH_INSN_FABSS, SH_INSN_FADDD, SH_INSN_FADDS
, SH_INSN_FCMPEQD, SH_INSN_FCMPEQS, SH_INSN_FCMPGED, SH_INSN_FCMPGES
, SH_INSN_FCMPGTD, SH_INSN_FCMPGTS, SH_INSN_FCMPUND, SH_INSN_FCMPUNS
, SH_INSN_FCNVDS, SH_INSN_FCNVSD, SH_INSN_FDIVD, SH_INSN_FDIVS
, SH_INSN_FGETSCR, SH_INSN_FIPRS, SH_INSN_FLDD, SH_INSN_FLDP
, SH_INSN_FLDS, SH_INSN_FLDXD, SH_INSN_FLDXP, SH_INSN_FLDXS
, SH_INSN_FLOATLD, SH_INSN_FLOATLS, SH_INSN_FLOATQD, SH_INSN_FLOATQS
, SH_INSN_FMACS, SH_INSN_FMOVD, SH_INSN_FMOVDQ, SH_INSN_FMOVLS
, SH_INSN_FMOVQD, SH_INSN_FMOVS, SH_INSN_FMOVSL, SH_INSN_FMULD
, SH_INSN_FMULS, SH_INSN_FNEGD, SH_INSN_FNEGS, SH_INSN_FPUTSCR
, SH_INSN_FSQRTD, SH_INSN_FSQRTS, SH_INSN_FSTD, SH_INSN_FSTP
, SH_INSN_FSTS, SH_INSN_FSTXD, SH_INSN_FSTXP, SH_INSN_FSTXS
, SH_INSN_FSUBD, SH_INSN_FSUBS, SH_INSN_FTRCDL, SH_INSN_FTRCSL
, SH_INSN_FTRCDQ, SH_INSN_FTRCSQ, SH_INSN_FTRVS, SH_INSN_GETCFG
, SH_INSN_GETCON, SH_INSN_GETTR, SH_INSN_ICBI, SH_INSN_LDB
, SH_INSN_LDL, SH_INSN_LDQ, SH_INSN_LDUB, SH_INSN_LDUW
, SH_INSN_LDW, SH_INSN_LDHIL, SH_INSN_LDHIQ, SH_INSN_LDLOL
, SH_INSN_LDLOQ, SH_INSN_LDXB, SH_INSN_LDXL, SH_INSN_LDXQ
, SH_INSN_LDXUB, SH_INSN_LDXUW, SH_INSN_LDXW, SH_INSN_MABSL
, SH_INSN_MABSW, SH_INSN_MADDL, SH_INSN_MADDW, SH_INSN_MADDSL
, SH_INSN_MADDSUB, SH_INSN_MADDSW, SH_INSN_MCMPEQB, SH_INSN_MCMPEQL
, SH_INSN_MCMPEQW, SH_INSN_MCMPGTL, SH_INSN_MCMPGTUB, SH_INSN_MCMPGTW
, SH_INSN_MCMV, SH_INSN_MCNVSLW, SH_INSN_MCNVSWB, SH_INSN_MCNVSWUB
, SH_INSN_MEXTR1, SH_INSN_MEXTR2, SH_INSN_MEXTR3, SH_INSN_MEXTR4
, SH_INSN_MEXTR5, SH_INSN_MEXTR6, SH_INSN_MEXTR7, SH_INSN_MMACFXWL
, SH_INSN_MMACNFX_WL, SH_INSN_MMULL, SH_INSN_MMULW, SH_INSN_MMULFXL
, SH_INSN_MMULFXW, SH_INSN_MMULFXRPW, SH_INSN_MMULHIWL, SH_INSN_MMULLOWL
, SH_INSN_MMULSUMWQ, SH_INSN_MOVI, SH_INSN_MPERMW, SH_INSN_MSADUBQ
, SH_INSN_MSHALDSL, SH_INSN_MSHALDSW, SH_INSN_MSHARDL, SH_INSN_MSHARDW
, SH_INSN_MSHARDSQ, SH_INSN_MSHFHIB, SH_INSN_MSHFHIL, SH_INSN_MSHFHIW
, SH_INSN_MSHFLOB, SH_INSN_MSHFLOL, SH_INSN_MSHFLOW, SH_INSN_MSHLLDL
, SH_INSN_MSHLLDW, SH_INSN_MSHLRDL, SH_INSN_MSHLRDW, SH_INSN_MSUBL
, SH_INSN_MSUBW, SH_INSN_MSUBSL, SH_INSN_MSUBSUB, SH_INSN_MSUBSW
, SH_INSN_MULSL, SH_INSN_MULUL, SH_INSN_NOP, SH_INSN_NSB
, SH_INSN_OCBI, SH_INSN_OCBP, SH_INSN_OCBWB, SH_INSN_OR
, SH_INSN_ORI, SH_INSN_PREFI, SH_INSN_PTA, SH_INSN_PTABS
, SH_INSN_PTB, SH_INSN_PTREL, SH_INSN_PUTCFG, SH_INSN_PUTCON
, SH_INSN_RTE, SH_INSN_SHARD, SH_INSN_SHARDL, SH_INSN_SHARI
, SH_INSN_SHARIL, SH_INSN_SHLLD, SH_INSN_SHLLDL, SH_INSN_SHLLI
, SH_INSN_SHLLIL, SH_INSN_SHLRD, SH_INSN_SHLRDL, SH_INSN_SHLRI
, SH_INSN_SHLRIL, SH_INSN_SHORI, SH_INSN_SLEEP, SH_INSN_STB
, SH_INSN_STL, SH_INSN_STQ, SH_INSN_STW, SH_INSN_STHIL
, SH_INSN_STHIQ, SH_INSN_STLOL, SH_INSN_STLOQ, SH_INSN_STXB
, SH_INSN_STXL, SH_INSN_STXQ, SH_INSN_STXW, SH_INSN_SUB
, SH_INSN_SUBL, SH_INSN_SWAPQ, SH_INSN_SYNCI, SH_INSN_SYNCO
, SH_INSN_TRAPA, SH_INSN_XOR, SH_INSN_XORI
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID SH_INSN_INVALID
/* Total number of insns in table. */
#define MAX_INSNS ((int) SH_INSN_XORI + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
{
int length;
long f_nil;
long f_anyof;
long f_op4;
long f_op8;
long f_op16;
long f_sub4;
long f_sub8;
long f_sub10;
long f_rn;
long f_rm;
long f_7_1;
long f_11_1;
long f_16_4;
long f_disp8;
long f_disp12;
long f_imm8;
long f_imm4;
long f_imm4x2;
long f_imm4x4;
long f_imm8x2;
long f_imm8x4;
long f_imm12x4;
long f_imm12x8;
long f_dn;
long f_dm;
long f_vn;
long f_vm;
long f_xn;
long f_xm;
long f_imm20_hi;
long f_imm20_lo;
long f_imm20;
long f_op;
long f_ext;
long f_rsvd;
long f_left;
long f_right;
long f_dest;
long f_left_right;
long f_tra;
long f_trb;
long f_likely;
long f_6_3;
long f_23_2;
long f_imm6;
long f_imm10;
long f_imm16;
long f_uimm6;
long f_uimm16;
long f_disp6;
long f_disp6x32;
long f_disp10;
long f_disp10x8;
long f_disp10x4;
long f_disp10x2;
long f_disp16;
};
#define CGEN_INIT_PARSE(od) \
{\
}
#define CGEN_INIT_INSERT(od) \
{\
}
#define CGEN_INIT_EXTRACT(od) \
{\
}
#define CGEN_INIT_PRINT(od) \
{\
}
#endif /* SH_OPC_H */

84
sim/sh64/sh64-sim.h
View File

@ -1,84 +0,0 @@
/* collection of junk waiting time to sort out
Copyright (C) 2000-2021 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef SH64_SIM_H
#define SH64_SIM_H
enum {
ISM_COMPACT, ISM_MEDIA
};
extern IDESC * sh64_idesc_media;
extern IDESC * sh64_idesc_compact;
/* Function prototypes from sh64.c. */
BI sh64_endian (SIM_CPU *);
VOID sh64_break (SIM_CPU *, PCADDR);
SI sh64_movua (SIM_CPU *, PCADDR, SI);
VOID sh64_trapa (SIM_CPU *, DI, PCADDR);
VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR);
SF sh64_fldi0 (SIM_CPU *);
SF sh64_fldi1 (SIM_CPU *);
DF sh64_fcnvsd (SIM_CPU *, SF);
SF sh64_fcnvds (SIM_CPU *, DF);
DF sh64_fabsd (SIM_CPU *, DF);
SF sh64_fabss (SIM_CPU *, SF);
DF sh64_faddd (SIM_CPU *, DF, DF);
SF sh64_fadds (SIM_CPU *, SF, SF);
DF sh64_fdivd (SIM_CPU *, DF, DF);
SF sh64_fdivs (SIM_CPU *, SF, SF);
DF sh64_floatld (SIM_CPU *, SF);
SF sh64_floatls (SIM_CPU *, SF);
DF sh64_floatqd (SIM_CPU *, DF);
SF sh64_floatqs (SIM_CPU *, DF);
SF sh64_fmacs(SIM_CPU *, SF, SF, SF);
DF sh64_fmuld (SIM_CPU *, DF, DF);
SF sh64_fmuls (SIM_CPU *, SF, SF);
DF sh64_fnegd (SIM_CPU *, DF);
SF sh64_fnegs (SIM_CPU *, SF);
DF sh64_fsqrtd (SIM_CPU *, DF);
SF sh64_fsqrts (SIM_CPU *, SF);
DF sh64_fsubd (SIM_CPU *, DF, DF);
SF sh64_fsubs (SIM_CPU *, SF, SF);
SF sh64_ftrcdl (SIM_CPU *, DF);
DF sh64_ftrcdq (SIM_CPU *, DF);
SF sh64_ftrcsl (SIM_CPU *, SF);
DF sh64_ftrcsq (SIM_CPU *, SF);
VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned);
VOID sh64_fipr (SIM_CPU *cpu, unsigned m, unsigned n);
SF sh64_fiprs (SIM_CPU *cpu, unsigned g, unsigned h);
VOID sh64_fldp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
VOID sh64_fstp (SIM_CPU *cpu, PCADDR pc, DI rm, DI rn, unsigned f);
VOID sh64_ftrv (SIM_CPU *cpu, UINT ignored);
VOID sh64_pref (SIM_CPU *cpu, SI addr);
BI sh64_fcmpeqs (SIM_CPU *, SF, SF);
BI sh64_fcmpeqd (SIM_CPU *, DF, DF);
BI sh64_fcmpges (SIM_CPU *, SF, SF);
BI sh64_fcmpged (SIM_CPU *, DF, DF);
BI sh64_fcmpgts (SIM_CPU *, SF, SF);
BI sh64_fcmpgtd (SIM_CPU *, DF, DF);
BI sh64_fcmpund (SIM_CPU *, DF, DF);
BI sh64_fcmpuns (SIM_CPU *, SF, SF);
DI sh64_nsb (SIM_CPU *, DI);
#endif /* SH64_SIM_H */

1138
sim/sh64/sh64.c
View File

File diff suppressed because it is too large Load Diff

204
sim/sh64/sim-if.c
View File

@ -1,204 +0,0 @@
/* Main simulator entry points specific to the SH5.
Copyright (C) 2000-2021 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "config.h"
#include "libiberty.h"
#include "bfd.h"
#include "sim-main.h"
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#include "sim-options.h"
#include "dis-asm.h"
static void free_state (SIM_DESC);
/* Since we don't build the cgen-opcode table, we use a wrapper around
the existing disassembler from libopcodes. */
static CGEN_DISASSEMBLER sh64_disassemble_insn;
/* Cover function of sim_state_free to free the cpu buffers as well. */
static void
free_state (SIM_DESC sd)
{
if (STATE_MODULES (sd) != NULL)
sim_module_uninstall (sd);
sim_cpu_free_all (sd);
sim_state_free (sd);
}
/* Create an instance of the simulator. */
SIM_DESC
sim_open (kind, callback, abfd, argv)
SIM_OPEN_KIND kind;
host_callback *callback;
struct bfd *abfd;
char * const *argv;
{
char c;
int i;
SIM_DESC sd = sim_state_alloc (kind, callback);
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
#if 0 /* FIXME: pc is in mach-specific struct */
/* FIXME: watchpoints code shouldn't need this */
{
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
STATE_WATCHPOINTS (sd)->pc = &(PC);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
}
#endif
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* The parser will print an error message for us, so we silently return. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Allocate core managed memory if none specified by user.
Use address 4 here in case the user wanted address 0 unmapped. */
if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE);
/* Add a small memory region way up in the address space to handle
writes to invalidate an instruction cache line. This is used for
trampolines. Since we don't simulate the cache, this memory just
avoids bus errors. 64K ought to do. */
sim_do_command (sd," memory region 0xf0000000,0x10000");
/* check for/establish the reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Open a copy of the cpu descriptor table. */
{
CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
CGEN_ENDIAN_BIG);
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
CPU_CPU_DESC (cpu) = cd;
CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn;
}
}
/* Clear idesc table pointers for good measure. */
sh64_idesc_media = sh64_idesc_compact = NULL;
/* Initialize various cgen things not done by common framework.
Must be done after sh_cgen_cpu_open. */
cgen_init (sd);
return sd;
}
SIM_RC
sim_create_inferior (sd, abfd, argv, envp)
SIM_DESC sd;
struct bfd *abfd;
char * const *argv;
char * const *envp;
{
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
SIM_ADDR addr;
if (abfd != NULL)
addr = bfd_get_start_address (abfd);
else
addr = 0;
sim_pc_set (current_cpu, addr);
/* Standalone mode (i.e. `run`) will take care of the argv for us in
sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
with `gdb`), we need to handle it because the user can change the
argv on the fly via gdb's 'run'. */
if (STATE_PROG_ARGV (sd) != argv)
{
freeargv (STATE_PROG_ARGV (sd));
STATE_PROG_ARGV (sd) = dupargv (argv);
}
return SIM_RC_OK;
}
/* Disassemble an instruction. */
static void
sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
const ARGBUF *abuf, IADDR pc, char *buf)
{
struct disassemble_info disasm_info;
SFILE sfile;
SIM_DESC sd = CPU_STATE (cpu);
sfile.buffer = sfile.current = buf;
INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
(fprintf_ftype) sim_disasm_sprintf);
disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd));
disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd));
disasm_info.endian =
(bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
: bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_UNKNOWN);
disasm_info.read_memory_func = sim_disasm_read_memory;
disasm_info.memory_error_func = sim_disasm_perror_memory;
disasm_info.application_data = (PTR) cpu;
if (sh64_h_ism_get (cpu) == ISM_MEDIA)
print_insn_sh64x_media (pc, &disasm_info);
else
print_insn_sh (pc, &disasm_info);
}

72
sim/sh64/sim-main.h
View File

@ -1,72 +0,0 @@
/* Main header for the Hitachi SH64 architecture. */
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
/* sim-basics.h includes config.h but cgen-types.h must be included before
sim-basics.h and cgen-types.h needs config.h. */
#include "config.h"
/* This is a global setting. Different cpu families can't mix-n-match -scache
and -pbb. However some cpu families may use -simple while others use
one of -scache/-pbb. ???? */
#define WITH_SCACHE_PBB 1
#include "symcat.h"
#include "sim-basics.h"
#include "cgen-types.h"
#include "sh-desc.h"
#include "sh-opc.h"
#include "arch.h"
/* These must be defined before sim-base.h. */
typedef UDI sim_cia;
#define CIA_ADDR(cia) (cia)
#include "sim-base.h"
#include "cgen-sim.h"
#include "sh64-sim.h"
/* The _sim_cpu struct. */
struct _sim_cpu {
/* sim/common cpu base. */
sim_cpu_base base;
/* Static parts of cgen. */
CGEN_CPU cgen_cpu;
/* CPU specific parts go here.
Note that in files that don't need to access these pieces WANT_CPU_FOO
won't be defined and thus these parts won't appear. This is ok in the
sense that things work. It is a source of bugs though.
One has to of course be careful to not take the size of this
struct and no structure members accessed in non-cpu specific files can
go after here. Oh for a better language. */
#if defined (WANT_CPU_SH64)
SH64_CPU_DATA cpu_data;
#endif
};
/* The sim_state struct. */
struct sim_state {
sim_cpu *cpu[MAX_NR_PROCESSORS];
CGEN_STATE cgen_state;
sim_state_base base;
};
/* Misc. */
/* Catch address exceptions. */
extern SIM_CORE_SIGNAL_FN sh64_core_signal;
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
sh64_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
(TRANSFER), (ERROR))
/* Default memory size. */
#define SH64_DEFAULT_MEM_SIZE 0x800000 /* 8M */
#endif /* SIM_MAIN_H */

5
sim/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2021-01-09 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
* sim/sh64/: Delete.
2021-01-05 Mike Frysinger <vapier@gentoo.org>
* sim/fr30/: Delete.

3
sim/testsuite/configure vendored
View File

@ -1940,9 +1940,6 @@ case "${target}" in
rx-*-*)
sim_arch=rx
;;
sh64*-*-*)
sim_arch=sh64
;;
sh*-*-*)
sim_arch=sh
;;

21
sim/testsuite/sim/sh64/ChangeLog
View File

@ -1,21 +0,0 @@
2001-01-06 Ben Elliston <bje@redhat.com>
* misc/fr-dr.s: New test.
2001-01-03 Ben Elliston <bje@redhat.com>
* interwork.exp: Match .s files only.
2000-12-06 Ben Elliston <bje@redhat.com>
* interwork.exp: New test case.
2000-11-16 Ben Elliston <bje@redhat.com>
* allinsn.exp: Rename from this ..
* compact.exp: .. to this.
* media.exp: New test case.
2000-11-13 Ben Elliston <bje@redhat.com>
* allinsn.exp: New test case.

19
sim/testsuite/sim/sh64/compact.exp
View File

@ -1,19 +0,0 @@
# SHcompact testsuite.
if [istarget sh64-*-*] {
# load support procs (none yet)
# load_lib cgen.exp
# all machines
set all_machs "sh5"
# The .cgs suffix is for "cgen .s".
foreach src [lsort [glob -nocomplain $srcdir/$subdir/compact/*.cgs]] {
# If we're only testing specific files and this isn't one of them,
# skip it.
if ![runtest_file_p $runtests $src] {
continue
}
run_sim_test $src $all_machs
}
}

26
sim/testsuite/sim/sh64/compact/ChangeLog
View File

@ -1,26 +0,0 @@
2002-01-09 Ben Elliston <bje@redhat.com>
* macl.cgs: For good measure, clear the S bit at startup.
2001-01-11 Ben Elliston <bje@redhat.com>
* fmov.cgs (f13b): Compare R0 with R1, not R2, when testing that
the source register was correctly post-incremented.
2000-12-01 Ben Elliston <bje@redhat.com>
* *.cgs (ld): Link tests with -m shelf32.
2000-11-24 Ben Elliston <bje@redhat.com>
* fmov.cgs: New test case.
* ftrv.cgs: Populate the matrix with meaningful values.
2000-11-22 Ben Elliston <bje@redhat.com>
* *.cgs (as): Assemble tests with -isa=shcompact.
2000-11-16 Ben Elliston <bje@redhat.com>
* *.cgs: New test cases.

55
sim/testsuite/sim/sh64/compact/add.cgs
View File

@ -1,55 +0,0 @@
# sh testcase for add $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
init:
# Initialise some registers with values which help us to verify
# that the correct source registers are used by the ADD instruction.
mov #0, r0
mov #1, r1
mov #2, r2
mov #3, r3
mov #5, r5
mov #15, r15
add:
# 0 + 0 = 0.
add r0, r0
assert r0, #0
# 0 + 1 = 1.
add r0, r1
assert r1, #1
# 1 + 2 = 3.
add r1, r2
assert r2, #3
# 3 + 5 = 8.
add r3, r5
assert r5, #8
# 8 + 8 = 16.
add r5, r5
assert r5, #16
# 15 + 1 = 16.
add r15, r1
assert r1, #16
neg:
mov #1, r0
neg r0, r0
mov #2, r1
add r0, r1
assert r1, #1
okay:
pass
wrong:
fail

90
sim/testsuite/sim/sh64/compact/addc.cgs
View File

@ -1,90 +0,0 @@
# sh testcase for addc $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
# Initialise some registers with values which help us to verify
# that the correct source registers are used by the ADDC instruction.
.macro init
mov #0, r0
mov #1, r1
mov #2, r2
mov #3, r3
mov #5, r5
mov #15, r15
.endm
start
init
add:
clrt
addc r0, r0
assert r0, #0
clrt
addc r0, r1
assert r1, #1
clrt
addc r1, r2
assert r2, #3
clrt
addc r3, r5
assert r5, #8
clrt
addc r5, r5
assert r5, #16
clrt
addc r15, r1
assert r1, #16
init
addt:
sett
addc r0, r0
assert r0, #1
sett
addc r0, r1
assert r1, #3
sett
addc r1, r2
assert r2, #6
sett
addc r3, r5
assert r5, #9
sett
addc r5, r5
assert r5, #19
sett
addc r15, r1
assert r1, #19
bra next
nop
wrong:
fail
next:
init
large:
clrt
mov #1, r0
neg r0, r0
mov #2, r1
addc r0, r1
assert r1, #1
init
larget:
sett
mov #1, r0
neg r0, r0
mov #2, r1
addc r0, r1
assert r1, #2
okay:
pass

46
sim/testsuite/sim/sh64/compact/addi.cgs
View File

@ -1,46 +0,0 @@
# sh testcase for add #$imm8, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
init:
# Initialise some registers with values which help us to verify
# that the correct source registers are used by the ADD instruction.
mov #0, r0
mov #1, r1
mov #2, r2
mov #3, r3
mov #5, r5
mov #15, r15
addi:
# 0 + 0 = 0.
add #0, r0
assert r0, #0
# 0 + 1 = 1.
add #0, r1
assert r1, #1
# 2 + 2 = 4.
add #2, r2
assert r2, #4
# 120 + 5 = 125.
add #120, r5
assert r5, #125
large:
mov #1, r0
neg r0, r0
add #2, r0
assert r0, #1
okay:
pass
wrong:
fail

48
sim/testsuite/sim/sh64/compact/addv.cgs
View File

@ -1,48 +0,0 @@
# sh testcase for addv $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zero:
mov #0, r0
mov #0, r1
addv r0, r1
# Assert !T and #0.
bt wrong
assert r1, #0
one:
mov #0, r0
mov #1, r1
addv r0, r1
# Assert !T and #1.
bt wrong
assert r1, #1
large:
# Produce MAXINT in R0.
mov #0, r0
not r0, r0
shlr r0
# Put #3 into R1.
mov #3, r1
# Add them and overflow.
addv r0, r1
# Assert T and overflowed value.
bf wrong
mov #1, r7
rotr r7
add #2, r7
cmp/eq r1, r7
bf wrong
okay:
pass
wrong:
fail

33
sim/testsuite/sim/sh64/compact/and.cgs
View File

@ -1,33 +0,0 @@
# sh testcase for and $rm64, $rn64 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global and
and:
mov #1, r1
mov #7, r2
rotr r2
rotr r2
and r1, r2
# R1 & R2 = 1.
assert r2, #1
another:
mov #192, r1
mov #0, r2
and r1, r2
# R1 & R2 = 0.
assert r2, #0
okay:
pass
wrong:
fail

24
sim/testsuite/sim/sh64/compact/andb.cgs
View File

@ -1,24 +0,0 @@
# sh testcase for and.b #$imm8, @(r0, gbr) -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global orb
init:
# Init GBR and R0.
mov #30, r0
ldc r0, gbr
mov #40, r0
orb:
and.b #255, @(r0, gbr)
and.b #170, @(r0, gbr)
and.b #255, @(r0, gbr)
and.b #0, @(r0, gbr)
okay:
pass

43
sim/testsuite/sim/sh64/compact/andi.cgs
View File

@ -1,43 +0,0 @@
# sh testcase for and #$imm8, r0 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global andi
andi:
mov #0, r0
or #255, r0
and #0, r0
assert r0, #0
large:
mov #0, r0
or #255, r0
shll8 r0
or #255, r0
shll8 r0
or #255, r0
shll8 r0
or #255, r0
mask:
and #255, r0
mov r0, r1
mov #0, r0
or #255, r0
cmp/eq r0, r1
bf wrong
mask0:
and #0, r0
assert r0, #0
okay:
pass
wrong:
fail

24
sim/testsuite/sim/sh64/compact/bf.cgs
View File

@ -1,24 +0,0 @@
# sh testcase for bf $disp8 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global taken
taken:
clrt
bf ntaken
fail
.global ntaken
ntaken:
sett
bf bad
pass
bad:
fail
fail
fail
fail

28
sim/testsuite/sim/sh64/compact/bfs.cgs
View File

@ -1,28 +0,0 @@
# sh testcase for bf/s $disp8 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global taken
taken:
clrt
bf/s ntaken
slot1:
nop
fail
.global ntaken
ntaken:
sett
bf/s bad
slot2:
nop
pass
bad:
fail
fail
fail
fail

23
sim/testsuite/sim/sh64/compact/bra.cgs
View File

@ -1,23 +0,0 @@
# sh testcase for bra $disp12 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global bra
bra:
bra okay
slot:
nop
bad:
fail
fail
fail
.global okay
okay:
pass
fail

24
sim/testsuite/sim/sh64/compact/braf.cgs
View File

@ -1,24 +0,0 @@
# sh testcase for braf $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global braf
braf:
mov #4, r0
braf r0
slot:
nop
bad:
fail
fail
okay:
pass
alsobad:
fail
fail
fail

18
sim/testsuite/sim/sh64/compact/brk.cgs
View File

@ -1,18 +0,0 @@
# sh testcase for brk -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global brk
brk:
# If we hit the breakpoint, the sim will stop.
pass
# FIXME: breakpoint instruction.
# The SH4 assembler doesn't know about "brk".
.word 0x003b
bad:
fail

21
sim/testsuite/sim/sh64/compact/bsr.cgs
View File

@ -1,21 +0,0 @@
# sh testcase for bsr $disp12 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global bsr
bsr:
bsr okay
slot:
nop
bad:
fail
fail
okay:
pass
alsobad:
fail

22
sim/testsuite/sim/sh64/compact/bsrf.cgs
View File

@ -1,22 +0,0 @@
# sh testcase for bsrf $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
bsrf:
mov #4, r0
bsrf r0
slot:
nop
bad:
fail
fail
okay:
pass
alsobad:
fail
fail

24
sim/testsuite/sim/sh64/compact/bt.cgs
View File

@ -1,24 +0,0 @@
# sh testcase for bt $disp8
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global taken
taken:
sett
bt ntaken
fail
.global ntaken
ntaken:
clrt
bt bad
pass
bad:
fail
fail
fail
fail

28
sim/testsuite/sim/sh64/compact/bts.cgs
View File

@ -1,28 +0,0 @@
# sh testcase for bt/s $disp8 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global taken
taken:
sett
bt/s ntaken
slot1:
nop
fail
.global ntaken
ntaken:
clrt
bt/s bad
slot2:
nop
pass
bad:
fail
fail
fail
fail

13
sim/testsuite/sim/sh64/compact/clrmac.cgs
View File

@ -1,13 +0,0 @@
# sh testcase for clrmac -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global clrmac
clrmac:
clrmac
pass

14
sim/testsuite/sim/sh64/compact/clrs.cgs
View File

@ -1,14 +0,0 @@
# sh testcase for clrs -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global clrs
clrs:
clrs
# Somehow ensure that S is set.
pass

16
sim/testsuite/sim/sh64/compact/clrt.cgs
View File

@ -1,16 +0,0 @@
# sh testcase for clrt -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global clrt
clrt:
clrt
bt wrong
pass
wrong:
fail

52
sim/testsuite/sim/sh64/compact/cmpeq.cgs
View File

@ -1,52 +0,0 @@
# sh testcase for cmp/eq $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zeroes:
mov #0, r1
mov #0, r2
cmp/eq r1, r2
bf wrong
zero1:
mov #0, r1
mov #1, r2
cmp/eq r1, r2
bt wrong
zero2:
mov #0, r2
mov #1, r1
cmp/eq r2, r1
bt wrong
equal:
mov #192, r1
mov #192, r2
cmp/eq r1, r2
bf wrong
noteq:
mov #192, r1
mov #193, r2
cmp/eq r1, r2
bt wrong
large:
mov #1, r1
rotr r1
mov #1, r2
rotr r2
cmp/eq r1, r2
bf wrong
okay:
pass
wrong:
fail

39
sim/testsuite/sim/sh64/compact/cmpeqi.cgs
View File

@ -1,39 +0,0 @@
# sh testcase for cmp/eq #$imm8, r0 -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zeroes:
mov #0, r0
cmp/eq #0, r0
bf wrong
zero1:
mov #0, r0
cmp/eq #1, r0
bt wrong
zero2:
mov #1, r0
cmp/eq #0, r0
bt wrong
equal:
mov #192, r0
cmp/eq #192, r0
bf wrong
sign:
mov #255, r0
cmp/eq #255, r0
bf wrong
okay:
pass
wrong:
fail

69
sim/testsuite/sim/sh64/compact/cmpge.cgs
View File

@ -1,69 +0,0 @@
# sh testcase for cmp/ge $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zero:
mov #0, r0
mov #0, r1
cmp/ge r0, r1
bf wrong
onezero:
mov #1, r0
mov #0, r1
cmp/ge r0, r1
bt wrong
zeroone:
mov #0, r0
mov #1, r1
cmp/ge r0, r1
bf wrong
equal:
mov #192, r0
mov #192, r1
cmp/ge r0, r1
bf wrong
eqlarge:
mov #1, r0
rotr r0
add #85, r0
mov #1, r1
rotr r1
add #85, r1
cmp/ge r0, r1
bf wrong
large2:
mov #1, r0
rotr r0
add #85, r0
mov #1, r1
rotr r1
add #84, r1
cmp/ge r0, r1
bt wrong
large3:
mov #1, r0
rotr r0
add #84, r0
mov #1, r1
rotr r1
add #85, r1
cmp/ge r0, r1
bf wrong
okay:
pass
wrong:
fail

69
sim/testsuite/sim/sh64/compact/cmpgt.cgs
View File

@ -1,69 +0,0 @@
# sh testcase for cmp/gt $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zero:
mov #0, r0
mov #0, r1
cmp/gt r0, r1
bt wrong
onezero:
mov #1, r0
mov #0, r1
cmp/gt r0, r1
bt wrong
zeroone:
mov #0, r0
mov #1, r1
cmp/gt r0, r1
bf wrong
equal:
mov #192, r0
mov #192, r1
cmp/gt r0, r1
bt wrong
eqlarge:
mov #1, r0
rotr r0
add #85, r0
mov #1, r1
rotr r1
add #85, r1
cmp/gt r0, r1
bt wrong
large2:
mov #1, r0
rotr r0
add #85, r0
mov #1, r1
rotr r1
add #84, r1
cmp/gt r0, r1
bt wrong
large3:
mov #1, r0
rotr r0
add #84, r0
mov #1, r1
rotr r1
add #85, r1
cmp/gt r0, r1
bf wrong
okay:
pass
wrong:
fail

68
sim/testsuite/sim/sh64/compact/cmphi.cgs
View File

@ -1,68 +0,0 @@
# sh testcase for cmp/hi $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zero:
mov #0, r0
mov #0, r0
cmp/hi r0, r1
bt wrong
equal:
mov #1, r0
rotr r0
add #3, r0
mov #1, r1
rotr r1
add #3, r1
cmp/hi r0, r1
bt wrong
gt:
mov #10, r0
mov #12, r1
cmp/hi r0, r1
bf wrong
lt:
mov #12, r0
mov #10, r1
cmp/hi r0, r1
bt wrong
gtneg:
mov #1, r0
rotr r0
add #1, r0
mov #1, r1
rotr r1
add #3, r1
cmp/hi r0, r1
bf wrong
ltneg:
mov #1, r0
rotr r0
add #3, r0
mov #1, r1
rotr r1
add #1, r1
cmp/hi r0, r1
bt wrong
okay:
pass
wrong:
fail

59
sim/testsuite/sim/sh64/compact/cmphs.cgs
View File

@ -1,59 +0,0 @@
# sh testcase for cmp/hs $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zero:
mov #0, r0
mov #0, r0
cmp/hs r0, r1
equal:
mov #1, r0
rotr r0
add #3, r0
mov #1, r1
rotr r1
add #3, r1
cmp/hs r0, r1
gt:
mov #10, r0
mov #12, r1
cmp/hs r0, r1
lt:
mov #12, r0
mov #10, r1
cmp/hs r0, r1
gtneg:
mov #1, r0
rotr r0
add #1, r0
mov #1, r1
rotr r1
add #3, r1
cmp/hs r0, r1
ltneg:
mov #1, r0
rotr r0
add #3, r0
mov #1, r1
rotr r1
add #1, r1
cmp/hs r0, r1
okay:
pass

37
sim/testsuite/sim/sh64/compact/cmppl.cgs
View File

@ -1,37 +0,0 @@
# sh testcase for cmp/pl $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zero:
mov #0, r0
cmp/pl r0
bt wrong
plus:
mov #10, r0
cmp/pl r0
bf wrong
minus:
mov #10, r0
neg r0, r0
cmp/pl r0
bt wrong
large:
mov #10, r0
shll8 r0
add #123, r0
cmp/pl r0
bf wrong
okay:
pass
wrong:
fail

37
sim/testsuite/sim/sh64/compact/cmppz.cgs
View File

@ -1,37 +0,0 @@
# sh testcase for cmp/pz $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
zero:
mov #0, r0
cmp/pz r0
bf wrong
plus:
mov #10, r0
cmp/pz r0
bf wrong
minus:
mov #10, r0
neg r0, r0
cmp/pz r0
bt wrong
large:
mov #10, r0
shll8 r0
add #123, r0
cmp/pz r0
bf wrong
okay:
pass
wrong:
fail

148
sim/testsuite/sim/sh64/compact/cmpstr.cgs
View File

@ -1,148 +0,0 @@
# sh testcase for cmp/str $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
.macro rot8
rotr r0
rotr r0
rotr r0
rotr r0
rotr r0
rotr r0
rotr r0
rotr r0
.endm
start
# Use multiple "wrong" labels because this program is quite long. It's
# likely that some instructions will be too far away from the branch
# target to use PC-relative branches.
match0:
# No bytes matching.
mov #1, r0
neg r0, r0
xor #170, r0
rot8
xor #170, r0
rot8
xor #170, r0
rot8
xor #170, r0
rot8
mov r0, r1
mov #1, r0
neg r0, r0
xor #85, r0
rot8
xor #85, r0
rot8
xor #85, r0
rot8
xor #85, r0
rot8
cmp/str r0, r1
bt wrong0
bra match1
nop
wrong0:
fail
match1:
# One byte matching.
mov #1, r0
neg r0, r0
xor #170, r0
rot8
xor #170, r0
rot8
xor #170, r0
rot8
mov r0, r1
mov #1, r0
neg r0, r0
xor #85, r0
rot8
xor #85, r0
rot8
xor #85, r0
rot8
cmp/str r0, r1
bf wrong1
bra match2
nop
wrong1:
fail
match2:
# Two bytes matching.
mov #1, r0
neg r0, r0
xor #170, r0
rot8
xor #170, r0
rot8
mov r0, r1
mov #1, r0
neg r0, r0
xor #85, r0
rot8
xor #85, r0
rot8
cmp/str r0, r1
bf wrong2
bra match3
nop
wrong2:
fail
byte0:
match3:
# One byte matching.
# This is also the test for byte 0.
mov #85, r0
mov #85, r1
cmp/str r0, r1
bf wrong3
byte1:
# Match in byte position 1.
mov #85, r0
shll8 r0
mov #85, r1
shll8 r1
cmp/str r0, r1
bf wrong3
byte2:
# Match in byte position 2.
mov #85, r0
shll16 r0
mov #85, r1
shll16 r1
cmp/str r0, r1
bf wrong3
byte3:
# Match in byte position 3.
mov #85, r0
shll16 r0
shll8 r0
mov #85, r1
shll16 r1
shll8 r1
cmp/str r0, r1
bf wrong3
okay:
pass
wrong3:
fail

52
sim/testsuite/sim/sh64/compact/div0s.cgs
View File

@ -1,52 +0,0 @@
# sh testcase for div0s $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
init:
mov #0, r0
mov #3, r1
mov #4, r2
neg r1, r3
neg r2, r4
perm1:
div0s r0, r0
bt wrong
div0s r0, r1
bt wrong
div0s r1, r0
bt wrong
perm2:
div0s r0, r4
bf wrong
div0s r4, r0
bf wrong
perm3:
div0s r1, r2
bt wrong
div0s r2, r1
bt wrong
perm4:
div0s r3, r4
bt wrong
div0s r4, r3
bt wrong
perm5:
div0s r1, r1
bt wrong
div0s r3, r3
bt wrong
okay:
pass
wrong:
fail

21
sim/testsuite/sim/sh64/compact/div0u.cgs
View File

@ -1,21 +0,0 @@
# sh testcase for div0u -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global div0u
div0u:
div0u
# Can't easily test Q and M (other than visually inspecting
# the simulator's trace output).
bt wrong
okay:
pass
wrong:
fail

52
sim/testsuite/sim/sh64/compact/div1.cgs
View File

@ -1,52 +0,0 @@
# sh testcase for div1 $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
mov #10, r0
mov #2, r1
div0s r0,r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
div1 r0, r1
pass

115
sim/testsuite/sim/sh64/compact/dmulsl.cgs
View File

@ -1,115 +0,0 @@
# sh testcase for dmuls.l $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
mov #0, r0
mov #0, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
assert r3, #0
assert r4, #0
test2:
mov #0, r0
mov #5, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
assert r3, #0
assert r4, #0
test3:
mov #5, r0
mov #0, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
assert r3, #0
assert r4, #0
test4:
mov #1, r0
mov #5, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
assert r3, #0
assert r4, #5
test5:
mov #5, r0
mov #1, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
assert r3, #0
assert r4, #5
bra test6
nop
wrong:
fail
test6:
mov #2, r0
mov #2, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
assert r3, #0
assert r4, #4
test7:
mov #1, r0
neg r0, r0
mov #2, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
mov #0, r8
not r8, r9
not r8, r10
shll r10
cmp/eq r3, r9
bf wrong
cmp/eq r4, r10
bf wrong
test8:
mov #1, r0
neg r0, r0
mov #1, r1
neg r1, r1
dmuls.l r0, r1
# check result
sts mach, r3
sts macl, r4
assert r3, #0
assert r4, #1
test9:
mov #1, r0
neg r0, r0
shlr r0
mov #1, r1
neg r1, r1
shlr r1
dmuls.l r0, r1
okay:
pass

53
sim/testsuite/sim/sh64/compact/dmulul.cgs
View File

@ -1,53 +0,0 @@
# sh testcase for dmulu.l $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
mov #0, r0
mov #0, r1
dmulu.l r0, r1
mov #0, r0
mov #5, r1
dmulu.l r0, r1
mov #5, r0
mov #0, r1
dmulu.l r0, r1
mov #1, r0
mov #5, r1
dmulu.l r0, r1
mov #5, r0
mov #1, r1
dmulu.l r0, r1
mov #2, r0
mov #2, r1
dmulu.l r0, r1
mov #1, r0
neg r0, r0
mov #2, r1
dmulu.l r0, r1
mov #1, r0
neg r0, r0
mov #1, r1
neg r1, r1
dmulu.l r0, r1
mov #1, r0
neg r0, r0
shlr r0
mov #1, r1
neg r1, r1
shlr r1
dmulu.l r0, r1
pass

42
sim/testsuite/sim/sh64/compact/dt.cgs
View File

@ -1,42 +0,0 @@
# sh testcase for dt $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global dt
dt:
mov #3, r0
dt r0
bt wrong
assert r0, #2
mov #1, r0
dt r0
bf wrong
assert r0, #0
mov #0, r0
dt r0
bt wrong
mov #0, r7
not r7, r7
cmp/eq r7, r0
bf wrong
mov #1, r0
neg r0, r0
dt r0
mov #1, r7
not r7, r7
cmp/eq r7, r0
bf wrong
okay:
pass
wrong:
fail

29
sim/testsuite/sim/sh64/compact/extsb.cgs
View File

@ -1,29 +0,0 @@
# sh testcase for exts.b $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global extsb
extsb:
mov #42, r1
exts.b r1, r2
assert r2, #42
signed:
mov #0, r0
or #255, r0
exts.b r0, r1
mov #0, r7
not r7, r7
cmp/eq r1, r7
bf wrong
okay:
pass
wrong:
fail

32
sim/testsuite/sim/sh64/compact/extsw.cgs
View File

@ -1,32 +0,0 @@
# sh testcase for exts.w $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global extsw
extsw:
mov #42, r1
exts.w r1, r2
assert r2, #42
another:
mov #0, r0
or #255, r0
shll8 r0
exts.w r0, r1
mov #-1, r7
shll8 r7
cmp/eq r1, r7
bf wrong
okay:
pass
wrong:
fail

31
sim/testsuite/sim/sh64/compact/extub.cgs
View File

@ -1,31 +0,0 @@
# sh testcase for extu.b $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global extub
extub:
mov #42, r1
extu.b r1, r2
assert r2, #42
another:
mov #0, r0
or #255, r0
extu.b r0, r1
mov #0, r0
or #255, r0
cmp/eq r0, r1
bf wrong
okay:
pass
wrong:
fail

31
sim/testsuite/sim/sh64/compact/extuw.cgs
View File

@ -1,31 +0,0 @@
# sh testcase for extu.w $rm, $rn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
.global extuw
extuw:
mov #42, r1
extu.w r1, r2
assert r2, #42
another:
mov #0, r0
or #255, r0
shll8 r0
extu.w r0, r1
mov #0, r0
or #255, r0
shll8 r0
cmp/eq r0, r1
bf wrong
okay:
pass
wrong:
fail

88
sim/testsuite/sim/sh64/compact/fabs.cgs
View File

@ -1,88 +0,0 @@
# sh testcase for fabs -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
_clrpr
# fabs(0.0) = 0.0.
fldi0 fr0
fabs fr0
fldi0 fr1
fcmp/eq fr0, fr1
bf wrong
# fabs(1.0) = 1.0.
fldi1 fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf wrong
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf wrong
bra double
nop
wrong:
fail
double:
# double precision tests.
# fabs(0.0) = 0.0.
fldi0 fr0
_s2d fr0, dr0
_setpr
fabs dr0
_clrpr
# check.
fldi0 fr2
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bf wrong
_clrpr
one:
# fabs(1.0) = 1.0.
fldi1 fr0
_s2d fr0, dr0
_setpr
fabs dr0
_clrpr
# check.
fldi1 fr2
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bf wrong2
_clrpr
minusone:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
_s2d fr0, dr0
_setpr
fabs dr0
_clrpr
# check.
fldi1 fr2
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bf wrong2
_clrpr
okay:
pass
wrong2:
fail

31
sim/testsuite/sim/sh64/compact/fadd.cgs
View File

@ -1,31 +0,0 @@
# sh testcase for fadd
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
_clrpr
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fldi0 fr0
fldi1 fr1
fadd fr0, fr1
fldi1 fr0
fldi0 fr1
fadd fr0, fr1
_setpr
double:
fldi1 fr0
fldi1 fr1
_s2d fr0, dr4
_s2d fr1, dr6
fadd dr4, dr6
pass

88
sim/testsuite/sim/sh64/compact/fcmpeq.cgs
View File

@ -1,88 +0,0 @@
# sh testcase for fcmpeq -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
# 1.0 == 1.0.
fldi1 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf wrong
# 0.0 != 1.0.
fldi0 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt wrong
# 1.0 != 0.0.
fldi1 fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt wrong
# 2.0 != 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt wrong
bra double
# delay slot
nop
wrong:
fail
double:
# 1.0 == 1.0
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bf wrong
_clrpr
# 0.0 != 1.0
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bt wrong
_clrpr
# 1.0 != 0.0
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bt wrong2
_clrpr
# 2.0 != 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bt wrong2
_clrpr
okay:
pass
wrong2:
fail

95
sim/testsuite/sim/sh64/compact/fcmpgt.cgs
View File

@ -1,95 +0,0 @@
# sh testcase for fcmpgt -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bt wrong
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf wrong
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr1
fcmp/gt fr0, fr1
bt wrong
# 2.0 > 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/gt fr0, fr1
bt wrong
bra double
nop
wrong:
fail
double:
# double precision tests.
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/gt dr0, dr2
bt wrong2
_clrpr
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/gt dr0, dr2
bf wrong2
_clrpr
bra next
nop
wrong2:
fail
next:
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/gt dr0, dr2
bt wrong2
_clrpr
# 2.0 > 1.0.
fldi1 fr0
fadd fr0, fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fcmp/gt dr0, dr2
bt wrong2
_clrpr
okay:
pass
wrong3:
fail

13
sim/testsuite/sim/sh64/compact/fcnvds.cgs
View File

@ -1,13 +0,0 @@
# sh testcase for fcnvds -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
_setpr
fcnvds dr0, fpul
_clrpr
okay:
pass

27
sim/testsuite/sim/sh64/compact/fcnvsd.cgs
View File

@ -1,27 +0,0 @@
# sh testcase for fcnvsd -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
fldi1 fr0
flds fr0, fpul
_setpr
fcnvsd fpul, dr2
_clrpr
# Convert back.
_setpr
fcnvds dr2, fpul
_clrpr
fsts fpul, fr1
fcmp/eq fr0, fr1
bf wrong
okay:
pass
wrong:
fail

83
sim/testsuite/sim/sh64/compact/fdiv.cgs
View File

@ -1,83 +0,0 @@
# sh testcase for fdiv -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
_clrpr
# 1.0 / 0.0 should be INF
# (and not crash the sim).
fldi0 fr0
fldi1 fr1
fdiv fr0, fr1
# 0.0 / 1.0 == 0.0.
fldi0 fr0
fldi1 fr1
fdiv fr1, fr0
fldi0 fr2
fcmp/eq fr0, fr2
bf wrong
# 2.0 / 1.0 == 2.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr1, fr2
# Load 2.0 into fr3.
fldi1 fr3
fadd fr3, fr3
fcmp/eq fr2, fr3
bf wrong
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr2, fr1
# fr1 should contain 0.5.
fadd fr1, fr1
# Load 1.0 into fr3.
fldi1 fr3
# Compare fr1 with fr3.
fcmp/eq fr1, fr3
bf wrong
bra double
nop
wrong:
fail
double:
# double test
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
_s2d fr1, dr6
fldi1 fr2
fadd fr2, fr2
_s2d fr2, dr8
_setpr
fdiv dr8, dr6
# dr0 should contain 0.5.
# double it, expect 1.0.
fadd dr6, dr6
_clrpr
foo:
# Load 1.0 into dr4.
fldi1 fr1
_s2d fr1, dr10
# Compare dr0 with dr10.
_setpr
fcmp/eq dr6, dr10
bf wrong2
_clrpr
okay:
pass
wrong2:
fail

44
sim/testsuite/sim/sh64/compact/fipr.cgs
View File

@ -1,44 +0,0 @@
# sh testcase for fipr $fvm, $fvn
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
initv1:
fldi1 fr0
# Load 2 into fr2.
fldi1 fr1
fadd fr1, fr1
# Load 4 into fr2.
fldi1 fr2
fadd fr2, fr2
fadd fr2, fr2
fldi0 fr3
initv2:
fldi1 fr8
fldi0 fr9
fldi1 fr10
fldi0 fr11
fipr fv0, fv8
# Result will be in fr11.
fldi1 fr0
fldi1 fr1
# Two.
fadd fr1, fr0
# Four.
fadd fr0, fr0
# Five.
fadd fr1, fr0
fcmp/eq fr0, fr11
bf wrong
okay:
pass
wrong:
fail

17
sim/testsuite/sim/sh64/compact/fldi0.cgs
View File

@ -1,17 +0,0 @@
# sh testcase for fldi0 $frn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
fldi0 fr0
fldi0 fr2
fldi0 fr4
fldi0 fr6
fldi0 fr8
fldi0 fr10
fldi0 fr12
fldi0 fr14
pass

17
sim/testsuite/sim/sh64/compact/fldi1.cgs
View File

@ -1,17 +0,0 @@
# sh testcase for fldi1 $frn -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
fldi1 fr1
fldi1 fr3
fldi1 fr5
fldi1 fr7
fldi1 fr9
fldi1 fr11
fldi1 fr13
fldi1 fr15
pass

26
sim/testsuite/sim/sh64/compact/flds.cgs
View File

@ -1,26 +0,0 @@
# sh testcase for flds -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
fldi0 fr0
flds fr0, fpul
fsts fpul, fr1
fcmp/eq fr0, fr1
bf wrong
fldi1 fr0
flds fr0, fpul
fsts fpul, fr1
fcmp/eq fr0, fr1
bf wrong
okay:
pass
wrong:
fail

80
sim/testsuite/sim/sh64/compact/float.cgs
View File

@ -1,80 +0,0 @@
# sh testcase for float -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
pos:
mov #3, r0
lds r0, fpul
float fpul, fr7
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fcmp/eq fr1, fr7
bf wrong
neg:
mov #3, r0
neg r0, r0
lds r0, fpul
float fpul, fr7
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fneg fr1
fcmp/eq fr1, fr7
bf wrong
bra double
nop
wrong:
fail
double:
mov #3, r0
lds r0, fpul
_setpr
float fpul, dr8
_clrpr
# check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
_s2d fr1, dr2
fcmp/eq dr2, dr8
bf wrong
dneg:
mov #3, r0
neg r0, r0
lds r0, fpul
_setpr
float fpul, dr8
_clrpr
# check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fneg fr1
_s2d fr1, dr2
fcmp/eq dr2, dr8
bf wrong
okay:
pass
wrong2:
fail

78
sim/testsuite/sim/sh64/compact/fmac.cgs
View File

@ -1,78 +0,0 @@
# sh testcase for fmac -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
# 0.0 * x + y = y.
fldi0 fr0
fldi1 fr1
fldi1 fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fcmp/eq fr0, fr2
bf wrong
# x * y + 0.0 = x * y.
fldi1 fr0
fldi1 fr1
fldi0 fr2
# double it.
fadd fr1, fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fadd fr0, fr0
fcmp/eq fr0, fr2
bf wrong
# x * 0.0 + y = y.
fldi1 fr0
fldi0 fr1
fldi1 fr2
fadd fr2, fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
# double fr0.
fadd fr0, fr0
fcmp/eq fr0, fr2
bf wrong
# x * 0.0 + 0.0 = 0.0
fldi1 fr0
fadd fr0, fr0
fldi0 fr1
fldi0 fr2
fmac fr0, fr1, fr2
# check result.
fldi0 fr0
fcmp/eq fr0, fr2
bf wrong
# 0.0 * x + 0.0 = 0.0.
fldi0 fr0
fldi1 fr1
# double it.
fadd fr1, fr1
fldi0 fr2
fmac fr0, fr1, fr2
# check result.
fldi0 fr0
fcmp/eq fr0, fr2
bf wrong
okay:
pass
wrong:
fail

273
sim/testsuite/sim/sh64/compact/fmov.cgs
View File

@ -1,273 +0,0 @@
# sh testcase for all fmov instructions
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
.macro init
fldi0 fr0
fldi1 fr2
.endm
# Set the SZ (SiZe) bit in the fpscr.
.macro _setsz
sts fpscr, r7
mov #16, r8
shll16 r8
or r8, r7
lds r7, fpscr
.endm
# Clear the SZ bit.
.macro _clrsz
sts fpscr, r7
mov #16, r8
shll16 r8
not r8, r8
and r8, r7
lds r7, fpscr
.endm
start
fmov1: # Test fr -> fr.
init
_clrpr
_clrsz
fmov fr0, fr10
# Ensure fr0 and fr10 are now equal.
fcmp/eq fr0, fr10
bt fmov2
fail
fmov2: # Test dr -> dr.
init
_setpr
_setsz
fmov dr0, dr2
# Ensure dr0 and dr2 are now equal.
fcmp/eq dr0, dr2
bt fmov3
fail
fmov3: # Test dr -> xd and xd -> dr.
init
_setsz
fmov dr0, xd0
# Ensure dr0 and xd0 are now equal.
fmov xd0, dr2
fcmp/eq dr0, dr2
bt fmov4
fail
fmov4: # Test xd -> xd.
init
_setsz
_setpr
fmov dr0, xd0
fmov xd0, xd2
fmov xd2, dr2
# Ensure dr0 and dr2 are now equal.
fcmp/eq dr0, dr2
bt fmov5
fail
fmov5: # Test fr -> @rn and @rn -> fr.
init
_clrsz
_clrpr
mov #40, r0
shll8 r0
fmov fr0, @r0
fmov @r0, fr1
fcmp/eq fr0, fr1
bt fmov6
fail
fmov6: # Test dr -> @rn and @rn -> dr.
init
_setsz
_setpr
mov #40, r0
shll8 r0
fmov dr0, @r0
fmov @r0, dr2
fcmp/eq dr0, dr2
bt fmov7
fail
fmov7: # Test xd -> @rn and @rn -> xd.
init
_setsz
_setpr
mov #40, r0
shll8 r0
fmov dr0, xd0
fmov xd0, @r0
fmov @r0, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt fmov8
fail
fmov8: # Test fr -> @-rn.
init
_clrsz
_clrpr
mov #40, r0
shll8 r0
# Preserve.
mov r0, r1
fmov fr0, @-r0
fmov @r0, fr2
fcmp/eq fr0, fr2
bt f8b
fail
f8b: # check pre-dec.
add #4, r0
cmp/eq r0, r1
bt fmov9
fail
fmov9: # Test dr -> @-rn.
init
_setsz
_setpr
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, @-r0
fmov @r0, dr2
fcmp/eq dr0, dr2
bt f9b
fail
f9b: # check pre-dec.
add #8, r0
cmp/eq r0, r1
bt fmov10
fail
fmov10: # Test xd -> @-rn.
init
_setsz
_setpr
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, xd0
fmov xd0, @-r0
fmov @r0, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt f10b
fail
f10b: # check pre-dec.
add #8, r0
cmp/eq r0, r1
bt fmov11
fail
fmov11: # Test @rn+ -> fr.
init
_clrsz
_clrpr
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov fr0, @r0
fmov @r0+, fr2
fcmp/eq fr0, fr2
bt f11b
fail
f11b: # check post-inc.
add #4, r1
cmp/eq r0, r1
bt fmov12
fail
fmov12: # Test @rn+ -> dr.
init
_setsz
_setpr
mov #40, r0
shll8 r0
# preserve r0.
mov r0, r1
fmov dr0, @r0
fmov @r0+, dr2
fcmp/eq dr0, dr2
bt f12b
fail
f12b: # check post-inc.
add #8, r1
cmp/eq r0, r1
bt fmov13
fail
fmov13: # Test @rn -> xd.
init
_setsz
_setpr
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, xd0
fmov xd0, @r0
fmov @r0+, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt f13b
fail
f13b:
add #8, r1
cmp/eq r0, r1
bt fmov14
fail
fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.
init
_clrsz
_clrpr
mov #40, r0
shll8 r0
mov #0, r1
fmov fr0, @(r0, r1)
fmov @(r0, r1), fr1
fcmp/eq fr0, fr1
bt fmov15
fail
fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.
init
_setsz
_setpr
mov #40, r0
shll8 r0
mov #0, r1
fmov dr0, @(r0, r1)
fmov @(r0, r1), dr2
fcmp/eq dr0, dr2
bt fmov16
fail
fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.
init
_setsz
_setpr
mov #40, r0
shll8 r0
mov #0, r1
fmov dr0, xd0
fmov xd0, @(r0, r1)
fmov @(r0, r1), xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt okay
fail
okay:
pass

121
sim/testsuite/sim/sh64/compact/fmul.cgs
View File

@ -1,121 +0,0 @@
# sh testcase for fmul -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fldi0 fr7
fldi1 fr8
.endm
start
# 0.0 * 0.0 = 0.0.
init
fmul fr0, fr0
fcmp/eq fr7, fr0
bf wrong
# 0.0 * 1.0 = 0.0.
init
fmul fr1, fr0
fcmp/eq fr7, fr0
bf wrong
# 1.0 * 0.0 = 0.0.
init
fmul fr0, fr1
fcmp/eq fr7, fr1
bf wrong
# 1.0 * 1.0 = 1.0.
init
fmul fr1, fr1
fcmp/eq fr8, fr1
bf wrong
# 2.0 * 1.0 = 2.0.
init
fmul fr2, fr1
fcmp/eq fr2, fr1
bf wrong
bra double
nop
wrong:
fail
.macro dinit
fldi0 fr0
fldi1 fr2
fldi1 fr4
fadd fr4, fr4
fldi0 fr8
fldi1 fr10
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
_s2d fr8, dr8
_s2d fr10, dr10
.endm
double:
# 0.0 * 0.0 = 0.0.
dinit
_setpr
fmul dr0, dr0
fcmp/eq dr8, dr0
bf wrong
_clrpr
# 0.0 * 1.0 = 0.0.
dinit
_setpr
fmul dr2, dr0
fcmp/eq dr8, dr0
bf wrong2
_clrpr
# 1.0 * 0.0 = 0.0.
dinit
_setpr
fmul dr0, dr2
fcmp/eq dr8, dr2
bf wrong2
_clrpr
bra next
nop
wrong2:
fail
next:
# 1.0 * 1.0 = 1.0.
dinit
_setpr
fmul dr2, dr2
fcmp/eq dr10, dr2
bf wrong3
_clrpr
# 2.0 * 1.0 = 2.0.
dinit
_setpr
fmul dr4, dr2
fcmp/eq dr4, dr2
bf wrong3
_clrpr
okay:
pass
wrong3:
fail

83
sim/testsuite/sim/sh64/compact/fneg.cgs
View File

@ -1,83 +0,0 @@
# sh testcase for fneg -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr1
fneg fr0
fcmp/eq fr0, fr1
bf wrong
# neg(1.0) = fsub(0,1)
fldi1 fr0
fneg fr0
fldi0 fr1
fldi1 fr2
fsub fr2, fr1
fcmp/eq fr0, fr1
bf wrong
# neg(neg(1.0)) = 1.0.
fldi1 fr0
fldi1 fr1
fneg fr0
fneg fr0
fcmp/eq fr0, fr1
bf wrong
bra double
nop
wrong:
fail
double:
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
_setpr
fneg dr0
fcmp/eq dr0, dr2
bf wrong2
_clrpr
# neg(1.0) = fsub(0,1)
fldi1 fr0
_s2d fr0, dr0
_setpr
fneg dr0
_clrpr
fldi0 fr2
fldi1 fr3
fsub fr3, fr2
_s2d fr2, dr2
_setpr
fcmp/eq fr0, fr2
bf wrong2
_clrpr
# neg(neg(1.0)) = 1.0.
fldi1 fr0
_s2d fr0, dr0
fldi1 fr2
_s2d fr2, dr2
_setpr
fneg dr0
fneg dr2
fcmp/eq dr0, dr2
bf wrong2
_clrpr
okay:
pass
wrong2:
fail

13
sim/testsuite/sim/sh64/compact/frchg.cgs
View File

@ -1,13 +0,0 @@
# sh testcase for frchg
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
frchg
frchg
frchg
frchg
pass

13
sim/testsuite/sim/sh64/compact/fschg.cgs
View File

@ -1,13 +0,0 @@
# sh testcase for fschg
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
fschg
fschg
fschg
fschg
pass

93
sim/testsuite/sim/sh64/compact/fsqrt.cgs
View File

@ -1,93 +0,0 @@
# sh testcase for fsqrt -*- Asm -*-
# mach: all
# as: -isa=shcompact
# ld: -m shelf32
.include "compact/testutils.inc"
start
# sqrt(0.0) = 0.0.
fldi0 fr0
fsqrt fr0
fldi0 fr1
fcmp/eq fr0, fr1
bf wrong
# sqrt(1.0) = 1.0.
fldi1 fr0
fsqrt fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf wrong
# sqrt(4.0) = 2.0
fldi1 fr0
# Double it.
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
fsqrt fr0
fldi1 fr1
# Double it.
fadd fr1, fr1
fcmp/eq fr0, fr1
bf wrong
bra double
nop
wrong:
fail
double:
# sqrt(0.0) = 0.0.
fldi0 fr0
_s2d fr0, dr0
_setpr
fsqrt dr0
_clrpr
fldi0 fr2
_s2d fr2, dr2
_setpr
fcmp/eq dr0, dr2
bf wrong2
_clrpr
# sqrt(1.0) = 1.0.
fldi1 fr0
_s2d fr0, dr0
_setpr
fsqrt dr0
_clrpr
fldi1 fr2
_s2d fr2, dr2
_setpr
fcmp/eq fr0, fr2
bf wrong2
_clrpr
# sqrt(4.0) = 2.0.
fldi1 fr0
# Double it.
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
_s2d fr0, dr0
_setpr
fsqrt dr0
_clrpr
fldi1 fr2
# Double it.
fadd fr2, fr2
_s2d fr2, dr2
_setpr
fcmp/eq fr0, fr2
bf wrong2
_clrpr
okay:
pass
wrong2:
fail

Some files were not shown because too many files have changed in this diff Show More