RISC-V: Add support for the Zvkned ISA extension
Zvkned is part of the vector crypto extensions. This extension adds the following instructions: - vaesef.[vv,vs] - vaesem.[vv,vs] - vaesdf.[vv,vs] - vaesdm.[vv,vs] - vaeskf1.vi - vaeskf2.vi - vaesz.vs bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkned. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkned.d: New test. * testsuite/gas/riscv/zvkned.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VAESDF_VS): New. (MASK_VAESDF_VS): New. (MATCH_VAESDF_VV): New. (MASK_VAESDF_VV): New. (MATCH_VAESDM_VS): New. (MASK_VAESDM_VS): New. (MATCH_VAESDM_VV): New. (MASK_VAESDM_VV): New. (MATCH_VAESEF_VS): New. (MASK_VAESEF_VS): New. (MATCH_VAESEF_VV): New. (MASK_VAESEF_VV): New. (MATCH_VAESEM_VS): New. (MASK_VAESEM_VS): New. (MATCH_VAESEM_VV): New. (MASK_VAESEM_VV): New. (MATCH_VAESKF1_VI): New. (MASK_VAESKF1_VI): New. (MATCH_VAESKF2_VI): New. (MASK_VAESKF2_VI): New. (MATCH_VAESZ_VS): New. (MASK_VAESZ_VS): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkned. opcodes/ChangeLog: * riscv-opc.c: Add Zvkned instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This commit is contained in:
Christoph Müllner
Jeff Law
parent
9d469329d2
commit
fce8fef965
@ -1265,6 +1265,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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@ -2436,6 +2437,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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return riscv_subset_supports (rps, "zvbc");
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case INSN_CLASS_ZVKG:
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return riscv_subset_supports (rps, "zvkg");
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case INSN_CLASS_ZVKNED:
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return riscv_subset_supports (rps, "zvkned");
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case INSN_CLASS_SVINVAL:
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return riscv_subset_supports (rps, "svinval");
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case INSN_CLASS_H:
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@ -2630,6 +2633,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return _("zvbc");
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case INSN_CLASS_ZVKG:
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return _("zvkg");
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case INSN_CLASS_ZVKNED:
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return _("zvkned");
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case INSN_CLASS_SVINVAL:
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return "svinval";
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case INSN_CLASS_H:
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21
gas/testsuite/gas/riscv/zvkned.d
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21
gas/testsuite/gas/riscv/zvkned.d
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@ -0,0 +1,21 @@
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#as: -march=rv64gc_zvkned
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#objdump: -dr
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <.text>:
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[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+a680a277[ ]+vaesdf.vs[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+a2802277[ ]+vaesdm.vv[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+a6802277[ ]+vaesdm.vs[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+a281a277[ ]+vaesef.vv[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+a681a277[ ]+vaesef.vs[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+a2812277[ ]+vaesem.vv[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+a6812277[ ]+vaesem.vs[ ]+v4,v8
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[ ]+[0-9a-f]+:[ ]+8a812277[ ]+vaeskf1.vi[ ]+v4,v8,2
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[ ]+[0-9a-f]+:[ ]+8a872277[ ]+vaeskf1.vi[ ]+v4,v8,14
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[ ]+[0-9a-f]+:[ ]+aa812277[ ]+vaeskf2.vi[ ]+v4,v8,2
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[ ]+[0-9a-f]+:[ ]+aa872277[ ]+vaeskf2.vi[ ]+v4,v8,14
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[ ]+[0-9a-f]+:[ ]+a683a277[ ]+vaesz.vs[ ]+v4,v8
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13
gas/testsuite/gas/riscv/zvkned.s
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13
gas/testsuite/gas/riscv/zvkned.s
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@ -0,0 +1,13 @@
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vaesdf.vv v4, v8
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vaesdf.vs v4, v8
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vaesdm.vv v4, v8
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vaesdm.vs v4, v8
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vaesef.vv v4, v8
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vaesef.vs v4, v8
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vaesem.vv v4, v8
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vaesem.vs v4, v8
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vaeskf1.vi v4, v8, 2
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vaeskf1.vi v4, v8, 14
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vaeskf2.vi v4, v8, 2
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vaeskf2.vi v4, v8, 14
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vaesz.vs v4, v8
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@ -2168,6 +2168,29 @@
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#define MASK_VGHSH_VV 0xfe00707f
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#define MATCH_VGMUL_VV 0xa208a077
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#define MASK_VGMUL_VV 0xfe0ff07f
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/* Zvkned instructions. */
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#define MATCH_VAESDF_VS 0xa600a077
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#define MASK_VAESDF_VS 0xfe0ff07f
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#define MATCH_VAESDF_VV 0xa200a077
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#define MASK_VAESDF_VV 0xfe0ff07f
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#define MATCH_VAESDM_VS 0xa6002077
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#define MASK_VAESDM_VS 0xfe0ff07f
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#define MATCH_VAESDM_VV 0xa2002077
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#define MASK_VAESDM_VV 0xfe0ff07f
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#define MATCH_VAESEF_VS 0xa601a077
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#define MASK_VAESEF_VS 0xfe0ff07f
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#define MATCH_VAESEF_VV 0xa201a077
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#define MASK_VAESEF_VV 0xfe0ff07f
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#define MATCH_VAESEM_VS 0xa6012077
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#define MASK_VAESEM_VS 0xfe0ff07f
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#define MATCH_VAESEM_VV 0xa2012077
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#define MASK_VAESEM_VV 0xfe0ff07f
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#define MATCH_VAESKF1_VI 0x8a002077
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#define MASK_VAESKF1_VI 0xfe00707f
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#define MATCH_VAESKF2_VI 0xaa002077
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#define MASK_VAESKF2_VI 0xfe00707f
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#define MATCH_VAESZ_VS 0xa603a077
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#define MASK_VAESZ_VS 0xfe0ff07f
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/* Svinval instruction. */
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#define MATCH_SINVAL_VMA 0x16000073
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#define MASK_SINVAL_VMA 0xfe007fff
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@ -3302,6 +3325,18 @@ DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
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/* Zvkg instructions. */
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DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
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DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
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/* Zvkned instructions. */
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DECLARE_INSN(vaesdf_vs, MATCH_VAESDF_VS, MASK_VAESDF_VS)
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DECLARE_INSN(vaesdf_vv, MATCH_VAESDF_VV, MASK_VAESDF_VV)
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DECLARE_INSN(vaesdm_vs, MATCH_VAESDM_VS, MASK_VAESDM_VS)
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DECLARE_INSN(vaesdm_vv, MATCH_VAESDM_VV, MASK_VAESDM_VV)
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DECLARE_INSN(vaesef_vs, MATCH_VAESEF_VS, MASK_VAESEF_VS)
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DECLARE_INSN(vaesef_vv, MATCH_VAESEF_VV, MASK_VAESEF_VV)
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DECLARE_INSN(vaesem_vs, MATCH_VAESEM_VS, MASK_VAESEM_VS)
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DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV)
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DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
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DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
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DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
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/* Vendor-specific (T-Head) XTheadBa instructions. */
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DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
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/* Vendor-specific (T-Head) XTheadBb instructions. */
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@ -417,6 +417,7 @@ enum riscv_insn_class
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INSN_CLASS_ZVBB,
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INSN_CLASS_ZVBC,
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INSN_CLASS_ZVKG,
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INSN_CLASS_ZVKNED,
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INSN_CLASS_SVINVAL,
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INSN_CLASS_ZICBOM,
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INSN_CLASS_ZICBOP,
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@ -1912,6 +1912,19 @@ const struct riscv_opcode riscv_opcodes[] =
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{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
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{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
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/* Zvkned instructions. */
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{"vaesdf.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VV, MASK_VAESDF_VV, match_opcode, 0},
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{"vaesdf.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VS, MASK_VAESDF_VV, match_opcode, 0},
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{"vaesdm.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VV, MASK_VAESDM_VV, match_opcode, 0},
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{"vaesdm.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VS, MASK_VAESDM_VV, match_opcode, 0},
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{"vaesef.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VV, MASK_VAESEF_VV, match_opcode, 0},
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{"vaesef.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VS, MASK_VAESEF_VV, match_opcode, 0},
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{"vaesem.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VV, MASK_VAESEM_VV, match_opcode, 0},
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{"vaesem.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VS, MASK_VAESEM_VV, match_opcode, 0},
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{"vaeskf1.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1_VI, MASK_VAESKF1_VI, match_opcode, 0},
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{"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0},
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{"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0},
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/* Supervisor instructions. */
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{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
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{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
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