2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
PR ld/7036 * elfxx-ia64.c (elfNN_ia64_relax_section): Assume linker will always insert 32byte between the .plt and .text sections after the the first relaxation pass.
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2008-12-23 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/7036
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* elfxx-ia64.c (elfNN_ia64_relax_section): Assume linker will
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always insert 32byte between the .plt and .text sections after
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the the first relaxation pass.
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2008-12-23 Nick Clifton <nickc@redhat.com>
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PR 7093
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@ -994,8 +994,20 @@ elfNN_ia64_relax_section (bfd *abfd, asection *sec,
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+ sec->output_offset
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+ roff) & (bfd_vma) -4;
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/* The .plt section is aligned at 32byte and the .text section
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is aligned at 64byte. The .text section is right after the
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.plt section. After the first relaxation pass, linker may
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increase the gap between the .plt and .text sections up
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to 32byte. We assume linker will always insert 32byte
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between the .plt and .text sections after the the first
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relaxation pass. */
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if (tsec == ia64_info->plt_sec)
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offset = -0x1000000 + 32;
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else
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offset = -0x1000000;
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/* If the branch is in range, no need to do anything. */
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if ((bfd_signed_vma) (symaddr - reladdr) >= -0x1000000
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if ((bfd_signed_vma) (symaddr - reladdr) >= offset
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&& (bfd_signed_vma) (symaddr - reladdr) <= 0x0FFFFF0)
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{
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/* If the 60-bit branch is in 21-bit range, optimize it. */
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