These were renamed from bfd_read and bfd_write back in 2001 when they
lost an unnecessary parameter. Rename them back, and get rid of a few
casts that are only needed without prototyped functions (K&R C).
According to the reporter of this bug the newlib fseek implementation
is likely slowed down by locking and fflush, only attempting to
optimise seeks when the file is opened read-only. Thus when writing
the output we get a dramatic slowdown due to commit 014a602b86.
PR 30724
* bfd.c (enum bfd_last_io): New.
(struct bfd): Add last_io field.
* bfd-in2.h: Regenerate.
* bfd-io.c (bfd_bread, bfd_bwrite): Force seek if last_io is
opposite direction.
(bfd_seek): Reinstate optimisation for seek to same position.
Because the 'Ztso' extension is now ratified, it has a version number of 1.0
(not 0.1). This commit updates the number.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Update the version
number of the 'Ztso' extension since it's ratified.
PR 15545 * cache.c (bfd_cache_close_all): Extend description to note that all files will be closed, even those that are not cacheable. Add code to prevent a possible infinite loop.
Check for output buffer overruns.
* elf32-ppc.c (swap_reloc_out, count_and_swap_reloc_out): New
functions. Use throughout file.
* elf64-ppc.c (swap_reloc_out, count_and_swap_reloc_out): Likewise.
This fixes miscounting of dynamic relocations on GOT entries when
a) there are both local-dynamic and global-dynamic tls accesss for a
given symbol, and
b) the symbol is global with non-default visibility, and
c) the __tls_get_addr calls aren't optimised away.
PR 30697
bfd/
* elf32-ppc.c (allocate_dynrelocs): Correct local-dynamic
reloc count.
ld/
* testsuite/ld-powerpc/tls32ldgd.d,
* testsuite/ld-powerpc/tls32ldgd.s: New test.
* testsuite/ld-powerpc/powerpc.exp: Run it.
I noticed a few files double-included libcoff.h, and digging deeper I
found that the PEI_HEADERS define is a sort of external include guard.
This patch adds include guards to the few files in include/coff that
were missing one, and then removes the PEI_HEADERS workaround and the
redundant includes.
I didn't see anything in these files that indicated that
double-inclusion would be useful, so it seems to me that this approach
is ok.
Tested by rebuilding with --enable-targets=all.
2023-08-02 Tom Tromey <tromey@adacore.com>
* pei-x86_64.c (PEI_HEADERS): Do not define.
* pei-loongarch64.c (PEI_HEADERS): Do not define.
* pei-aarch64.c (PEI_HEADERS): Do not define.
* pe-x86_64.c (PEI_HEADERS): Do not define.
* pe-aarch64.c (PEI_HEADERS): Do not define.
* libpei.h (_LIBPEI_H): Add include guard.
* coff-x86_64.c (PEI_HEADERS): Do not check.
* coff-loongarch64.c (PEI_HEADERS): Do not check.
* coff-aarch64.c (PEI_HEADERS): Do not check.
include/ChangeLog
2023-08-02 Tom Tromey <tromey@adacore.com>
* coff/x86_64.h (COFF_X86_64_H): Add include guard.
* coff/loongarch64.h (COFF_LOONGARCH64_H): Add include guard.
* coff/aarch64.h (COFF_AARCH64_H): Add include guard.
This commit adds support for recently ratified vector FP16 extensions:
'Zvfh' and 'Zvfhmin'.
This is based on:
<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point>
<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfh-vector-extension-for-half-precision-floating-point>
Despite not having any new instructions, it will be necessary since those
extensions are already implemented in GCC.
Note that however, in this commit, following dependencies are implemented.
1. 'Zvfhmin' -> 'Zve32f'
2. 'Zvfh' -> 'Zvfhmin' (not 'Zvfh' -> 'Zve32f' as in the documentation)
3. 'Zvfh' -> 'Zfhmin'
This is because the instructions and configurations supported by the
'Zvfh' extension is a strict superset of the 'Zvfhmin' extension and
'Zvfh' -> 'Zve32f' dependency is indirectly derived from that fact.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add implications
related to 'Zvfh' and 'Zvfhmin' extensions.
(riscv_supported_std_z_ext) Add 'Zvfh' and 'Zvfhmin' to the list.
Further clarification is made so that 'Zve32x' implies 'Zicsr' (the same
implication is already implemented in LLVM).
See related issue (the author raised) on the vector specification:
<https://github.com/riscv/riscv-v-spec/issues/908>
and its resolution:
<https://github.com/riscv/riscv-v-spec/issues/909>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zve32x' -> 'Zicsr'.
Make the n64 ABI the default for 64-bit Linux targets specified with
`-gnuabi64' suffix included in the target triplet, for configurations
such as the Debian mips64el and mips64r6el ports. Adjust testsuite
configuration accordingly.
There are the following regressions with the new target triplet:
mips64-linux-gnuabi64 +FAIL: readelf -S bintest
mips64-linux-gnuabi64 +FAIL: MIPS reloc estimation 1
mips64el-linux-gnuabi64 +FAIL: readelf -S bintest
mips64el-linux-gnuabi64 +FAIL: MIPS reloc estimation 1
The `readelf' issue comes from a difference in section headers produced
that the `binutils/testsuite/binutils-all/readelf.s-64' pattern template
does not match. While there has been a precedent it does not appear to
me that there is a clear advantage from adding more and more variations
to the template rather than forking the existing template into multiple
ones for a more exact match. So this is best deferred to a separate
discussion.
The MIPS reloc estimation issue is an actual bug in `objdump', which
discards a number of trailing entries from output here for n64 composed
relocations:
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
0000000000000000 R_MIPS_NONE *ABS*
0000000000000000 R_MIPS_NONE *ABS*
and consequently `ld/testsuite/ld-mips-elf/reloc-estimate-1.d' does not
match even though ELF output produced is correct according to `readelf':
Relocation section '.rel.dyn' at offset 0x10400 contains 2 entries:
Offset Info Type Sym. Value Sym. Name
000000000000 000000000000 R_MIPS_NONE
Type2: R_MIPS_NONE
Type3: R_MIPS_NONE
000000010000 000300001203 R_MIPS_REL32 0000000000010010 foo@@V2
Type2: R_MIPS_64
Type3: R_MIPS_NONE
As a genuine bug this has to be handled separately.
Co-Authored by: Maciej W. Rozycki <macro@orcam.me.uk>
bfd/
* config.bfd: Add `mips64*el-*-linux*-gnuabi64' and
`mips64*-*-linux*-gnuabi64' targets.
binutils/
* testsuite/binutils-all/mips/mips.exp: Handle `*-*-*-gnuabi64'
targets.
* testsuite/binutils-all/objcopy.exp: Handle
`mips64*-*-*-gnuabi64' targets.
* testsuite/binutils-all/remove-relocs-01.d: Likewise.
* testsuite/binutils-all/remove-relocs-04.d: Likewise.
* testsuite/binutils-all/remove-relocs-05.d: Likewise.
* testsuite/binutils-all/remove-relocs-06.d: Likewise.
gas/
* configure.ac: Handle `mips64*-linux-gnuabi64' targets.
* configure: Regenerate.
* testsuite/gas/mips/compact-eh-eb-7.d: Handle
`mips64*-*-*-gnuabi64' targets.
* testsuite/gas/mips/compact-eh-el-7.d: Likewise.
ld/
* configure.tgt: Add `mips64*el-*-linux-gnuabi64' and
`mips64*-*-linux-gnuabi64' targets.
* testsuite/ld-undefined/undefined.exp: Handle
`mips64*-*-*-gnuabi64' targets.
* testsuite/ld-mips-elf/attr-gnu-4-10.d: Likewise.
* testsuite/ld-mips-elf/compact-eh6.d: Likewise.
* testsuite/ld-mips-elf/mips-elf.exp: Handle `*-*-*-gnuabi64'
targets.
This reverts commit 32f1c80375ebe8ad25d9805ee5889f0006c51e59. It had
two unrelated changes lumped together, one of which changed the meaning
of the `mipsisa64*-*-linux*' target triplets, which was not properly
evaluated.
This fixes failure of the "extract symbols" test for rs6000, where
--extract-symbols generates a non-zero sized .text. By the look of
coffcode.h the same problem might occur for coff/pe too, but doesn't
happen to trigger a test failure.
bfd/
* coffcode.h (coff_compute_section_file_positions): Don't
adjust size of !SEC_LOAD sections.
binutils/
* objcopy.c (setup_section): Clear SEC_LOAD for --extract-symbol.
The 'Zvkt' extension is listed on the added extensions in the GNU Binutils
version 2.41 (see binutils/NEWS). However, the support of this extension
was actually missing.
This commit adds actual support of this extension and adds implications
from 'Zvkn' and 'Zvks' superset extensions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets) Add implications from
'Zvkn' and 'Zvks'. (riscv_supported_std_z_ext): Add 'Zvkt' to
the supported extension list.
The version 1.0.4-1 of the code size reduction specification clarifies
that 'Zcf' implies 'F' and 'Zcd' implies 'D'.
cf:
<https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.4-1>
This commit adds those implications.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add two implications,
'Zcf' -> 'F' and 'Zcd' -> 'D'.
gas/ChangeLog:
* testsuite/gas/riscv/march-imply-zcd.d: New test.
* testsuite/gas/riscv/march-imply-zcf.d: New test.
As per:
<https://github.com/riscv/riscv-code-size-reduction/issues/221>,
the 'Zcf' extension does not exist on RV64. This is reflected on the
version 1.0.4-1 of the code size reduction specification:
<https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.4-1>.
This commit prohibits the combination: RV64 (or any ISA with XLEN > 32)
and the 'Zcf' extension.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Prohibit
combination of RV64 and 'Zcf'.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv64i_zcf.d: New test.
* testsuite/gas/riscv/march-fail-rv64i_zcf.l: Likewise.
bfd
* peXXigen.c (_bfd_XXi_only_swap_filehdr_out): If inserting a timestamp, use the value held in the SOURCE_DATE_EPOCH environment variable, if it is defined.
binutils
* doc/binutils.texi (objcopy): Document change in behaviour of objcopy's --preserve-dates command line option.
ld
* pe-dll.c (fill_edata): If inserting a timestamp, use the value held in the SOURCE_DATE_EPOCH environment variable, if it is defined.
* ld.texi (--insert-timestamp): Document change in behaviour.
In LoongArch, the R_LARCH_IRELATIVE relocations for local ifunc symbols are
in .rela.dyn. Before, this is done by loongarch_elf_finish_dynamic_sections.
But this function is called after elf_link_sort_relocs, it need to find a
null slot to insert IRELATIVE relocation.
Now, it is processed by elf_loongarch_output_arch_local_syms before
elf_link_sort_relocs, just need to call loongarch_elf_append_rela to
insert IRELATIVE relocation.
bfd/ChangeLog:
* elfnn-loongarch.c (elfNN_allocate_local_ifunc_dynrelocs): Return
type change to int.
(loongarch_elf_size_dynamic_sections): Delete (void *).
(loongarch_elf_finish_dynamic_symbol): Use loongarch_elf_append_rela
insert IRELATIVE relocation to .rela.dyn.
(elfNN_loongarch_finish_local_dynamic_symbol): Return type change to
int.
(loongarch_elf_finish_dynamic_sections): Delete process of local
ifunc symbols.
(elf_backend_output_arch_local_syms): New.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/local-ifunc-reloc.d: Regenerated.
For B16/B21/B26/PCREL20_S2 relocations, if immediate overflow check after
rightshift, and the mask need to include sign bit.
Now, the immediate overflow check before rightshift for easier understand.
bfd/ChangeLog:
* elfxx-loongarch.c (reloc_bits_pcrel20_s2): Delete.
(reloc_bits_b16): Delete.
(reloc_bits_b21): Delete.
(reloc_bits_b26): Delete.
(reloc_sign_bits): New.
For extreme code mode, the instruction sequences is
pcalau12i $t0, hi20
addi.d $t1, $zero, lo12
lu32i.d $t1, lo20
lu52i.d $t1, hi12
add.d $t1, $t0, $t1
If lo12 > 0x7ff, hi20 need to add 0x1, lo20 need to sub 0x1.
If hi20 > 0x7ffff, lo20 need to add 0x1.
bfd/ChangeLog:
* elfnn-loongarch.c (RELOCATE_CALC_PC32_HI20): Redefined.
(RELOCATE_CALC_PC64_HI32): Redefined.
This patch adds support for the V4 BPF instruction jal/gotol, which is
like ja/goto but it supports a signed 32-bit PC-relative (in number of
64-bit words minus one) target operand instead of the 16-bit signed
operand of the other instruction. This greatly increases the jump
range in BPF programs.
Tested in bpf-unkown-none.
bfd/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32.
* elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc.
* libbfd.h (bfd_reloc_code_real_names): Regenerate.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.
(md_assemble): Save the ids of successfully parsed instructions
and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
(md_apply_fix): Adapt to the new BFD reloc.
* testsuite/gas/bpf/jump.s: Test JAL.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document new instruction
jal/gotol.
Document new operand type disp32.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
opcodes/ChangeLog:
2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entry for jal.
CGEN is cool, but the BPF architecture is simply too bizarre for it.
The weird way of BPF to handle endianness in instruction encoding, the
weird C-like alternative assembly syntax, the weird abuse of
multi-byte (or infra-byte) instruction fields as opcodes, the unusual
presence of opcodes beyond the first 32-bits of some instructions, are
all examples of what makes it a PITA to continue using CGEN for this
port. The bpf.cpu file is becoming so complex and so nested with
p-macros that it is very difficult to read, and quite challenging to
update. Also, every time we are forced to change something in CGEN to
accommodate BPF requirements (which is often) we have to do extensive
testing to make sure we do not break any other target using CGEN.
This is getting un-maintenable.
So I have decided to bite the bullet and revamp/rewrite the port so it
no longer uses CGEN. Overall, this involved:
* To remove the cpu/bpf.{cpu,opc} descriptions.
* To remove the CGEN generated files.
* To replace the CGEN generated opcodes table with a new hand-written
opcodes table for BPF.
* To replace the CGEN generated disassembler wih a new disassembler
that uses the new opcodes.
* To replace the CGEN generated assembler with a new assembler that uses the
new opcodes.
* To replace the CGEN generated simulator with a new simulator that uses the
new opcodes. [This is pushed in GDB in another patch.]
* To adapt the build systems to the new situation.
Additionally, this patch introduces some extensions and improvements:
* A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF
relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These
relocations are used for section-relative 16-bit offsets used in
load/store instructions.
* The disassembler now has support for the "pseudo-c" assembly syntax of
BPF. What dialect to use when disassembling is controlled by a command
line option.
* The disassembler now has support for dumping instruction immediates in
either octal, hexadecimal or decimal. The used output base is controlled
by a new command-line option.
* The GAS BPF test suite has been re-structured and expanded in order to
test the disassembler pseudoc syntax support. Minor bugs have been also
fixed there. The assembler generic tests that were disabled for bpf-*-*
targets due to the previous implementation of pseudoc syntax are now
re-enabled. Additional tests have been added to test the new features of
the assembler. .dump files are no longer used.
* The linker BPF test suite has been adapted to the command line options
used by the new disassembler.
The result is very satisfactory. This patchs adds 3448 lines of code
and removes 10542 lines of code.
Tested in:
* Target bpf-unknown-none with 64-bit little-endian host and 32-bit
little-endian host.
* Target x86-64-linux-gnu with --enable-targets=all
Note that I have not tested in a big-endian host yet. I will do so
once this lands upstream so I can use the GCC compiler farm.
I have not included ChangeLog entries in this patch: these would be
massive and not very useful, considering this is pretty much a rewrite
of the port. I beg the indulgence of the global maintainers.
This patch support Zcb extension, contains new compressed instructions,
some instructions depend on other existed extension, like 'zba', 'zbb'
and 'zmmul'. Zcb also imply Zca extension to enable the compressing
features.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcb.d: New test.
* testsuite/gas/riscv/zcb.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_C_LBU): New opcode.
(MASK_C_LBU): New mask.
(MATCH_C_LHU): New opcode.
(MASK_C_LHU): New mask.
(MATCH_C_LH): New opcode.
(MASK_C_LH): New mask.
(MATCH_C_SB): New opcode.
(MASK_C_SB): New mask.
(MATCH_C_SH): New opcode.
(MASK_C_SH): New mask.
(MATCH_C_ZEXT_B): New opcode.
(MASK_C_ZEXT_B): New mask.
(MATCH_C_SEXT_B): New opcode.
(MASK_C_SEXT_B): New mask.
(MATCH_C_ZEXT_H): New opcode.
(MASK_C_ZEXT_H): New mask.
(MATCH_C_SEXT_H): New opcode.
(MASK_C_SEXT_H): New mask.
(MATCH_C_ZEXT_W): New opcode.
(MASK_C_ZEXT_W): New mask.
(MATCH_C_NOT): New opcode.
(MASK_C_NOT): New mask.
(MATCH_C_MUL): New opcode.
(MASK_C_MUL): New mask.
(DECLARE_INSN): New opcode.
* opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func.
(EXTRACT_ZCB_HALFWORD_UIMM): Ditto.
(ENCODE_ZCB_BYTE_UIMM): Ditto.
(ENCODE_ZCB_HALFWORD_UIMM): Ditto.
(VALID_ZCB_BYTE_UIMM): Ditto.
(VALID_ZCB_HALFWORD_UIMM): Ditto.
(enum riscv_insn_class): New extension class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): New operators.
* riscv-opc.c: New instructions.
This patch add Zca/f/d extensions support, since all ZC*
extensions will imply Zca extension, just enabled compress
feature when Zca extension is available.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extensions.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (riscv_set_arch): Extend compress check.
* testsuite/gas/riscv/zca.d: New test.
* testsuite/gas/riscv/zca.s: New test.
* testsuite/gas/riscv/zcd.d: New test.
* testsuite/gas/riscv/zcd.s: New test.
* testsuite/gas/riscv/zcf.d: New test.
* testsuite/gas/riscv/zcf.s: New test.
