The following patch attempts to use x86 SHA ISA if available to speed
up in my testing about 2.5x sha1 build-id processing (in my case on
AMD Ryzen 5 3600) while producing the same result.
I believe AArch64 has similar HW acceleration for SHA1, perhaps it
could be added similarly.
Note, seems lld uses BLAKE3 rather than md5/sha1. I think it would be
a bad idea to lie to users, if they choose --buildid=sha1, we should
be using SHA1, not some other checksum, but perhaps we could add some other
--buildid= styles and perhaps make one of the new the default.
Tested on x86_64-linux, both on Intel i9-7960X (which doesn't have
sha_ni ISA support) without/with the patch and on AMD Ryzen 5 3600
(which does have it) without/with the patch.
2023-11-28 Jakub Jelinek <jakub@redhat.com>
include/
* sha1.h (sha1_process_bytes_fn): New typedef.
(sha1_choose_process_bytes): Declare.
libiberty/
* configure.ac (HAVE_X86_SHA1_HW_SUPPORT): New check.
* sha1.c: If HAVE_X86_SHA1_HW_SUPPORT is defined, include x86intrin.h
and cpuid.h.
(sha1_hw_process_bytes, sha1_hw_process_block,
sha1_choose_process_bytes): New functions.
* config.in: Regenerated.
* configure: Regenerated.
ld/
* ldbuildid.c (generate_build_id): Use sha1_choose_process_bytes ()
instead of &sha1_process_bytes.
I noticed a few files double-included libcoff.h, and digging deeper I
found that the PEI_HEADERS define is a sort of external include guard.
This patch adds include guards to the few files in include/coff that
were missing one, and then removes the PEI_HEADERS workaround and the
redundant includes.
I didn't see anything in these files that indicated that
double-inclusion would be useful, so it seems to me that this approach
is ok.
Tested by rebuilding with --enable-targets=all.
2023-08-02 Tom Tromey <tromey@adacore.com>
* pei-x86_64.c (PEI_HEADERS): Do not define.
* pei-loongarch64.c (PEI_HEADERS): Do not define.
* pei-aarch64.c (PEI_HEADERS): Do not define.
* pe-x86_64.c (PEI_HEADERS): Do not define.
* pe-aarch64.c (PEI_HEADERS): Do not define.
* libpei.h (_LIBPEI_H): Add include guard.
* coff-x86_64.c (PEI_HEADERS): Do not check.
* coff-loongarch64.c (PEI_HEADERS): Do not check.
* coff-aarch64.c (PEI_HEADERS): Do not check.
include/ChangeLog
2023-08-02 Tom Tromey <tromey@adacore.com>
* coff/x86_64.h (COFF_X86_64_H): Add include guard.
* coff/loongarch64.h (COFF_LOONGARCH64_H): Add include guard.
* coff/aarch64.h (COFF_AARCH64_H): Add include guard.
This patch adds support for EF_BPF_CPUVER bits in the ELF
machine-dependent header flags. These bits encode the BPF CPU
version for which the object file has been compiled for.
The BPF assembler is updated so it annotates the object files it
generates with these bits.
The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the
appropriate ISA version if the user didn't specify an explicit ISA
version in the command line. Note that a value of zero in
EF_BPF_CPUVER is interpreted by the disassembler as "use the later
supported version" (the BPF CPU versions start with v1.)
The readelf utility is updated to pretty print EF_BPF_CPUVER when it
prints out the ELF header:
$ readelf -h a.out
ELF Header:
...
Flags: 0x4, CPU Version: 4
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/bpf.h (EF_BPF_CPUVER): Define.
* opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in
EF_BPF_CPUVER.
binutils/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* readelf.c (get_machine_flags): Recognize and pretty print BPF
machine flags.
opcodes/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-dis.c: Initialize asm_bpf_version to -1.
(print_insn_bpf): Set BPF ISA version from the cpu version ELF
header flags if no explicit version set in the command line.
* disassemble.c (disassemble_init_for_target): Remove unused code.
gas/ChangeLog:
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.h (elf_tc_final_processing): Define.
* config/tc-bpf.c (bpf_elf_final_processing): New function.
This patch adds support for the BPF V4 ISA byte swap instructions to
opcodes, assembler and disassembler.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_IMM32_BSWAP16): Define.
(BPF_IMM32_BSWAP32): Likewise.
(BPF_IMM32_BSWAP64): Likewise.
(enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}.
opcodes/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
instructions.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
This patch adds support for the V4 BPF instruction jal/gotol, which is
like ja/goto but it supports a signed 32-bit PC-relative (in number of
64-bit words minus one) target operand instead of the 16-bit signed
operand of the other instruction. This greatly increases the jump
range in BPF programs.
Tested in bpf-unkown-none.
bfd/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32.
* elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc.
* libbfd.h (bfd_reloc_code_real_names): Regenerate.
gas/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.
(md_assemble): Save the ids of successfully parsed instructions
and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
(md_apply_fix): Adapt to the new BFD reloc.
* testsuite/gas/bpf/jump.s: Test JAL.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document new instruction
jal/gotol.
Document new operand type disp32.
include/ChangeLog:
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL.
(enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI.
opcodes/ChangeLog:
2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entry for jal.
This commit adds the signed load to register (ldxs*) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Add entries for signed load
instructions.
(BPF_MODE_SMEM): Define.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Add signed load instructions.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document the signed load
instructions.
This commit adds the signed register move (movs) instructions
introduced in the BPF ISA version 4, including opcodes and assembler
tests.
Tested in bpf-unknown-none.
include/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (BPF_OFFSET16_MOVS8): Define.
(BPF_OFFSET16_MOVS16): Likewise.
(BPF_OFFSET16_MOVS32): Likewise.
(enum bpf_insn_id): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R.
opcodes/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
MOVS32{8,16,32}R instructions. and MOVS32I instructions.
gas/ChangeLog:
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Test movs instructions.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
bfd/ChangeLog:
* coff-rs6000.c (_bfd_xcoff_put_ldsymbol_name): Write len in
ldinfo->strings instead of directly in the output_bfd.
* coff64-rs6000.c (_bfd_xcoff64_put_ldsymbol_name): Likewise.
* xcofflink.c (struct xcoff_link_hash_table): Remove ldrel_count
field. Add ldinfo field.
(xcoff_mark_symbol): Adjust to new ldinfo field.
(xcoff_mark): Likewise.
(bfd_xcoff_link_count_reloc): Likewise.
(xcoff_build_loader_section): Split into two functions: one that
build the loader section (this function) and one that only size
it...
(xcoff_size_loader_section): ... (this function).
(bfd_xcoff_size_dynamic_sections): Adapt to new ldinfo field.
Move the part where the dynamic sections are build to ...
(bfd_xcoff_build_dynamic_sections): ... this function.
* xcofflink.h: Add bfd_xcoff_build_dynamic_sections prototype.
include/ChangeLog:
* coff/xcoff.h (struct xcoff_loader_info): Add ldrel_count and
libpath fields.
ld/ChangeLog:
* emultempl/aix.em (_after_allocation): New function.
bfd * coff-i386.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_i386_relocation_section): Add support for R_SECTION.
(coff_i386_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* coff-x86_64.c (in_reloc_p): Add R_SECTION.
(howto_table): Add R_SECTION.
(coff_pe_amd64_relocation_section): Add support for R_SECTION.
(coff_amd64_reloc_type_lookup): Add support for
BFD_RELOC_16_SECCIDX.
* reloc.c: Add BFD_RELOC_16_SECIDX.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas * config/tc-i386.c (pe_directive_secidx): New function.
(md_pseudo_table): Add support for secidx.
(x86_cons_fix_new): Likewise.
(tc_gen_reloc): Likewise.
* expr.c (op_rank): Add O_secidx.
* expr.h (operatorT): Likewise.
* symbols.c (resolve_symbol_value): Add support for O_secidx.
* testsuite/gas/i386/secidx.s: New test source file.
* testsuite/gas/i386/secidx.d: New test driver file.
* testsuite/gas/i386/i386.exp: Run new test.
include * coff/i386.h: Define R_SECTION.
* coff/x86_64.h: Likewise.
ld * testsuite/ld-pe/secidx1.s: New test source file.
* testsuite/ld-pe/secidx2.s: New test source file.
* testsuite/ld-pe/secidx.d: New test driver file.
* testsuite/ld-pe/secidx_64.d: New test driver file.
* testsuite/ld-pe/pe.exp: Add new tests.
This core dump note contains the value of the base address of the %fs
and %gs segments for both i386 and amd64 core dumps. It is primarily
useful in resolving the address of TLS variables in core dumps.
binutils/ChangeLog:
* readelf.c (get_freebsd_elfcore_note_type): Handle
NT_FREEBSD_X86_SEGBASES.
include/ChangeLog:
* elf/common.h (NT_FREEBSD_X86_SEGBASES): Define.
Handle the NT_AMDGPU_METADATA note, which is described here:
https://llvm.org/docs/AMDGPUUsage.html#code-object-v3-note-records
As of this patch, just print out the name, not the contents, which is in
the msgpack format.
binutils/ChangeLog:
* readelf.c (get_amdgpu_elf_note_type): New.
(process_note): Handle "AMDGPU" notes.
include/ChangeLog:
* elf/amdgcn.h (NT_AMDGPU_METADATA): New.
Change-Id: Id2dba2e2aeaa55ef7464fb35aee9c7d5f96ddb23
Decode and print the AMDGPU-specific fields of e_flags, as documented
here:
https://llvm.org/docs/AMDGPUUsage.html#header
That is:
- The specific GPU model
- Whether the xnack and sramecc features are enabled
The result looks like:
- Flags: 0x52f
+ Flags: 0x52f, gfx906, xnack any, sramecc any
The flags for the "HSA" OS ABI are properly versioned and documented on
that page. But the NONE, PAL and MESA3D OS ABIs are not well documented
nor versioned. Taking a peek at the LLVM source code, we see that they
encode their flags the same way as HSA v3. For example, for PAL:
c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)
So for those other OS ABIs, we read them the same as HSA v3.
binutils/ChangeLog:
* readelf.c: Include elf/amdgcn.h.
(decode_AMDGPU_machine_flags): New.
(get_machine_flags): Handle flags for EM_AMDGPU machine type.
include/ChangeLog:
* elf/amdgcn.h: Add EF_AMDGPU_MACH_AMDGCN_* and
EF_AMDGPU_FEATURE_* defines.
Change-Id: Ib5b94df7cae0719a22cf4e4fd0629330e9485c12
When the machine is EM_AMDGPU, handle the various OS ABIs described
here:
https://llvm.org/docs/AMDGPUUsage.html#header
For a binary with the HSA OS ABI, the change looks like:
- OS/ABI: <unknown: 40>
+ OS/ABI: AMD HSA
binutils/ChangeLog:
* readelf.c (get_osabi_name): Handle EM_AMDGPU OS ABIs.
include/ChangeLog:
* elf/common.h (ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D):
New.
Change-Id: I383590c390f7dc2fe0f902f50038735626d71863
Add support for the AMDGCN architecture to BFD.
This is the bare minimum to get
$ ./configure --target=amdgcn-hsa-amdhsa --disable-gas
$ make all-binutils
working later in this series.
The specific AMDGCN models added here are a bit arbitrary, based on
what we intend to initially support in GDB. This list will need to be
updated in the future anyway. The complete up-to-date list of existing
AMDGPU models can be found here:
https://llvm.org/docs/AMDGPUUsage.html#processors
The ELF format for this architecture is documented here:
https://llvm.org/docs/AMDGPUUsage.html#elf-code-object
The flags for the "HSA" OS ABI are properly versioned and documented on
that page. But the NONE, PAL and MESA3D OS ABIs are not well documented
nor versioned. Taking a peek at the LLVM source code, we see that they
encode their flags the same way as HSA v3. For example, for PAL:
c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)
So at least, we know that all AMDGPU objects (of which AMDGCN objects
are a subset of) at the time of writing encode the specific GPU model in
the EF_AMDGPU_MACH field of e_flags.
bfd/ChangeLog:
* Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES):
Add cpu-amdgcn.c.
(BFD64_BACKENDS): Add elf64-amdgcn.lo.
(BFD64_BACKENDS_CFILES): Add elf64-amdgcn.c.
* Makefile.in: Re-generate.
* cpu-amdgcn.c: New.
* elf64-amdgcn.c: New.
* archures.c (bfd_architecture): Add bfd_arch_amdgcn and related
mach defines.
(bfd_amdgcn_arch): New.
(bfd_archures_list): Add bfd_amdgcn_arch.
* bfd-in2.h: Re-generate.
* config.bfd: Handle amdgcn* target.
* configure.ac: Handle amdgcn_elf64_le_vec.
* configure: Re-generate.
* elf-bfd.h (elf_target_id): Add AMDGCN_ELF_DATA.
* targets.c (amdgcn_elf64_le_vec): New.
(_bfd_target_vector): Add amdgcn_elf64_le_vec.
include/ChangeLog:
* elf/amdgpu.h: New.
* elf/common.h (ELFOSABI_AMDGPU_HSA): Add.
Change-Id: I969f7b14960797e88891c308749a6e341eece5b2
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
FreeBSD's kernel has recently added two new ELF auxiliary vector
entries. AT_FXRNG points to a root seed version for the kernel's
PRNG. Userland can use this to reseed a userland PRNG after the
kernel's PRNG has reseeded. AT_KPRELOAD is the base address of a
kernel-provided vDSO.
This change displays the proper name and description of these entries
in 'info auxv'.
include/ChangeLog:
* elf/common.h (AT_FREEBSD_FXRNG, AT_FREEBSD_KPRELOAD): Define.
In preparation for the next commit, which will add GDB support for
RISC-V disassembler options, this commit restructures how the
disassembler options are managed within libopcodes.
The implementation provided here is based on this mailing list patch
which was never committed:
https://sourceware.org/pipermail/binutils/2021-January/114944.html
which in turn took inspiration from the MIPS implementation of the
same feature.
The biggest changes from the original mailing list post are:
1. The GDB changes have been split into a separate patch, and
2. The `riscv_option_args_privspec` variable, which held the valid
priv-spec values is now gone, instead we use the `riscv_priv_specs`
array from bfd/cpu-riscv.c instead.
Co-authored-by: Simon Cook <simon.cook@embecosm.com>
include/ChangeLog:
* dis-asm.h (disassembler_options_riscv): Declare.
opcodes/ChangeLog:
* riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
(riscv_options): New static global.
(disassembler_options_riscv): New function.
(print_riscv_disassembler_options): Rewrite to use
disassembler_options_riscv.
Although the XScale and its iwMMX extensions are implemented in the
Arm co-processor space, they are not considered to be part of the FPU
specification. In particular, they cannot be enabled or disabled via
a .fpu directive. It's therefore incorrect to strip these properties
when a new .fpu directive is encountered.
Note that the legacy Maverick co-processor is considered to be a FPU
and it is possible to control this via the .fpu directive.
include:
PR gas/28031
* opcode/arm.h (FPU_ANY): Exclude XScale-related features.
Implement GNU_PROPERTY_UINT32_AND_XXX/GNU_PROPERTY_UINT32_OR_XXX:
https://sourceware.org/pipermail/gnu-gabi/2021q1/000467.html
1. GNU_PROPERTY_UINT32_AND_LO..GNU_PROPERTY_UINT32_AND_HI
#define GNU_PROPERTY_UINT32_AND_LO 0xb0000000
#define GNU_PROPERTY_UINT32_AND_HI 0xb0007fff
A bit in the output pr_data field is set only if it is set in all
relocatable input pr_data fields. If all bits in the the output
pr_data field are zero, this property should be removed from output.
If the bit is 1, all input relocatables have the feature. If the
bit is 0 or the property is missing, the info is unknown.
2. GNU_PROPERTY_UINT32_OR_LO..GNU_PROPERTY_UINT32_OR_HI
#define GNU_PROPERTY_UINT32_OR_LO 0xb0008000
#define GNU_PROPERTY_UINT32_OR_HI 0xb000ffff
A bit in the output pr_data field is set if it is set in any
relocatable input pr_data fields. If all bits in the the output
pr_data field are zero, this property should be removed from output.
If the bit is 1, some input relocatables have the feature. If the
bit is 0 or the property is missing, the info is unknown.
bfd/
* elf-properties.c (_bfd_elf_parse_gnu_properties): Handle
GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI,
GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI.
(elf_merge_gnu_properties): Likewise.
binutils/
* readelf.c (print_gnu_property_note): Handle
GNU_PROPERTY_UINT32_AND_LO, GNU_PROPERTY_UINT32_AND_HI,
GNU_PROPERTY_UINT32_OR_LO and GNU_PROPERTY_UINT32_OR_HI.
include/
* elf/common.h (GNU_PROPERTY_UINT32_AND_LO): New.
(GNU_PROPERTY_UINT32_AND_HI): Likewise.
(GNU_PROPERTY_UINT32_OR_LO): Likewise.
(GNU_PROPERTY_UINT32_OR_HI): Likewise.
ld/
* testsuite/ld-elf/property-and-1.d: New file.
* testsuite/ld-elf/property-and-1.s: Likewise.
* testsuite/ld-elf/property-and-2.d: Likewise.
* testsuite/ld-elf/property-and-2.s: Likewise.
* testsuite/ld-elf/property-and-3.d: Likewise.
* testsuite/ld-elf/property-and-3.s: Likewise.
* testsuite/ld-elf/property-and-4.d: Likewise.
* testsuite/ld-elf/property-and-empty.s: Likewise.
* testsuite/ld-elf/property-or-1.d: Likewise.
* testsuite/ld-elf/property-or-1.s: Likewise.
* testsuite/ld-elf/property-or-2.d: Likewise.
* testsuite/ld-elf/property-or-2.s: Likewise.
* testsuite/ld-elf/property-or-3.d: Likewise.
* testsuite/ld-elf/property-or-3.s: Likewise.
* testsuite/ld-elf/property-or-4.d: Likewise.
* testsuite/ld-elf/property-or-empty.s: Likewise.
The idea of this change is simple: Populate a data structure, namely
"disasm_option_and_arg_t" from "include/dis-asm.h", to encompass the
disassembly options and their possible arguments.
This will make it easier to manage or extend those options by adapting
entries in a data structure, "arc_options". There will be lesser need
to hard-code the options in the code itself. Moreover, ARC GDB will
use this population function, "disassembler_options_arc ()", to enable
the "set disassembler-option" for ARC targets. The gdb change will be
in a separate patch though.
The changes in this patch can be divided into:
1) Introduction of "disassembler_options_arc ()" that will return a
"disasm_option_and_arg_t" structure representing the disassembly
options and their likely arguments.
2) New data type "arc_options_arg_t" and new data "arc_options".
These are the internals for keeping track of options and arguments
entries that can easily be extended.
3) To print the options, the "print_arc_disassembler_options ()" has
been adjusted to use this dynamically built structure instead of having
them hard-coded inside.
To see this in effect, one can look into the output of:
$ ./binutils/objdump --help
...
The following ARC specific disassembler options are...
...
include/ChangeLog:
* dis-asm.h (disassembler_options_arc): New prototype.
opcodes/ChangeLog:
* arc-dis.c (arc_option_arg_t): New enumeration.
(arc_options): New variable.
(disassembler_options_arc): New function.
(print_arc_disassembler_options): Reimplement in terms of
"disassembler_options_arc".
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.
include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.
In preparation for the next change factor out code for ISA matching
against instruction flags used in MIPS opcode tables, similarly to how
CPU matching is already done. No functional change, though for clarity
split the single `if' statement into multiple ones and use temporaries
rather than repeated expressions.
include/
* opcode/mips.h (isa_is_member): New inline function, factored
out from...
(opcode_is_member): ... here.
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
