When deleting NOP instructions addend by .align at second pass, this may cause
the PC decrease but the symbol address to remain unchanged due to section
alignment.
To solve this question, we subtract a maximux alignment of all sections like
RISC-V.
Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
With old "medium" code model, we call a function with a pair of PCALAU12I
and JIRL instructions. The assembler produces something like:
8: 1a00000c pcalau12i $t0, 0
8: R_LARCH_PCALA_HI20 g
c: 4c000181 jirl $ra, $t0, 0
c: R_LARCH_PCALA_LO12 g
The linker generates a "PLT entry" for data without any diagnostic.
If "g" is a data symbol and ld with -shared option, it may load two
instructions in the PLT.
Without -shared option, loongarch_elf_adjust_dynamic_symbol can delete PLT
entry.
For R_LARCH_PCALA_HI20 relocation, linker only generate PLT entry for STT_FUNC
and STT_GNU_IFUNC symbols.
Add tls le relax support and related relocs in bfd.
New relocation related explanation can refer to the following url:
https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc
This support does two main things:
1. Implement support for three new relocation items in bfd.
The three new relocation items are shown below:
R_LARCH_TLS_LE_ADD_R
R_LARCH_TLS_LE_HI20_R
R_LARCH_TLS_LE_LO12_R
2. ADD a new macro RELOCATE_TLS_TP32_HI20
Handle problems caused by symbol extensions in TLS LE, The processing
is similar to the macro RELOCATE_CALC_PC32_HI20 method.
3. Implement the tls le relax function.
bfd/ChangeLog:
* bfd-in2.h: Add relocs related to tls le relax.
* elfnn-loongarch.c:
(loongarch_relax_tls_le): New function.
(RELOCATE_TLS_TP32_HI20): New macro.
(loongarch_elf_check_relocs): Add new reloc support.
(perform_relocation): Likewise.
(loongarch_elf_relocate_section): Handle new relocs related to relax.
(loongarch_elf_relax_section): Likewise.
* elfxx-loongarch.c:
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type.
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise.
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise.
* libbfd.h: Add relocs related to tls le relax.
* reloc.c: Likewise.
1.The linker for each DESC generates a R_LARCH_TLS_DESC64 dynamic
relocation, which relocation is placed at .rela.dyn.
TLSDESC always allocates two GOT slots and one dynamic relocation
space to TLSDESC.
2. When using multiple ways to access the same TLS variable, a
maximum of 5 GOT slots are used. For example, using GD, TLSDESC,
and IE to access the same TLS variable, GD always uses the first
two of the five GOT, TLSDESC uses the third and fourth, and IE
uses the last.
If the symbol index is not zero, the addend is used to represent
the first and the third expressions of the .align.
The lowest 8 bits are used to represent the first expression.
Other bits are used to represent the third expression.
The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405.
The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405.
Even in shared objects, la.got -> la.pcrel relaxation can still be
performed for symbols with hidden visibility. For example, if a.c is:
extern int x;
int f() { return x++; }
and b.c is:
int x = 114514;
If compiling and linking with:
gcc -shared -fPIC -O2 -fvisibility=hidden a.c b.c
Then the la.got in a.o should be relaxed to la.pcrel, and the resulted f
should be like:
pcaddi $t0, x
ldptr.w $a0, $t0, 0
addi.w $t1, $a0, 1
stptr.w $t1, $t0, 0
ret
Remove bfd_link_executable from the condition of la.got -> la.pcrel
relaxation so this will really happen. The SYMBOL_REFERENCES_LOCAL
check is enough not to wrongly relax preemptable symbols (for e.g.
when -fvisibility=hidden is not used).
Note that on x86_64 this is also relaxed and the produced code is like:
lea x(%rip), %rdx
mov (%rdx), %rax
lea 1(%rax), %ecx
mov %ecx, (%rdx)
ret
Tested by running ld test suite, bootstrapping and regtesting GCC with
the patched ld, and building and testing Glibc with the patched ld. No
regression is observed.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and
these two instructions must adjacent.
The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
Previously the condition prevented shared objects from being relaxed.
To remove the limitation, we need to update program header size and
.eh_frame_hdr size before relaxation.
Before, readelf -d RELASZ is the sum of .rela.dyn size and .rela.plt size.
To consistent with LoongArch lld, RELASZ chang to only the size of .rela.dyn.
In LoongArch, the R_LARCH_IRELATIVE relocations for local ifunc symbols are
in .rela.dyn. Before, this is done by loongarch_elf_finish_dynamic_sections.
But this function is called after elf_link_sort_relocs, it need to find a
null slot to insert IRELATIVE relocation.
Now, it is processed by elf_loongarch_output_arch_local_syms before
elf_link_sort_relocs, just need to call loongarch_elf_append_rela to
insert IRELATIVE relocation.
bfd/ChangeLog:
* elfnn-loongarch.c (elfNN_allocate_local_ifunc_dynrelocs): Return
type change to int.
(loongarch_elf_size_dynamic_sections): Delete (void *).
(loongarch_elf_finish_dynamic_symbol): Use loongarch_elf_append_rela
insert IRELATIVE relocation to .rela.dyn.
(elfNN_loongarch_finish_local_dynamic_symbol): Return type change to
int.
(loongarch_elf_finish_dynamic_sections): Delete process of local
ifunc symbols.
(elf_backend_output_arch_local_syms): New.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/local-ifunc-reloc.d: Regenerated.
For extreme code mode, the instruction sequences is
pcalau12i $t0, hi20
addi.d $t1, $zero, lo12
lu32i.d $t1, lo20
lu52i.d $t1, hi12
add.d $t1, $t0, $t1
If lo12 > 0x7ff, hi20 need to add 0x1, lo20 need to sub 0x1.
If hi20 > 0x7ffff, lo20 need to add 0x1.
bfd/ChangeLog:
* elfnn-loongarch.c (RELOCATE_CALC_PC32_HI20): Redefined.
(RELOCATE_CALC_PC64_HI32): Redefined.
Add relax support and related relocs in bfd.
bfd/ChangeLog:
* bfd-in2.h: Add relocs related to relax.
* elfnn-loongarch.c (struct loongarch_elf_link_hash_table): New integer
pointer (data_segment_phase) to monitor the data segment phase.
(loongarch_elf_check_relocs): Swap B21/B26 reloc sequence.
(loongarch_elf_adjust_dynamic_symbol): Fix code format.
(loongarch_reloc_rewrite_imm_insn): Fix function call.
(perform_relocation): Handle new relocs related to relax.
(RELOCATE_CALC_PC32_HI20): Fix code format.
(RELOCATE_CALC_PC64_HI32): Likewise.
(loongarch_elf_relocate_section): Handle new relocs related to relax.
(loongarch_relax_delete_bytes): New function.
(loongarch_relax_pcala_addi): Likewise.
(loongarch_relax_pcala_ld): Likewise.
(bfd_elfNN_loongarch_set_data_segment_info): Likewise.
(loongarch_relax_align): Likewise.
(loongarch_elf_relax_section): Likewise.
(bfd_elfNN_bfd_relax_section): New macro define.
* elfxx-loongarch.c (reloc_bits): New bfd point parameter.
(reloc_bits_b16): Likewise.
(reloc_bits_b21): Likewise.
(reloc_bits_b26): Likewise.
(loongarch_adjust_reloc_bitsfield): Likewise.
(reloc_bits_pcrel20_s2): New function.
(loongarch_elf_add_sub_reloc): Likewise.
(loongarch_elf_add_sub_reloc_uleb128): Likewise.
(loongarch_write_unsigned_leb128): New function.
* elfxx-loongarch.h (loongarch_adjust_reloc_bitsfield): New bfd point
parameter.
(bfd_elf32_loongarch_set_data_segment_info): New declare.
(bfd_elf64_loongarch_set_data_segment_info): Likewise.
(loongarch_write_unsigned_leb128): Likewise.
* libbfd.h: Add relocs related to relax.
* reloc.c: Add relocs related to relax.
If a function symbol only get its address by la.global, without
directly called by bl instruction, the PLT entry is not required.
bfd/ChangeLog:
* elfnn-loongarch.c (loongarch_elf_adjust_dynamic_symbol): Fix PLT
entry generate bug.
ld/ChangeLog:
* testsuite/ld-elf/shared.exp: Clear xfail for LoongArch.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
loongarch_elf_finish_dynamic_symbol is called after elf_link_sort_relocs
if -z combreloc. elf_link_sort_relocs redistributes the contents of
.rela.* sections those would be merged into .rela.dyn, so the slot for
R_LARCH_IRELATIVE may be out of relplt->contents now.
To make things worse, the boundary check
dyn < dyn + relplt->size / sizeof (*dyn)
is obviously wrong ("x + 10 < x"? :), causing the issue undetected
during the linking process and the resulted executable suddenly crashes
at runtime.
The issue was found during an attempt to add static-pie support to the
toolchain.
Fix it by iterating through the inputs of .rela.dyn to find the slot.
Local ifuncs are always resolved at runtime via R_LARCH_IRELATIVE, so
there is no need to write anything into GOT. And when we write the GOT
we actually trigger a heap-buffer-overflow: If a and b are different
sections, we cannot access something in b with "a->contents + (offset
from a)" because "a->contents" and "b->contents" are heap buffers
allocated separately, not slices of a large buffer.
So stop writing into GOT for local ifunc now.
Fix the bug that can not generate func@plt
when linking a undefined function with cmodel=medium.
Add testcase.
bfd/
* elfnn-loongarch.c
ld/testsuite/ld-loongarch-elf/
* cmodel-libjirl.dd
* cmodel.exp
* libjirl.s
Some R_LARCH_64 in section .eh_frame will to generate
R_LARCH_NONE, we change relocation to R_LARCH_32_PCREL
from R_LARCH_64 in setction .eh_frame and not generate
dynamic relocation for R_LARCH_32_PCREL.
Add New relocate type R_LARCH_32_PCREL for .eh_frame.
include/elf/
loongarch.h
bfd/
bfd/bfd-in2.h
libbfd.h
reloc.c
elfxx-loongarch.c
elfnn-loongarch.c
gas/config/
tc-loongarch.c
binutils/
readelf.c
ld/testsuite/ld-elf/
eh5.d
Delete R_LARCH_IRELATIVE from dynamic loader (glibc ld.so) when
loading lazy function (rela.plt section).
In dynamic programes, move ifunc dynamic relocate info to section
srelgot from srelplt.
bfd/
elfnn-loongarch.c
Fix it some more.
bfd/
* elfnn-loongarch.c: Remove commented out elf_backend_* defines.
ld/
* testsuite/ld-elf/elf.exp (target_defaults_to_execstack): Match
arm*. Delete loongarch.
Various packages (glib and gtk4 for example) produces data-only objects
using `ld -r -b binary` or `objcopy`, with no elf header flags set. But
these files also have no code sections, so they should be compatible
with all ABIs.
bfd/
* elfnn-loongarch.c (elfNN_loongarch_merge_private_bfd_data):
Skip ABI checks if the input has no code sections.
Reported-by: Wu Xiaotian <yetist@gmail.com>
Suggested-by: Wang Xuerui <i@xen0n.name>
Signed-off-by: Xi Ruoyao <xry111@mengyan1223.wang>
Some test cases about ifunc.
bfd/
* elfnn-loongarch.c
* elfxx-loongarch.h
=== ld Summary ===
of expected passes 1430
of expected failures 11
of untested testcases 1
of unsupported tests 154
Replace the magic numbers in gas(tc-loongarch.c) and
bfd(elfnn-loongarch.c) with the functions defined in
the howto table(elfxx-loongarch.c).
gas/
* config/tc-loongarch.c: use functions.
bfd/
* elfnn-loongarch.c: use functions.
* elfxx-loongarch.c: define functions.
* elfxx-loongarch.h
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
