8f29211c3f
We can't use the PLT entry as the function address for PIC since the PIC register may not be set up properly for indirect call. bfd/ PR ld/27998 * elf32-i386.c (elf_i386_relocate_section): Don't allow GOTOFF relocation against IFUNC symbol for PIC. ld/ PR ld/27998 * testsuite/ld-i386/pr27998a.d: Replace -shared with -e bar. * testsuite/ld-i386/pr27998b.d: Expect a linker error. * testsuite/ld-ifunc/ifunc-2-i386-now.d: Updated. * testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386.s: Replace @GOTOFF with @GOT. * testsuite/ld-ifunc/ifunc-2-local-i386.s: Likewise.
37 lines
1.0 KiB
Makefile
37 lines
1.0 KiB
Makefile
#source: ifunc-2-i386.s
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#ld: -z now -m elf_i386 -shared --hash-style=sysv -z noseparate-code $NO_DT_RELR_LDFLAGS
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#as: --32
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#objdump: -dw
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#target: x86_64-*-* i?86-*-*
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#notarget: *-*-lynxos *-*-nto*
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.*: +file format .*
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Disassembly of section .plt:
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0+f0 <\*ABS\*@plt-0x10>:
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+[a-f0-9]+: ff b3 04 00 00 00 push 0x4\(%ebx\)
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+[a-f0-9]+: ff a3 08 00 00 00 jmp \*0x8\(%ebx\)
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+[a-f0-9]+: 00 00 add %al,\(%eax\)
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...
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0+100 <\*ABS\*@plt>:
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+[a-f0-9]+: ff a3 0c 00 00 00 jmp \*0xc\(%ebx\)
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+[a-f0-9]+: 68 00 00 00 00 push \$0x0
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+[a-f0-9]+: e9 e0 ff ff ff jmp f0 <\*ABS\*@plt-0x10>
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Disassembly of section .text:
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0+110 <foo>:
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+[a-f0-9]+: c3 ret
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0+111 <bar>:
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+[a-f0-9]+: e8 00 00 00 00 call 116 <bar\+0x5>
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+[a-f0-9]+: 5b pop %ebx
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+[a-f0-9]+: 81 c3 9e 10 00 00 add \$0x109e,%ebx
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+[a-f0-9]+: e8 de ff ff ff call 100 <\*ABS\*@plt>
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+[a-f0-9]+: 8b 83 0c 00 00 00 mov 0xc\(%ebx\),%eax
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+[a-f0-9]+: c3 ret
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#pass
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