binutils-gdb

History

Mike Frysinger 16a6d5420b sim: example-synacor: move libsim.a creation to top-level

The objects are still compiled in the subdir, but the creation of the
archive itself is in the top-level.  This is a required step before we
can move compilation itself up, and makes it easier to review.

The downside is that each object compile is a recursive make instead of
a single one.  On my 4 core system, it adds ~100msec to the build per
port, so it's not great, but it shouldn't be a big deal.  This will go
away of course once the top-level compiles objects.

2023-01-10 01:15:24 -05:00

ChangeLog-2021

sim: rename ChangeLog files to ChangeLog-2021

2021-08-17 20:27:36 -04:00

example-synacor-sim.h

Update copyright year range in header of all files managed by GDB

2023-01-01 17:01:16 +04:00

interp.c

Update copyright year range in header of all files managed by GDB

2023-01-01 17:01:16 +04:00

local.mk

sim: example-synacor: move libsim.a creation to top-level

2023-01-10 01:15:24 -05:00

Makefile.in

sim: example-synacor: move libsim.a creation to top-level

2023-01-10 01:15:24 -05:00

README

…

README.arch-spec

…

sim-main.c

Update copyright year range in header of all files managed by GDB

2023-01-01 17:01:16 +04:00

sim-main.h

Update copyright year range in header of all files managed by GDB

2023-01-01 17:01:16 +04:00

README

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.