1e2e8c529c
- 32 128 bit vector registers (overlapping with the existing 16 64 bit floating point registers) - vector double instructions - vector integer instructions - scalar vector instructions (allowing to have more floating point registers for scalar operations) - vector string instructions gas/ChangeLog: * config/tc-s390.c (struct pd_reg): Remove. (pre_defined_registers): Remove. (REG_NAME_CNT): Remove. (reg_name_search): Calculate the register number instead of doing a lookup. (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new reg_name_search signature. (s390_parse_cpu): Support the new arch string z13. (s390_insert_operand): Support for vector registers with the extra field for the fifth bit of each vector register operand. (md_gather_operand): Adjust to the new handling of optional parameters. * doc/as.texinfo: Document the z13 cpu string. gas/testsuite/ChangeLog: * gas/s390/esa-g5.d: Add a variant without the optional operand. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z9-109.d: Likewise. * gas/s390/esa-z9-109.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise. * gas/s390/zarch-z10.d: For variants with a zero optional argument it is not dumped by objdump anymore. * gas/s390/zarch-zEC12.d: Likewise. * gas/s390/zarch-z13.d: New file. * gas/s390/zarch-z13.s: New file. * gas/s390/s390.exp: Run the test for the z13 files. include/opcode/ChangeLog: * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. ld/testsuite/ChangeLog: * ld-s390/tlsbin.dd: The nopr register operand is optional and not printed if 0 anymore. opcodes/ChangeLog: * s390-dis.c (s390_extract_operand): Support vector register operands. (s390_print_insn_with_opcode): Support new operands types and add new handling of optional operands. * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove and include opcode/s390.h instead. (struct op_struct): New field `flags'. (insertOpcode, insertExpandedMnemonic): New parameter `flags'. (dumpTable): Dump flags. (main): Parse flags from the s390-opc.txt file. Add z13 as cpu string. * s390-opc.c: Add new operands types, instruction formats, and instruction masks. (s390_opformats): Add new formats for .insn. * s390-opc.txt: Add new instructions.
63 lines
2.6 KiB
Makefile
63 lines
2.6 KiB
Makefile
#name: s390x opcode
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#objdump: -dr
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.*: +file format .*
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Disassembly of section .text:
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.* <foo>:
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.*: b2 ec 00 60 [ ]*etnd %r6
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.*: e3 67 8a 4d fe 25 [ ]*ntstg %r6,-5555\(%r7,%r8\)
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.*: b2 fc 6f a0 [ ]*tabort 4000\(%r6\)
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.*: e5 60 6f a0 fd e8 [ ]*tbegin 4000\(%r6\),65000
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.*: e5 61 6f a0 fd e8 [ ]*tbeginc 4000\(%r6\),65000
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.*: b2 f8 00 00 [ ]*tend
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.*: c7 a0 6f a0 00 00 [ ]*bpp 10,1e <foo\+0x1e>,4000\(%r6\)
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.*: c5 a0 00 00 00 0c [ ]*bprp 10,24 <foo\+0x24>,3c <foo\+0x3c>
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.*: b2 fa 00 ad [ ]*niai 10,13
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.*: e3 67 8a 4d fe 9f [ ]*lat %r6,-5555\(%r7,%r8\)
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.*: e3 67 8a 4d fe 85 [ ]*lgat %r6,-5555\(%r7,%r8\)
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.*: e3 67 8a 4d fe c8 [ ]*lfhat %r6,-5555\(%r7,%r8\)
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.*: e3 67 8a 4d fe 9d [ ]*llgfat %r6,-5555\(%r7,%r8\)
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.*: e3 67 8a 4d fe 9c [ ]*llgtat %r6,-5555\(%r7,%r8\)
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.*: eb 6a 7a 4d fe 23 [ ]*cltnl %r6,-5555\(%r7\)
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.*: eb 62 7a 4d fe 23 [ ]*clth %r6,-5555\(%r7\)
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.*: eb 62 7a 4d fe 23 [ ]*clth %r6,-5555\(%r7\)
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.*: eb 64 7a 4d fe 23 [ ]*cltl %r6,-5555\(%r7\)
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.*: eb 64 7a 4d fe 23 [ ]*cltl %r6,-5555\(%r7\)
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.*: eb 66 7a 4d fe 23 [ ]*cltne %r6,-5555\(%r7\)
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.*: eb 66 7a 4d fe 23 [ ]*cltne %r6,-5555\(%r7\)
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.*: eb 68 7a 4d fe 23 [ ]*clte %r6,-5555\(%r7\)
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.*: eb 68 7a 4d fe 23 [ ]*clte %r6,-5555\(%r7\)
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.*: eb 6a 7a 4d fe 23 [ ]*cltnl %r6,-5555\(%r7\)
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.*: eb 6a 7a 4d fe 23 [ ]*cltnl %r6,-5555\(%r7\)
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.*: eb 6c 7a 4d fe 23 [ ]*cltnh %r6,-5555\(%r7\)
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.*: eb 6c 7a 4d fe 23 [ ]*cltnh %r6,-5555\(%r7\)
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.*: eb 6a 7a 4d fe 2b [ ]*clgtnl %r6,-5555\(%r7\)
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.*: eb 62 7a 4d fe 2b [ ]*clgth %r6,-5555\(%r7\)
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.*: eb 62 7a 4d fe 2b [ ]*clgth %r6,-5555\(%r7\)
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.*: eb 64 7a 4d fe 2b [ ]*clgtl %r6,-5555\(%r7\)
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.*: eb 64 7a 4d fe 2b [ ]*clgtl %r6,-5555\(%r7\)
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.*: eb 66 7a 4d fe 2b [ ]*clgtne %r6,-5555\(%r7\)
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.*: eb 66 7a 4d fe 2b [ ]*clgtne %r6,-5555\(%r7\)
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.*: eb 68 7a 4d fe 2b [ ]*clgte %r6,-5555\(%r7\)
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.*: eb 68 7a 4d fe 2b [ ]*clgte %r6,-5555\(%r7\)
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.*: eb 6a 7a 4d fe 2b [ ]*clgtnl %r6,-5555\(%r7\)
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.*: eb 6a 7a 4d fe 2b [ ]*clgtnl %r6,-5555\(%r7\)
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.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
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.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
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.*: ec 67 0c 0d 0e 59 [ ]*risbgn %r6,%r7,12,13,14
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.*: ed 0f 8f a0 6d aa [ ]*cdzt %f6,4000\(16,%r8\),13
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.*: ed 21 8f a0 4d ab [ ]*cxzt %f4,4000\(34,%r8\),13
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.*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13
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.*: ed 21 8f a0 4d a9 [ ]*czxt %f4,4000\(34,%r8\),13
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.*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12
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.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9
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.*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1
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.*: c5 a0 06 00 00 06 [ ]*bprp 10,11e <bar>,11e <bar>
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.*: c5 a0 00 00 00 00 [ ]*bprp 10,118 <foo\+0x118>,118 <foo\+0x118>
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[ ]*119: R_390_PLT12DBL bar\+0x1
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[ ]*11b: R_390_PLT24DBL bar\+0x3
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.* <bar>:
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.*: 07 07 [ ]*nopr %r7
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