Alan Modra 9d4f36166d sim regen
This regenerates sim files.

Tested with the following tools from a recent binutils build in
sim-site-config.exp, plus a few cross compilers.

set AS_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/gas/as-new"
set LD_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_AARCH64 "aarch64-linux-gnu-gcc"
set AS_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/gas/as-new"
set LD_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/ld/ld-new"
set CC_FOR_TARGET_ARM "arm-linux-gnueabi-gcc"
set AS_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/gas/as-new"
set LD_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/ld/ld-new"
set CC_FOR_TARGET_AVR ""
set AS_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/gas/as-new"
set LD_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/ld/ld-new"
set CC_FOR_TARGET_BFIN ""
set AS_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/gas/as-new"
set LD_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/ld/ld-new"
set CC_FOR_TARGET_BPF ""
set AS_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/gas/as-new"
set LD_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/ld/ld-new"
set CC_FOR_TARGET_CR16 ""
set AS_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/gas/as-new"
set LD_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/ld/ld-new"
set CC_FOR_TARGET_CRIS ""
set AS_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/gas/as-new"
set LD_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/ld/ld-new"
set CC_FOR_TARGET_D10V ""
set AS_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/gas/as-new"
set LD_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/ld/ld-new"
set CC_FOR_TARGET_FRV ""
set AS_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/gas/as-new"
set LD_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/ld/ld-new"
set CC_FOR_TARGET_FT32 ""
set AS_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/gas/as-new"
set LD_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/ld/ld-new"
set CC_FOR_TARGET_H8300 ""
set AS_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/gas/as-new"
set LD_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/ld/ld-new"
set CC_FOR_TARGET_IQ2000 ""
set AS_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/gas/as-new"
set LD_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_LM32 ""
set AS_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/gas/as-new"
set LD_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/ld/ld-new"
set CC_FOR_TARGET_M32C ""
set AS_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/gas/as-new"
set LD_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/ld/ld-new"
set CC_FOR_TARGET_M32R ""
set AS_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/gas/as-new"
set LD_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/ld/ld-new"
set CC_FOR_TARGET_M68HC11 ""
set AS_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/gas/as-new"
set LD_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/ld/ld-new"
set CC_FOR_TARGET_MCORE ""
set AS_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MICROBLAZE "microblaze-linux-gnu-gcc"
set AS_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MIPS "mips-linux-gnu-gcc"
set AS_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/gas/as-new"
set LD_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/ld/ld-new"
set CC_FOR_TARGET_MN10300 ""
set AS_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/gas/as-new"
set LD_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/ld/ld-new"
set CC_FOR_TARGET_MOXIE ""
set AS_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/gas/as-new"
set LD_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/ld/ld-new"
set CC_FOR_TARGET_MSP430 ""
set AS_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/gas/as-new"
set LD_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_OR1K ""
set AS_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/gas/as-new"
set LD_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_PPC "powerpc-linux-gnu-gcc"
set AS_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/gas/as-new"
set LD_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/ld/ld-new"
set CC_FOR_TARGET_PRU ""
set AS_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/gas/as-new"
set LD_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/ld/ld-new"
set CC_FOR_TARGET_RISCV ""
set AS_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/gas/as-new"
set LD_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/ld/ld-new"
set CC_FOR_TARGET_RL78 ""
set AS_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/gas/as-new"
set LD_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/ld/ld-new"
set CC_FOR_TARGET_RX ""
set AS_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/gas/as-new"
set LD_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/ld/ld-new"
set CC_FOR_TARGET_SH ""
set AS_FOR_TARGET_ERC32 ""
set LD_FOR_TARGET_ERC32 ""
set CC_FOR_TARGET_ERC32 ""
set AS_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/gas/as-new"
set LD_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/ld/ld-new"
set CC_FOR_TARGET_V850 ""

Results both before and after were:
FAIL: crisv10 mem1.ms (execution)
FAIL: crisv10 mem2.ms (execution)
FAIL: crisv32 mem1.ms (execution)
FAIL: crisv32 mem2.ms (execution)
FAIL: microblaze fail.s (execution)
FAIL: microblaze pass.s (execution)
expected passes            5288
unexpected failures        6
expected failures          3
untested testcases         373
unsupported tests          14
2023-08-19 12:41:32 +09:30

1177 lines
33 KiB
C

/* Simulator model support for lm32bf.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#define WANT_CPU lm32bf
#define WANT_CPU_LM32BF
#include "sim-main.h"
/* The profiling data is recorded here, but is accessed via the profiling
mechanism. After all, this is information for profiling. */
#if WITH_PROFILE_MODEL_P
/* Model handlers for each insn. */
static int
model_lm32_add (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_addi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_and (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_andi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_andhii (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_b (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_bi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_be (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_bg (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_bge (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_bgeu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_bgu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_bne (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_call (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_calli (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpe (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpei (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpg (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpgi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpge (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpgei (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpgeu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpgeui (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpgu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpgui (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpne (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_cmpnei (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_divu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_lb (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_lbu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_lh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_lhu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_lw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_modu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_mul (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_muli (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_nor (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_nori (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_or (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_ori (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_orhii (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_rcsr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_rcsr.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sb (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sextb (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sexth (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sl (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sli (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sri (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sru (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_srui (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sub (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_sw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_user (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_wcsr (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_wcsr.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_xor (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_xori (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_xnor (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_xnori (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_andi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_break (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_lm32_scall (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
/* We assume UNIT_NONE == 0 because the tables don't always terminate
entries with it. */
/* Model timing data for `lm32'. */
static const INSN_TIMING lm32_timing[] = {
{ LM32BF_INSN_X_INVALID, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_X_AFTER, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_X_BEFORE, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_X_CHAIN, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_X_BEGIN, 0, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_ADD, model_lm32_add, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_ADDI, model_lm32_addi, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_AND, model_lm32_and, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_ANDI, model_lm32_andi, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_ANDHII, model_lm32_andhii, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_B, model_lm32_b, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BI, model_lm32_bi, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BE, model_lm32_be, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BG, model_lm32_bg, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BGE, model_lm32_bge, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BGEU, model_lm32_bgeu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BGU, model_lm32_bgu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BNE, model_lm32_bne, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CALL, model_lm32_call, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CALLI, model_lm32_calli, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPE, model_lm32_cmpe, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPEI, model_lm32_cmpei, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPG, model_lm32_cmpg, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPGI, model_lm32_cmpgi, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPGE, model_lm32_cmpge, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPGEI, model_lm32_cmpgei, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPGEU, model_lm32_cmpgeu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPGEUI, model_lm32_cmpgeui, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPGU, model_lm32_cmpgu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPGUI, model_lm32_cmpgui, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPNE, model_lm32_cmpne, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_CMPNEI, model_lm32_cmpnei, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_DIVU, model_lm32_divu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_LB, model_lm32_lb, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_LBU, model_lm32_lbu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_LH, model_lm32_lh, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_LHU, model_lm32_lhu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_LW, model_lm32_lw, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_MODU, model_lm32_modu, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_MUL, model_lm32_mul, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_MULI, model_lm32_muli, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_NOR, model_lm32_nor, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_NORI, model_lm32_nori, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_OR, model_lm32_or, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_ORI, model_lm32_ori, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_ORHII, model_lm32_orhii, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_RCSR, model_lm32_rcsr, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SB, model_lm32_sb, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SEXTB, model_lm32_sextb, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SEXTH, model_lm32_sexth, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SH, model_lm32_sh, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SL, model_lm32_sl, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SLI, model_lm32_sli, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SR, model_lm32_sr, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SRI, model_lm32_sri, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SRU, model_lm32_sru, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SRUI, model_lm32_srui, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SUB, model_lm32_sub, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SW, model_lm32_sw, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_USER, model_lm32_user, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_WCSR, model_lm32_wcsr, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_XOR, model_lm32_xor, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_XORI, model_lm32_xori, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_XNOR, model_lm32_xnor, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_XNORI, model_lm32_xnori, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_BREAK, model_lm32_break, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
{ LM32BF_INSN_SCALL, model_lm32_scall, { { (int) UNIT_LM32_U_EXEC, 1, 1 } } },
};
#endif /* WITH_PROFILE_MODEL_P */
static void
lm32_model_init (SIM_CPU *cpu)
{
CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_LM32_DATA));
}
#if WITH_PROFILE_MODEL_P
#define TIMING_DATA(td) td
#else
#define TIMING_DATA(td) 0
#endif
static const SIM_MODEL lm32_models[] =
{
{ "lm32", & lm32_mach, MODEL_LM32, TIMING_DATA (& lm32_timing[0]), lm32_model_init },
{ 0 }
};
/* The properties of this cpu's implementation. */
static const SIM_MACH_IMP_PROPERTIES lm32bf_imp_properties =
{
sizeof (SIM_CPU),
#if WITH_SCACHE
sizeof (SCACHE)
#else
0
#endif
};
static void
lm32bf_prepare_run (SIM_CPU *cpu)
{
if (CPU_IDESC (cpu) == NULL)
lm32bf_init_idesc_table (cpu);
}
static const CGEN_INSN *
lm32bf_get_idata (SIM_CPU *cpu, int inum)
{
return CPU_IDESC (cpu) [inum].idata;
}
static void
lm32_init_cpu (SIM_CPU *cpu)
{
CPU_REG_FETCH (cpu) = lm32bf_fetch_register;
CPU_REG_STORE (cpu) = lm32bf_store_register;
CPU_PC_FETCH (cpu) = lm32bf_h_pc_get;
CPU_PC_STORE (cpu) = lm32bf_h_pc_set;
CPU_GET_IDATA (cpu) = lm32bf_get_idata;
CPU_MAX_INSNS (cpu) = LM32BF_INSN__MAX;
CPU_INSN_NAME (cpu) = cgen_insn_name;
CPU_FULL_ENGINE_FN (cpu) = lm32bf_engine_run_full;
#if WITH_FAST
CPU_FAST_ENGINE_FN (cpu) = lm32bf_engine_run_fast;
#else
CPU_FAST_ENGINE_FN (cpu) = lm32bf_engine_run_full;
#endif
}
const SIM_MACH lm32_mach =
{
"lm32", "lm32", MACH_LM32,
32, 32, & lm32_models[0], & lm32bf_imp_properties,
lm32_init_cpu,
lm32bf_prepare_run
};