Jaydeep Patil
1c37b30945
sim/riscv: fix JALR instruction simulation ...
Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written
before using it to calculate destination address.
This commit also improves testutils.inc for riscv; make use of
pushsection and popsection when adding things to .data, and setup the
%gp global pointer register within the 'start' macro.
Approved-By: Andrew Burgess <aburgess@redhat.com>
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1c37b30945