cfb8c0921c
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo . (ALL_MACHINES_CFILES): Add cpu-epiphany.c . (BFD32_BACKENDS): Add elf32-epiphany.lo . (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c . * Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate. * archures.c (bfd_arch_epiphany): Add. (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. (bfd_epiphany_arch): Declare. (bfd_archures_list): Add &bfd_epiphany_arch. * config.bfd (epiphany-*-elf): New target case. * configure.in (bfd_elf32_epiphany_vec): New target vector case. * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. * targets.c (bfd_elf32_epiphany_vec): Declare. (_bfd_target_vector): Add bfd_elf32_epiphany_vec. * po/SRC-POTFILES.in, po/bfd.pot: Regenerate. * cpu-epiphany.c, elf32-epiphany.c: New files. binutils: * readelf.c (include "elf/epiphany.h") (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY. (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise. (is_16bit_abs_reloc, is_none_reloc): Likewise. * po/binutils.pot: Regenerate. cpu: * cpu/epiphany.cpu, cpu/epiphany.opc: New files. gas: * NEWS: Mention addition of Adapteva Epiphany support. * config/tc-epiphany.c, config/tc-epiphany.h: New files. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c . (TARGET_CPU_HFILES): Add config/tc-epiphany.h . * Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate. * configure.in: Also set using_cgen for epiphany. * configure.tgt: Handle epiphany. * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi . * doc/all.texi: Set EPIPHANY. * doc/as.texinfo: Add EPIPHANY-specific text. * doc/c-epiphany.texi: New file. * po/gas.pot: Regenerate. gas/testsuite: * gas/epiphany: New directory. include: * dis-asm.h (print_insn_epiphany): Declare. * elf/epiphany.h: New file. * elf/common.h (EM_ADAPTEVA_EPIPHANY): Define. ld: * NEWS: Mention addition of Adapteva Epiphany support. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c . (eelf32epiphany.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Handle epiphany-*-elf. * po/ld.pot: Regenerate. * testsuite/ld-srec/srec.exp: xfail epiphany. * emulparams/elf32epiphany.sh: New file. opcodes: * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . (CLEANFILES): Add stamp-epiphany. (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. (stamp-epiphany): New rule. * Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate. * configure.in: Handle bfd_epiphany_arch. * disassemble.c (ARCH_epiphany): Define. (disassembler): Handle bfd_arch_epiphany. * epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files. * epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise. * epiphany-opc.h: Likewise.
222 lines
5.4 KiB
Makefile
222 lines
5.4 KiB
Makefile
#as:
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#objdump: -dr
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#name: sample
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.*\.o: file format elf32-epiphany
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Disassembly of section \.text:
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00000000 \<beq\>:
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\.\.\.
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00000002 \<bne\>:
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2: ff10 bne 0 \<beq\>
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00000004 \<bgtu\>:
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4: fe20 bgtu 0 \<beq\>
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00000006 \<bgteu\>:
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6: fd30 bgteu 0 \<beq\>
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00000008 \<blteu\>:
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8: fc40 blteu 0 \<beq\>
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0000000a \<bltu\>:
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a: fb50 bltu 0 \<beq\>
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0000000c \<bgt\>:
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c: fa60 bgt 0 \<beq\>
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0000000e \<bgte\>:
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e: f970 bgte 0 \<beq\>
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00000010 \<blt\>:
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10: f880 blt 0 \<beq\>
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00000012 \<blte\>:
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12: f790 blte 0 \<beq\>
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00000014 \<bbeq\>:
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14: f6a0 bbeq 0 \<beq\>
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00000016 \<bbne\>:
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16: f5b0 bbne 0 \<beq\>
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00000018 \<bblt\>:
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18: f4c0 bblt 0 \<beq\>
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0000001a \<b\>:
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1a: f3e0 b 0 \<beq\>
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0000001c \<bl\>:
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1c: f2f0 bl 0 \<beq\>
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0000001e \<jr\>:
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1e: 0542 jr r1
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20: 1d4f 0c02 jr r31
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00000024 \<jalr\>:
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24: 0552 jalr r1
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26: 1d5f 0c02 jalr r31
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0000002a \<add\>:
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2a: 299a add r1,r2,r3
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2c: 051f 920a add.l r32,r33,r34
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30: 2993 add r1,r2,3
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32: 681b 2002 add fp,r2,16
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00000036 \<sub\>:
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36: 29ba sub r1,r2,r3
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38: 053f 920a sub.l r32,r33,r34
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3c: 29b3 sub r1,r2,3
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3e: 683b 2002 sub fp,r2,16
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00000042 \<asr\>:
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42: 29ea asr r1,r2,r3
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44: 056f 920a asr.l r32,r33,r34
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48: 286e asr r1,r2,0x3
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4a: 6a0f 200e asr.l fp,r2,0x10
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0000004e \<lsr\>:
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4e: 29ca lsr r1,r2,r3
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50: 054f 920a lsr.l r32,r33,r34
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54: 2866 lsr r1,r2,0x3
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56: 6a0f 2006 lsr.l fp,r2,0x10
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0000005a \<lsl\>:
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5a: 29aa lsl r1,r2,r3
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5c: 052f 920a lsl.l r32,r33,r34
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60: 2876 lsl r1,r2,0x3
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62: 6a1f 2006 lsl.l fp,r2,0x10
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00000066 \<orr\>:
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66: 29fa orr r1,r2,r3
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68: 72ff 248a orr.l fp,ip,sp
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0000006c \<and\>:
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6c: 29da and r1,r2,r3
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6e: 72df 248a and.l fp,ip,sp
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00000072 \<eor\>:
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72: 298a eor r1,r2,r3
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74: 728f 248a eor.l fp,ip,sp
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78: 0584 ldrb r0,\[r1,0x3\]
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7a: 478c 201f ldrb.l sl,\[r1,\+0xff\]
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7e: 0501 ldrb r0,\[r1,r2\]
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80: 0589 0080 ldrb.l r0,\[r1,\+fp\]
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84: 0d05 ldrb r0,\[r3\],r2
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86: 528d 2480 ldrb.l sl,\[ip\],\+sp
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8a: 05a4 ldrh r0,\[r1,0x3\]
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8c: 47ac 201f ldrh.l sl,\[r1,\+0xff\]
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90: 0521 ldrh r0,\[r1,r2\]
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92: 05a9 0080 ldrh.l r0,\[r1,\+fp\]
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96: 0d25 ldrh r0,\[r3\],r2
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98: 52ad 2480 ldrh.l sl,\[ip\],\+sp
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9c: 05c4 ldr r0,\[r1,0x3\]
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9e: 47cc 201f ldr.l sl,\[r1,\+0xff\]
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a2: 0541 ldr r0,\[r1,r2\]
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a4: 05c9 0080 ldr.l r0,\[r1,\+fp\]
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a8: 0d45 ldr r0,\[r3\],r2
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aa: 52cd 2480 ldr.l sl,\[ip\],\+sp
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ae: 05e4 ldrd r0,\[r1,0x3\]
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b0: 47ec 201f ldrd.l sl,\[r1,\+0xff\]
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b4: 0561 ldrd r0,\[r1,r2\]
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b6: 05e9 0080 ldrd.l r0,\[r1,\+fp\]
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ba: 0d65 ldrd r0,\[r3\],r2
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bc: 52ed 2480 ldrd.l sl,\[ip\],\+sp
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c0: 0594 strb r0,\[r1,0x3\]
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c2: 479c 201f strb.l sl,\[r1,\+0xff\]
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c6: 0511 strb r0,\[r1,r2\]
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c8: 0599 0080 strb.l r0,\[r1,\+fp\]
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cc: 0d15 strb r0,\[r3\],r2
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ce: 529d 2480 strb.l sl,\[ip\],\+sp
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d2: 05b4 strh r0,\[r1,0x3\]
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d4: 47bc 201f strh.l sl,\[r1,\+0xff\]
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d8: 0531 strh r0,\[r1,r2\]
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da: 05b9 0080 strh.l r0,\[r1,\+fp\]
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de: 0d35 strh r0,\[r3\],r2
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e0: 52bd 2480 strh.l sl,\[ip\],\+sp
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e4: 05d4 str r0,\[r1,0x3\]
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e6: 47dc 201f str.l sl,\[r1,\+0xff\]
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ea: 0551 str r0,\[r1,r2\]
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ec: 05d9 0080 str.l r0,\[r1,\+fp\]
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f0: 0d55 str r0,\[r3\],r2
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f2: 52dd 2480 str.l sl,\[ip\],\+sp
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f6: 05f4 strd r0,\[r1,0x3\]
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f8: 47fc 201f strd.l sl,\[r1,\+0xff\]
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fc: 0571 strd r0,\[r1,r2\]
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fe: 05f9 0080 strd.l r0,\[r1,\+fp\]
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102: 0d75 strd r0,\[r3\],r2
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104: 52fd 2480 strd.l sl,\[ip\],\+sp
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00000108 \<mov\>:
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108: dfe3 mov r6,0xff
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10a: ffeb 6ff2 mov r31,0xffff
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10e: 004b 0102 mov r0,0x1002
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112: 2802 moveq r1,r2
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114: 700f 2402 moveq.l fp,ip
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118: 2812 movne r1,r2
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11a: 701f 2402 movne.l fp,ip
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11e: 2822 movgtu r1,r2
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120: 702f 2402 movgtu.l fp,ip
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124: 2832 movgteu r1,r2
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126: 703f 2402 movgteu.l fp,ip
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12a: 2842 movlteu r1,r2
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12c: 704f 2402 movlteu.l fp,ip
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130: 2852 movltu r1,r2
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132: 705f 2402 movltu.l fp,ip
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136: 2862 movgt r1,r2
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138: 706f 2402 movgt.l fp,ip
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13c: 2872 movgte r1,r2
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13e: 707f 2402 movgte.l fp,ip
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142: 2882 movlt r1,r2
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144: 708f 2402 movlt.l fp,ip
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148: 2892 movlte r1,r2
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14a: 709f 2402 movlte.l fp,ip
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14e: 28a2 movbeq r1,r2
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150: 70af 2402 movbeq.l fp,ip
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154: 28b2 movbne r1,r2
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156: 70bf 2402 movbne.l fp,ip
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15a: 28c2 movblt r1,r2
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15c: 70cf 2402 movblt.l fp,ip
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160: 28d2 movblte r1,r2
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162: 70df 2402 movblte.l fp,ip
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166: 28e2 mov r1,r2
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168: 70ef 2402 mov.l fp,ip
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0000016c \<nop\>:
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16c: 01a2 nop
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0000016e \<idle\>:
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16e: 01b2 idle
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00000170 \<bkpt\>:
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170: 01c2 bkpt
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00000172 \<fadd\>:
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172: 2987 fadd r1,r2,r3
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174: 728f 2487 fadd.l fp,ip,sp
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00000178 \<fsub\>:
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178: 2997 fsub r1,r2,r3
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17a: 729f 2487 fsub.l fp,ip,sp
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0000017e \<fmul\>:
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17e: 29a7 fmul r1,r2,r3
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180: 72af 2487 fmul.l fp,ip,sp
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00000184 \<fmadd\>:
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184: 29b7 fmadd r1,r2,r3
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186: 72bf 2487 fmadd.l fp,ip,sp
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0000018a \<fmsub\>:
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18a: 29c7 fmsub r1,r2,r3
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18c: 72cf 2487 fmsub.l fp,ip,sp
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190: 2102 movts config,r1
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192: e50f 6002 movts.l status,r31
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196: 251f 0402 movfs.l r1,imask
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19a: e91f 6002 movfs.l r31,pc
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0000019e \<trap\>:
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19e: 03e2 trap 0x0
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1a0: 01d2 rti
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