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bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.
69 lines
1.9 KiB
Plaintext
69 lines
1.9 KiB
Plaintext
# This shell script emits a C file. -*- C -*-
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# Copyright 2004, 2006, 2007, 2008, 2016 Free Software Foundation, Inc.
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#
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# This file is part of the GNU Binutils.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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# MA 02110-1301, USA.
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fragment <<EOF
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#include "ldmain.h"
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#include "ldctor.h"
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#include "elf/riscv.h"
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#include "elfxx-riscv.h"
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static void
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riscv_elf_before_allocation (void)
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{
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gld${EMULATION_NAME}_before_allocation ();
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if (link_info.discard == discard_sec_merge)
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link_info.discard = discard_l;
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/* We always need at least some relaxation to handle code alignment. */
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if (RELAXATION_DISABLED_BY_USER)
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TARGET_ENABLE_RELAXATION;
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else
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ENABLE_RELAXATION;
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link_info.relax_pass = 2;
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}
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static void
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gld${EMULATION_NAME}_after_allocation (void)
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{
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int need_layout = 0;
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/* Don't attempt to discard unused .eh_frame sections until the final link,
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as we can't reliably tell if they're used until after relaxation. */
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if (!bfd_link_relocatable (&link_info))
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{
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need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
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if (need_layout < 0)
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{
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einfo ("%X%P: .eh_frame/.stab edit: %E\n");
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return;
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}
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}
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gld${EMULATION_NAME}_map_segments (need_layout);
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}
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EOF
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LDEMUL_BEFORE_ALLOCATION=riscv_elf_before_allocation
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LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
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