ae296cc452
The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.
206 lines
6.8 KiB
Makefile
206 lines
6.8 KiB
Makefile
#as:
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#objdump: -dr
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#skip: loongarch32-*-*
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.*: file format .*
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Disassembly of section .text:
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0+ <.L1>:
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0: 00150004 move \$a0, \$zero
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4: 02bffc04 li.w \$a0, -1
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8: 00150004 move \$a0, \$zero
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c: 02bffc04 li.w \$a0, -1
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10: 1a000004 pcalau12i \$a0, 0
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10: R_LARCH_GOT_PC_HI20 .L1
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10: R_LARCH_RELAX \*ABS\*
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14: 28c00084 ld.d \$a0, \$a0, 0
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14: R_LARCH_GOT_PC_LO12 .L1
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14: R_LARCH_RELAX \*ABS\*
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18: 1a000004 pcalau12i \$a0, 0
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18: R_LARCH_GOT_PC_HI20 .L1
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18: R_LARCH_RELAX \*ABS\*
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1c: 28c00084 ld.d \$a0, \$a0, 0
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1c: R_LARCH_GOT_PC_LO12 .L1
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1c: R_LARCH_RELAX \*ABS\*
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20: 1a000004 pcalau12i \$a0, 0
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20: R_LARCH_GOT_PC_HI20 .L1
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20: R_LARCH_RELAX \*ABS\*
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24: 02c00005 li.d \$a1, 0
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24: R_LARCH_GOT_PC_LO12 .L1
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24: R_LARCH_RELAX \*ABS\*
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28: 16000005 lu32i.d \$a1, 0
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28: R_LARCH_GOT64_PC_LO20 .L1
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2c: 030000a5 lu52i.d \$a1, \$a1, 0
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2c: R_LARCH_GOT64_PC_HI12 .L1
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30: 380c1484 ldx.d \$a0, \$a0, \$a1
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34: 1a000004 pcalau12i \$a0, 0
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34: R_LARCH_GOT_PC_HI20 .L1
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34: R_LARCH_RELAX \*ABS\*
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38: 28c00084 ld.d \$a0, \$a0, 0
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38: R_LARCH_GOT_PC_LO12 .L1
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38: R_LARCH_RELAX \*ABS\*
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3c: 1a000004 pcalau12i \$a0, 0
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3c: R_LARCH_GOT_PC_HI20 .L1
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3c: R_LARCH_RELAX \*ABS\*
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40: 02c00005 li.d \$a1, 0
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40: R_LARCH_GOT_PC_LO12 .L1
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40: R_LARCH_RELAX \*ABS\*
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44: 16000005 lu32i.d \$a1, 0
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44: R_LARCH_GOT64_PC_LO20 .L1
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48: 030000a5 lu52i.d \$a1, \$a1, 0
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48: R_LARCH_GOT64_PC_HI12 .L1
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4c: 380c1484 ldx.d \$a0, \$a0, \$a1
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50: 1a000004 pcalau12i \$a0, 0
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50: R_LARCH_GOT_PC_HI20 .L1
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50: R_LARCH_RELAX \*ABS\*
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54: 28c00084 ld.d \$a0, \$a0, 0
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54: R_LARCH_GOT_PC_LO12 .L1
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54: R_LARCH_RELAX \*ABS\*
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58: 1a000004 pcalau12i \$a0, 0
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58: R_LARCH_GOT_PC_HI20 .L1
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58: R_LARCH_RELAX \*ABS\*
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5c: 02c00005 li.d \$a1, 0
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5c: R_LARCH_GOT_PC_LO12 .L1
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5c: R_LARCH_RELAX \*ABS\*
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60: 16000005 lu32i.d \$a1, 0
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60: R_LARCH_GOT64_PC_LO20 .L1
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64: 030000a5 lu52i.d \$a1, \$a1, 0
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64: R_LARCH_GOT64_PC_HI12 .L1
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68: 380c1484 ldx.d \$a0, \$a0, \$a1
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6c: 1a000004 pcalau12i \$a0, 0
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6c: R_LARCH_PCALA_HI20 .L1
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6c: R_LARCH_RELAX \*ABS\*
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70: 02c00084 addi.d \$a0, \$a0, 0
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70: R_LARCH_PCALA_LO12 .L1
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70: R_LARCH_RELAX \*ABS\*
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74: 1a000004 pcalau12i \$a0, 0
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74: R_LARCH_PCALA_HI20 .L1
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74: R_LARCH_RELAX \*ABS\*
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78: 02c00005 li.d \$a1, 0
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78: R_LARCH_PCALA_LO12 .L1
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78: R_LARCH_RELAX \*ABS\*
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7c: 16000005 lu32i.d \$a1, 0
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7c: R_LARCH_PCALA64_LO20 .L1
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80: 030000a5 lu52i.d \$a1, \$a1, 0
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80: R_LARCH_PCALA64_HI12 .L1
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84: 00109484 add.d \$a0, \$a0, \$a1
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88: 1a000004 pcalau12i \$a0, 0
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88: R_LARCH_PCALA_HI20 .L1
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88: R_LARCH_RELAX \*ABS\*
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8c: 02c00084 addi.d \$a0, \$a0, 0
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8c: R_LARCH_PCALA_LO12 .L1
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8c: R_LARCH_RELAX \*ABS\*
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90: 1a000004 pcalau12i \$a0, 0
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90: R_LARCH_PCALA_HI20 .L1
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90: R_LARCH_RELAX \*ABS\*
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94: 02c00005 li.d \$a1, 0
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94: R_LARCH_PCALA_LO12 .L1
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94: R_LARCH_RELAX \*ABS\*
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98: 16000005 lu32i.d \$a1, 0
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98: R_LARCH_PCALA64_LO20 .L1
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9c: 030000a5 lu52i.d \$a1, \$a1, 0
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9c: R_LARCH_PCALA64_HI12 .L1
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a0: 00109484 add.d \$a0, \$a0, \$a1
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a4: 14000004 lu12i.w \$a0, 0
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a4: R_LARCH_MARK_LA \*ABS\*
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a4: R_LARCH_ABS_HI20 .L1
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a8: 03800084 ori \$a0, \$a0, 0x0
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a8: R_LARCH_ABS_LO12 .L1
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ac: 16000004 lu32i.d \$a0, 0
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ac: R_LARCH_ABS64_LO20 .L1
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b0: 03000084 lu52i.d \$a0, \$a0, 0
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b0: R_LARCH_ABS64_HI12 .L1
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b4: 1a000004 pcalau12i \$a0, 0
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b4: R_LARCH_PCALA_HI20 .L1
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b4: R_LARCH_RELAX \*ABS\*
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b8: 02c00084 addi.d \$a0, \$a0, 0
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b8: R_LARCH_PCALA_LO12 .L1
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b8: R_LARCH_RELAX \*ABS\*
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bc: 1a000004 pcalau12i \$a0, 0
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bc: R_LARCH_PCALA_HI20 .L1
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bc: R_LARCH_RELAX \*ABS\*
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c0: 02c00084 addi.d \$a0, \$a0, 0
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c0: R_LARCH_PCALA_LO12 .L1
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c0: R_LARCH_RELAX \*ABS\*
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c4: 1a000004 pcalau12i \$a0, 0
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c4: R_LARCH_PCALA_HI20 .L1
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c4: R_LARCH_RELAX \*ABS\*
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c8: 02c00005 li.d \$a1, 0
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c8: R_LARCH_PCALA_LO12 .L1
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c8: R_LARCH_RELAX \*ABS\*
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cc: 16000005 lu32i.d \$a1, 0
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cc: R_LARCH_PCALA64_LO20 .L1
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d0: 030000a5 lu52i.d \$a1, \$a1, 0
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d0: R_LARCH_PCALA64_HI12 .L1
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d4: 00109484 add.d \$a0, \$a0, \$a1
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d8: 1a000004 pcalau12i \$a0, 0
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d8: R_LARCH_GOT_PC_HI20 .L1
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d8: R_LARCH_RELAX \*ABS\*
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dc: 28c00084 ld.d \$a0, \$a0, 0
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dc: R_LARCH_GOT_PC_LO12 .L1
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dc: R_LARCH_RELAX \*ABS\*
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e0: 1a000004 pcalau12i \$a0, 0
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e0: R_LARCH_GOT_PC_HI20 .L1
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e0: R_LARCH_RELAX \*ABS\*
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e4: 02c00005 li.d \$a1, 0
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e4: R_LARCH_GOT_PC_LO12 .L1
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e4: R_LARCH_RELAX \*ABS\*
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e8: 16000005 lu32i.d \$a1, 0
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e8: R_LARCH_GOT64_PC_LO20 .L1
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ec: 030000a5 lu52i.d \$a1, \$a1, 0
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ec: R_LARCH_GOT64_PC_HI12 .L1
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f0: 380c1484 ldx.d \$a0, \$a0, \$a1
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f4: 14000004 lu12i.w \$a0, 0
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f4: R_LARCH_TLS_LE_HI20 TLS1
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f8: 03800084 ori \$a0, \$a0, 0x0
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f8: R_LARCH_TLS_LE_LO12 TLS1
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fc: 1a000004 pcalau12i \$a0, 0
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fc: R_LARCH_TLS_IE_PC_HI20 TLS1
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100: 28c00084 ld.d \$a0, \$a0, 0
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100: R_LARCH_TLS_IE_PC_LO12 TLS1
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104: 1a000004 pcalau12i \$a0, 0
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104: R_LARCH_TLS_IE_PC_HI20 TLS1
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108: 02c00005 li.d \$a1, 0
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108: R_LARCH_TLS_IE_PC_LO12 TLS1
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10c: 16000005 lu32i.d \$a1, 0
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10c: R_LARCH_TLS_IE64_PC_LO20 TLS1
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110: 030000a5 lu52i.d \$a1, \$a1, 0
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110: R_LARCH_TLS_IE64_PC_HI12 TLS1
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114: 380c1484 ldx.d \$a0, \$a0, \$a1
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118: 1a000004 pcalau12i \$a0, 0
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118: R_LARCH_TLS_LD_PC_HI20 TLS1
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118: R_LARCH_RELAX \*ABS\*
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11c: 02c00084 addi.d \$a0, \$a0, 0
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11c: R_LARCH_GOT_PC_LO12 TLS1
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11c: R_LARCH_RELAX \*ABS\*
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120: 1a000004 pcalau12i \$a0, 0
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120: R_LARCH_TLS_LD_PC_HI20 TLS1
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120: R_LARCH_RELAX \*ABS\*
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124: 02c00005 li.d \$a1, 0
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124: R_LARCH_GOT_PC_LO12 TLS1
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124: R_LARCH_RELAX \*ABS\*
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128: 16000005 lu32i.d \$a1, 0
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128: R_LARCH_GOT64_PC_LO20 TLS1
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12c: 030000a5 lu52i.d \$a1, \$a1, 0
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12c: R_LARCH_GOT64_PC_HI12 TLS1
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130: 00109484 add.d \$a0, \$a0, \$a1
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134: 1a000004 pcalau12i \$a0, 0
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134: R_LARCH_TLS_GD_PC_HI20 TLS1
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134: R_LARCH_RELAX \*ABS\*
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138: 02c00084 addi.d \$a0, \$a0, 0
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138: R_LARCH_GOT_PC_LO12 TLS1
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138: R_LARCH_RELAX \*ABS\*
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13c: 1a000004 pcalau12i \$a0, 0
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13c: R_LARCH_TLS_GD_PC_HI20 TLS1
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13c: R_LARCH_RELAX \*ABS\*
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140: 02c00005 li.d \$a1, 0
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140: R_LARCH_GOT_PC_LO12 TLS1
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140: R_LARCH_RELAX \*ABS\*
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144: 16000005 lu32i.d \$a1, 0
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144: R_LARCH_GOT64_PC_LO20 TLS1
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148: 030000a5 lu52i.d \$a1, \$a1, 0
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148: R_LARCH_GOT64_PC_HI12 TLS1
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14c: 00109484 add.d \$a0, \$a0, \$a1
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