binutils-gdb/sim/example-synacor
Mike Frysinger eac2fbdc4b sim: common: move libcommon.a objects to sources
This simplifies the build logic and avoids an Automake bug where the
common_libcommon_a_OBJECTS variable isn't set in the arch libsim.a
DEPENDENCIES for targets that, alphabetically, come before "common".
We aren't affected by that bug with the current code, but as we move
things out of SIM_ALL_RECURSIVE_DEPS and rely on finer dependencies,
we will trip over it.
2023-01-14 20:48:49 -05:00
..

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.