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GDB has required GNU make for quite some time, and this patch applies this approach to the sim as well. Requiring GNU make means that automatic dependency tracking can be simple and reliable, and it also makes other refactorings simpler. sim/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * m4/sim_ac_common.m4 (SIM_AC_COMMON): Don't check for make. sim/aarch64/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/arm/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/avr/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/bfin/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/common/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * Make-common.in: Require GNU make. sim/cr16/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/cris/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/d10v/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/erc32/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/example-synacor/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/frv/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/ft32/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/h8300/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/iq2000/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/lm32/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/m32c/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/m32r/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/m68hc11/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/mcore/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/microblaze/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/mips/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/mn10300/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/moxie/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/msp430/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/or1k/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/pru/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/riscv/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/rl78/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/rx/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/sh/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild. sim/v850/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure: Rebuild.
= OVERVIEW = The Synacor Challenge is a fun programming exercise with a number of puzzles built into it. You can find more details about it here: https://challenge.synacor.com/ The first puzzle is writing an interpreter for their custom ISA. This is a simulator for that custom CPU. The CPU is quite basic: it's 16-bit with only 8 registers and a limited set of instructions. This means the port will never grow new features. See README.arch-spec for more details. Implementing it here ends up being quite useful: it acts as a simple constrained "real world" example for people who want to implement a new simulator for their own architecture. We demonstrate all the basic fundamentals (registers, memory, branches, and tracing) that all ports should have.