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arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes

Browse Source 
These newly updated tests were rewritten by Andrea. Some of them
needed further manual fixing as follows:

* The #shift immediate value not in the check-function-bodies as expected
* The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
  this case the test rewritten from the ACLE had the lsr+and pattern,
  but the compiler was able to optimise to ubfx. Hence I've changed the
  test to now match on ubfx.
* Added a separate test to check shift on constants being optimised to
  movs.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
	* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
	* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
	* gcc.target/arm/mve/mve_const_shifts.c: New test.
This commit is contained in:
Stam Markianos-Wright 2023-04-27 15:55:24 +01:00
parent f9b84a1651
commit def680b503
23 changed files with 81 additions and 128 deletions
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2
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
View File

@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int32_t

2
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
View File

@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int64_t

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
View File

@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@ -21,18 +21,6 @@ foo (uint32_t value)
return uqshl (value, 1);
}
/*
**foo1:
** ...
** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** ...
*/
uint32_t
foo1 ()
{
return uqshl (1, 1);
}
#ifdef __cplusplus
}
#endif

14
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
View File

@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@ -21,18 +21,6 @@ foo (uint64_t value)
return uqshll (value, 1);
}
/*
**foo1:
** ...
** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** ...
*/
uint64_t
foo1 ()
{
return uqshll (1, 1);
}
#ifdef __cplusplus
}
#endif

4
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
View File

@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@ -24,7 +24,7 @@ foo (uint32_t value)
/*
**foo1:
** ...
** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t

4
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
View File

@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@ -24,7 +24,7 @@ foo (uint64_t value)
/*
**foo1:
** ...
** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
View File

@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
View File

@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
View File

@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
View File

@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
View File

@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
View File

@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
View File

@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
View File

@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
View File

@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
View File

@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
View File

@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
View File

@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
View File

@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
View File

@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
View File

@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t

8
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
View File

@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
** ...
** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t

41
gcc/testsuite/gcc.target/arm/mve/mve_const_shifts.c Normal file
View File

@ -0,0 +1,41 @@
/* { dg-require-effective-target arm_v8_1m_mve_ok } */
/* { dg-add-options arm_v8_1m_mve } */
/* { dg-additional-options "-O2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "arm_mve.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
**foo11:
** ...
** movs r0, #2
** ...
*/
uint32_t
foo11 ()
{
return uqshl (1, 1);
}
/*
**foo12:
** ...
** movs r0, #2
** movs r1, #0
** ...
*/
uint64_t
foo12 ()
{
return uqshll (1, 1);
}
#ifdef __cplusplus
}
#endif
/* { dg-final { scan-assembler-not "__ARM_undef" } } */