Revert "[compiler-rt][RISCV] Implement __init_riscv_feature_bits (#85790)"
This reverts commit a41a4ac78294c728fb70a51623c602ea7f3e308a.
This commit is contained in:
Piyou Chen
Tobias Hieta
parent
03ae9f9fc6
commit
b14801954e
@ -739,7 +739,6 @@ endif()
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set(powerpc64le_SOURCES ${powerpc64_SOURCES})
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set(riscv_SOURCES
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riscv/feature_bits.c
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riscv/fp_mode.c
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riscv/save.S
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riscv/restore.S
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@ -1,298 +0,0 @@
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//=== feature_bits.c - Update RISC-V Feature Bits Structure -*- C -*-=========//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#define RISCV_FEATURE_BITS_LENGTH 1
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struct {
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unsigned length;
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unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
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} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
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#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
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struct {
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unsigned vendorID;
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unsigned length;
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unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
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} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
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// NOTE: Should sync-up with RISCVFeatures.td
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// TODO: Maybe generate a header from tablegen then include it.
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#define A_GROUPID 0
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#define A_BITMASK (1ULL << 0)
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#define C_GROUPID 0
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#define C_BITMASK (1ULL << 2)
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#define D_GROUPID 0
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#define D_BITMASK (1ULL << 3)
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#define F_GROUPID 0
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#define F_BITMASK (1ULL << 5)
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#define I_GROUPID 0
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#define I_BITMASK (1ULL << 8)
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#define M_GROUPID 0
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#define M_BITMASK (1ULL << 12)
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#define V_GROUPID 0
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#define V_BITMASK (1ULL << 21)
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#define ZACAS_GROUPID 0
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#define ZACAS_BITMASK (1ULL << 26)
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#define ZBA_GROUPID 0
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#define ZBA_BITMASK (1ULL << 27)
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#define ZBB_GROUPID 0
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#define ZBB_BITMASK (1ULL << 28)
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#define ZBC_GROUPID 0
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#define ZBC_BITMASK (1ULL << 29)
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#define ZBKB_GROUPID 0
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#define ZBKB_BITMASK (1ULL << 30)
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#define ZBKC_GROUPID 0
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#define ZBKC_BITMASK (1ULL << 31)
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#define ZBKX_GROUPID 0
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#define ZBKX_BITMASK (1ULL << 32)
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#define ZBS_GROUPID 0
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#define ZBS_BITMASK (1ULL << 33)
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#define ZFA_GROUPID 0
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#define ZFA_BITMASK (1ULL << 34)
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#define ZFH_GROUPID 0
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#define ZFH_BITMASK (1ULL << 35)
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#define ZFHMIN_GROUPID 0
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#define ZFHMIN_BITMASK (1ULL << 36)
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#define ZICBOZ_GROUPID 0
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#define ZICBOZ_BITMASK (1ULL << 37)
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#define ZICOND_GROUPID 0
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#define ZICOND_BITMASK (1ULL << 38)
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#define ZIHINTNTL_GROUPID 0
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#define ZIHINTNTL_BITMASK (1ULL << 39)
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#define ZIHINTPAUSE_GROUPID 0
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#define ZIHINTPAUSE_BITMASK (1ULL << 40)
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#define ZKND_GROUPID 0
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#define ZKND_BITMASK (1ULL << 41)
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#define ZKNE_GROUPID 0
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#define ZKNE_BITMASK (1ULL << 42)
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#define ZKNH_GROUPID 0
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#define ZKNH_BITMASK (1ULL << 43)
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#define ZKSED_GROUPID 0
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#define ZKSED_BITMASK (1ULL << 44)
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#define ZKSH_GROUPID 0
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#define ZKSH_BITMASK (1ULL << 45)
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#define ZKT_GROUPID 0
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#define ZKT_BITMASK (1ULL << 46)
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#define ZTSO_GROUPID 0
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#define ZTSO_BITMASK (1ULL << 47)
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#define ZVBB_GROUPID 0
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#define ZVBB_BITMASK (1ULL << 48)
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#define ZVBC_GROUPID 0
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#define ZVBC_BITMASK (1ULL << 49)
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#define ZVFH_GROUPID 0
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#define ZVFH_BITMASK (1ULL << 50)
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#define ZVFHMIN_GROUPID 0
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#define ZVFHMIN_BITMASK (1ULL << 51)
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#define ZVKB_GROUPID 0
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#define ZVKB_BITMASK (1ULL << 52)
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#define ZVKG_GROUPID 0
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#define ZVKG_BITMASK (1ULL << 53)
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#define ZVKNED_GROUPID 0
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#define ZVKNED_BITMASK (1ULL << 54)
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#define ZVKNHA_GROUPID 0
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#define ZVKNHA_BITMASK (1ULL << 55)
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#define ZVKNHB_GROUPID 0
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#define ZVKNHB_BITMASK (1ULL << 56)
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#define ZVKSED_GROUPID 0
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#define ZVKSED_BITMASK (1ULL << 57)
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#define ZVKSH_GROUPID 0
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#define ZVKSH_BITMASK (1ULL << 58)
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#define ZVKT_GROUPID 0
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#define ZVKT_BITMASK (1ULL << 59)
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#if defined(__linux__)
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static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
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long arg4, long arg5) {
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register long a7 __asm__("a7") = number;
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register long a0 __asm__("a0") = arg1;
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register long a1 __asm__("a1") = arg2;
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register long a2 __asm__("a2") = arg3;
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register long a3 __asm__("a3") = arg4;
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register long a4 __asm__("a4") = arg5;
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__asm__ __volatile__("ecall\n\t"
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: "=r"(a0)
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: "r"(a7), "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
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: "memory");
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return a0;
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}
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#define RISCV_HWPROBE_KEY_MVENDORID 0
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#define RISCV_HWPROBE_KEY_MARCHID 1
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#define RISCV_HWPROBE_KEY_MIMPID 2
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#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
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#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1ULL << 0)
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#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
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#define RISCV_HWPROBE_IMA_FD (1ULL << 0)
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#define RISCV_HWPROBE_IMA_C (1ULL << 1)
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#define RISCV_HWPROBE_IMA_V (1ULL << 2)
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#define RISCV_HWPROBE_EXT_ZBA (1ULL << 3)
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#define RISCV_HWPROBE_EXT_ZBB (1ULL << 4)
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#define RISCV_HWPROBE_EXT_ZBS (1ULL << 5)
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#define RISCV_HWPROBE_EXT_ZICBOZ (1ULL << 6)
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#define RISCV_HWPROBE_EXT_ZBC (1ULL << 7)
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#define RISCV_HWPROBE_EXT_ZBKB (1ULL << 8)
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#define RISCV_HWPROBE_EXT_ZBKC (1ULL << 9)
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#define RISCV_HWPROBE_EXT_ZBKX (1ULL << 10)
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#define RISCV_HWPROBE_EXT_ZKND (1ULL << 11)
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#define RISCV_HWPROBE_EXT_ZKNE (1ULL << 12)
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#define RISCV_HWPROBE_EXT_ZKNH (1ULL << 13)
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#define RISCV_HWPROBE_EXT_ZKSED (1ULL << 14)
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#define RISCV_HWPROBE_EXT_ZKSH (1ULL << 15)
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#define RISCV_HWPROBE_EXT_ZKT (1ULL << 16)
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#define RISCV_HWPROBE_EXT_ZVBB (1ULL << 17)
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#define RISCV_HWPROBE_EXT_ZVBC (1ULL << 18)
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#define RISCV_HWPROBE_EXT_ZVKB (1ULL << 19)
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#define RISCV_HWPROBE_EXT_ZVKG (1ULL << 20)
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#define RISCV_HWPROBE_EXT_ZVKNED (1ULL << 21)
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#define RISCV_HWPROBE_EXT_ZVKNHA (1ULL << 22)
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#define RISCV_HWPROBE_EXT_ZVKNHB (1ULL << 23)
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#define RISCV_HWPROBE_EXT_ZVKSED (1ULL << 24)
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#define RISCV_HWPROBE_EXT_ZVKSH (1ULL << 25)
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#define RISCV_HWPROBE_EXT_ZVKT (1ULL << 26)
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#define RISCV_HWPROBE_EXT_ZFH (1ULL << 27)
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#define RISCV_HWPROBE_EXT_ZFHMIN (1ULL << 28)
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#define RISCV_HWPROBE_EXT_ZIHINTNTL (1ULL << 29)
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#define RISCV_HWPROBE_EXT_ZVFH (1ULL << 30)
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#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
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#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
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#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
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#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
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#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
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#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
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#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
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#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
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#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
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#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
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#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
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/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
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struct riscv_hwprobe {
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long long key;
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unsigned long long value;
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};
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#define __NR_riscv_hwprobe 258
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static long initHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
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return syscall_impl_5_args(__NR_riscv_hwprobe, (long)Hwprobes, len, 0, 0, 0);
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}
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#define SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(EXTNAME) \
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SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_EXT_##EXTNAME, EXTNAME)
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#define SET_SINGLE_IMAEXT_RISCV_FEATURE(HWPROBE_BITMASK, EXT) \
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SET_SINGLE_RISCV_FEATURE(IMAEXT0Value &HWPROBE_BITMASK, EXT)
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#define SET_SINGLE_RISCV_FEATURE(COND, EXT) \
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if (COND) { \
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SET_RISCV_FEATURE(EXT); \
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}
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#define SET_RISCV_FEATURE(EXT) features[EXT##_GROUPID] |= EXT##_BITMASK
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static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
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// Note: If a hwprobe key is unknown to the kernel, its key field
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// will be cleared to -1, and its value set to 0.
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// This unsets all extension bitmask bits.
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// Init vendor extension
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__riscv_vendor_feature_bits.length = 0;
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__riscv_vendor_feature_bits.vendorID = Hwprobes[2].value;
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// Init standard extension
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// TODO: Maybe Extension implied generate from tablegen?
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__riscv_feature_bits.length = RISCV_FEATURE_BITS_LENGTH;
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unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
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int i;
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for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
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features[i] = 0;
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// Check RISCV_HWPROBE_KEY_BASE_BEHAVIOR
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unsigned long long BaseValue = Hwprobes[0].value;
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if (BaseValue & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) {
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SET_RISCV_FEATURE(I);
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SET_RISCV_FEATURE(M);
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SET_RISCV_FEATURE(A);
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}
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// Check RISCV_HWPROBE_KEY_IMA_EXT_0
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unsigned long long IMAEXT0Value = Hwprobes[1].value;
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if (IMAEXT0Value & RISCV_HWPROBE_IMA_FD) {
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SET_RISCV_FEATURE(F);
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SET_RISCV_FEATURE(D);
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}
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SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_C, C);
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SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_V, V);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBA);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBB);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBS);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOZ);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBC);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKB);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKC);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKX);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKND);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNE);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNH);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSED);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSH);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKT);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBB);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBC);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKB);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKG);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNED);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHA);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHB);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSED);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSH);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKT);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFH);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFHMIN);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTNTL);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTPAUSE);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFH);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFHMIN);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFA);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZTSO);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZACAS);
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SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICOND);
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for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
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__riscv_feature_bits.features[i] = features[i];
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}
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#endif // defined(__linux__)
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static int FeaturesBitCached = 0;
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void __init_riscv_feature_bits() {
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if (FeaturesBitCached)
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return;
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#if defined(__linux__)
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struct riscv_hwprobe Hwprobes[] = {
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{RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0},
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{RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
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{RISCV_HWPROBE_KEY_MVENDORID, 0},
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};
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if (initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0])))
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return;
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initRISCVFeature(Hwprobes);
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#endif // defined(__linux__)
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FeaturesBitCached = 1;
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}
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