FastISel: Fix incorrectly using getPointerTy (#110465)
This was using the default address space instead of the correct one. Fixes #56055 Keep old method around for ABI compatibility on the release branch. (cherry picked from commit 81ba95cefe1b5a12f0a7d8e6a383bcce9e95b785)
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@ -275,7 +275,12 @@ public:
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/// This is a wrapper around getRegForValue that also takes care of
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/// truncating or sign-extending the given getelementptr index value.
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Register getRegForGEPIndex(const Value *Idx);
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Register getRegForGEPIndex(MVT PtrVT, const Value *Idx);
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/// Retained for ABI compatibility in release branch.
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Register getRegForGEPIndex(const Value *Idx) {
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return getRegForGEPIndex(TLI.getPointerTy(DL), Idx);
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}
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/// We're checking to see if we can fold \p LI into \p FoldInst. Note
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/// that we could have a sequence where multiple LLVM IR instructions are
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@ -380,14 +380,13 @@ void FastISel::updateValueMap(const Value *I, Register Reg, unsigned NumRegs) {
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}
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}
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Register FastISel::getRegForGEPIndex(const Value *Idx) {
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Register FastISel::getRegForGEPIndex(MVT PtrVT, const Value *Idx) {
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Register IdxN = getRegForValue(Idx);
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if (!IdxN)
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// Unhandled operand. Halt "fast" selection and bail.
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return Register();
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// If the index is smaller or larger than intptr_t, truncate or extend it.
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MVT PtrVT = TLI.getPointerTy(DL);
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EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
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if (IdxVT.bitsLT(PtrVT)) {
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IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
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@ -543,7 +542,8 @@ bool FastISel::selectGetElementPtr(const User *I) {
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uint64_t TotalOffs = 0;
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// FIXME: What's a good SWAG number for MaxOffs?
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uint64_t MaxOffs = 2048;
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MVT VT = TLI.getPointerTy(DL);
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MVT VT = TLI.getValueType(DL, I->getType()).getSimpleVT();
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for (gep_type_iterator GTI = gep_type_begin(I), E = gep_type_end(I);
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GTI != E; ++GTI) {
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const Value *Idx = GTI.getOperand();
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@ -584,7 +584,7 @@ bool FastISel::selectGetElementPtr(const User *I) {
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// N = N + Idx * ElementSize;
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uint64_t ElementSize = GTI.getSequentialElementStride(DL);
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Register IdxN = getRegForGEPIndex(Idx);
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Register IdxN = getRegForGEPIndex(VT, Idx);
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if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
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return false;
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@ -902,6 +902,8 @@ redo_gep:
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uint64_t Disp = (int32_t)AM.Disp;
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unsigned IndexReg = AM.IndexReg;
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unsigned Scale = AM.Scale;
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MVT PtrVT = TLI.getValueType(DL, U->getType()).getSimpleVT();
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gep_type_iterator GTI = gep_type_begin(U);
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// Iterate through the indices, folding what we can. Constants can be
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// folded, and one dynamic index can be handled, if the scale is supported.
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@ -937,7 +939,7 @@ redo_gep:
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(S == 1 || S == 2 || S == 4 || S == 8)) {
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// Scaled-index addressing.
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Scale = S;
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IndexReg = getRegForGEPIndex(Op);
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IndexReg = getRegForGEPIndex(PtrVT, Op);
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if (IndexReg == 0)
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return false;
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break;
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81
llvm/test/CodeGen/X86/issue56055.ll
Normal file
81
llvm/test/CodeGen/X86/issue56055.ll
Normal file
@ -0,0 +1,81 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -fast-isel < %s | FileCheck -check-prefixes=CHECK,FASTISEL %s
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; RUN: llc < %s | FileCheck -check-prefixes=CHECK,SDAG %s
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target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-windows-msvc"
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define void @issue56055(ptr addrspace(270) %ptr, ptr %out) {
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; CHECK-LABEL: issue56055:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addl $2, %ecx
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; CHECK-NEXT: movl %ecx, (%rdx)
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds i8, ptr addrspace(270) %ptr, i32 2
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store ptr addrspace(270) %add.ptr, ptr %out
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ret void
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}
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define void @issue56055_vector(<2 x ptr addrspace(270)> %ptr, ptr %out) {
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; CHECK-LABEL: issue56055_vector:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa (%rcx), %xmm0
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; CHECK-NEXT: paddd __xmm@00000000000000000000000200000002(%rip), %xmm0
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; CHECK-NEXT: movq %xmm0, (%rdx)
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds i8, <2 x ptr addrspace(270)> %ptr, <2 x i32> <i32 2, i32 2>
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store <2 x ptr addrspace(270)> %add.ptr, ptr %out
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ret void
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}
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define void @issue56055_small_idx(ptr addrspace(270) %ptr, ptr %out, i16 %idx) {
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; CHECK-LABEL: issue56055_small_idx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movswl %r8w, %eax
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: movl %eax, (%rdx)
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds i8, ptr addrspace(270) %ptr, i16 %idx
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store ptr addrspace(270) %add.ptr, ptr %out
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ret void
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}
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define void @issue56055_small_idx_vector(<2 x ptr addrspace(270)> %ptr, ptr %out, <2 x i16> %idx) {
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; CHECK-LABEL: issue56055_small_idx_vector:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,0,2,1,4,5,6,7]
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; CHECK-NEXT: psrad $16, %xmm0
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; CHECK-NEXT: paddd (%rcx), %xmm0
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; CHECK-NEXT: movq %xmm0, (%rdx)
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds i8, <2 x ptr addrspace(270)> %ptr, <2 x i16> %idx
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store <2 x ptr addrspace(270)> %add.ptr, ptr %out
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ret void
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}
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define void @issue56055_large_idx(ptr addrspace(270) %ptr, ptr %out, i64 %idx) {
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; CHECK-LABEL: issue56055_large_idx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addl %ecx, %r8d
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; CHECK-NEXT: movl %r8d, (%rdx)
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds i8, ptr addrspace(270) %ptr, i64 %idx
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store ptr addrspace(270) %add.ptr, ptr %out
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ret void
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}
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define void @issue56055_large_idx_vector(<2 x ptr addrspace(270)> %ptr, ptr %out, <2 x i64> %idx) {
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; CHECK-LABEL: issue56055_large_idx_vector:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = mem[0,2,2,3]
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; CHECK-NEXT: paddd (%rcx), %xmm0
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; CHECK-NEXT: movq %xmm0, (%rdx)
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; CHECK-NEXT: retq
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%add.ptr = getelementptr inbounds i8, <2 x ptr addrspace(270)> %ptr, <2 x i64> %idx
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store <2 x ptr addrspace(270)> %add.ptr, ptr %out
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ret void
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; FASTISEL: {{.*}}
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; SDAG: {{.*}}
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