Enable SHA-512 ARM acceleration when available.
This imports the changes to sha512-armv8.pl from upstream's af0fcf7b4668218b24d9250b95e0b96939ccb4d1. Tweaks needed: - Add an explicit .text because we put .LK$BITS in .rodata for XOM - .LK$bits and code are in separate sections, so use adrp/add instead of plain adr - Where glibc needs feature flags to *enable* pthread_rwlock, Apple interprets _XOPEN_SOURCE as a request to *disable* Apple extensions. Tighten the condition on the _XOPEN_SOURCE check. Added support for macOS and Linux, tested manually on an ARM Mac and a VM, respectively. Fuchsia and Windows do not currently have APIs to expose this bit, so I've left in TODOs. Benchmarks from an Apple M1 Max: Before: Did 4647000 SHA-512 (16 bytes) operations in 1000103us (74.3 MB/sec) Did 1614000 SHA-512 (256 bytes) operations in 1000379us (413.0 MB/sec) Did 439000 SHA-512 (1350 bytes) operations in 1001694us (591.6 MB/sec) Did 76000 SHA-512 (8192 bytes) operations in 1011821us (615.3 MB/sec) Did 39000 SHA-512 (16384 bytes) operations in 1024311us (623.8 MB/sec) After: Did 10369000 SHA-512 (16 bytes) operations in 1000088us (165.9 MB/sec) [+123.1%] Did 3650000 SHA-512 (256 bytes) operations in 1000079us (934.3 MB/sec) [+126.2%] Did 1029000 SHA-512 (1350 bytes) operations in 1000521us (1388.4 MB/sec) [+134.7%] Did 175000 SHA-512 (8192 bytes) operations in 1001874us (1430.9 MB/sec) [+132.5%] Did 89000 SHA-512 (16384 bytes) operations in 1010314us (1443.3 MB/sec) [+131.4%] (This doesn't seem to change the overall SHA-256 vs SHA-512 performance question on ARM, when hashing perf matters. SHA-256 on the same chip gets up to 2454.6 MB/s.) In terms of build coverage, for now, we'll have build coverage everywhere and test coverage on Chromium, which runs this code on macOS CI. We should request a macOS ARM64 bot for our standalone CI. Longer term, we need a QEMU-based builder to test various features. QEMU seems to have pretty good coverage of all this, which will at least give us Linux. I haven't added an OPENSSL_STATIC_ARMCAP_SHA512 for now. Instead, we just look at the standard __ARM_FEATURE_SHA512 define. Strangely, the corresponding -march tag is not sha512. Neither GCC and nor Clang have -march=armv8-a+sha512. Instead, -march=armv8-a+sha3 implies both __ARM_FEATURE_SHA3 and __ARM_FEATURE_SHA512! Yet everything else seems to describe the SHA512 extension as separate from SHA3. https://developer.arm.com/architectures/system-architectures/software-standards/acle Update-Note: Consumers with a different build setup may need to limit -D_XOPEN_SOURCE=700 to Linux or non-Apple platforms. Otherwise, <sys/types.h> won't define some typedef needed by <sys/sysctl.h>. If you see a build error about u_char, etc., being undefined in some system header, that is probably the cause. Change-Id: Ia213d3796b84c71b7966bb68e0aec92e5d7d26f0 Reviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/50807 Reviewed-by: Adam Langley <agl@google.com> Commit-Queue: David Benjamin <davidben@google.com>
This commit is contained in:
David Benjamin
Boringssl LUCI CQ
parent
af561c221d
commit
1e15682f1a
35
BUILDING.md
35
BUILDING.md
@ -163,22 +163,17 @@ BoringSSL maintainers if making use of it.
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don't have steps for assembling the assembly language source files, so they
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currently cannot be used to build BoringSSL.
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## Embedded ARM
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## ARM CPU Capabilities
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ARM, unlike Intel, does not have an instruction that allows applications to
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discover the capabilities of the processor. Instead, the capability information
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has to be provided by the operating system somehow.
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ARM, unlike Intel, does not have a userspace instruction that allows
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applications to discover the capabilities of the processor. Instead, the
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capability information has to be provided by a combination of compile-time
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information and the operating system.
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By default, on Linux-based systems, BoringSSL will try to use `getauxval` and
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`/proc` to discover the capabilities. But some environments don't support that
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sort of thing and, for them, it's possible to configure the CPU capabilities at
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compile time.
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On iOS or builds which define `OPENSSL_STATIC_ARMCAP`, features will be
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determined based on the `__ARM_NEON__` and `__ARM_FEATURE_CRYPTO` preprocessor
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symbols reported by the compiler. These values are usually controlled by the
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`-march` flag. You can also define any of the following to enable the
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corresponding ARM feature.
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BoringSSL determines capabilities at compile-time based on `__ARM_NEON__`,
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`__ARM_FEATURE_CRYPTO`, and other preprocessor symbols reported by the compiler.
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These values are usually controlled by the `-march` flag. You can also define
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any of the following to enable the corresponding ARM feature.
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* `OPENSSL_STATIC_ARMCAP_NEON`
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* `OPENSSL_STATIC_ARMCAP_AES`
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@ -186,8 +181,16 @@ corresponding ARM feature.
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* `OPENSSL_STATIC_ARMCAP_SHA256`
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* `OPENSSL_STATIC_ARMCAP_PMULL`
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Note that if a feature is enabled in this way, but not actually supported at
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run-time, BoringSSL will likely crash.
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The resulting binary will assume all such features are always present. This can
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reduce code size, by allowing the compiler to omit fallbacks. However, if the
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feature is not actually supported at runtime, BoringSSL will likely crash.
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BoringSSL will additionally query the operating system at runtime for additional
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features, e.g. with `getauxval` on Linux. This allows a single binary to use
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newer instructions when present, but still function on CPUs without them. But
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some environments don't support runtime queries. If building for those, define
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`OPENSSL_STATIC_ARMCAP` to limit BoringSSL to compile-time capabilities. If not
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defined, the target operating system must be known to BoringSSL.
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## Binary Size
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@ -257,8 +257,10 @@ if(CMAKE_COMPILER_IS_GNUCXX)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=c11")
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endif()
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# pthread_rwlock_t requires a feature flag.
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if(NOT WIN32)
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# pthread_rwlock_t on Linux requires a feature flag. However, it should not be
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# set on Apple platforms, where it instead disables APIs we use. See compat(5)
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# and sys/cdefs.h.
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if(NOT WIN32 AND NOT APPLE)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -D_XOPEN_SOURCE=700")
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endif()
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@ -263,6 +263,7 @@ add_library(
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cipher_extra/tls_cbc.c
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cmac/cmac.c
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conf/conf.c
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cpu-aarch64-apple.c
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cpu-aarch64-fuchsia.c
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cpu-aarch64-linux.c
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cpu-aarch64-win.c
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73
crypto/cpu-aarch64-apple.c
Normal file
73
crypto/cpu-aarch64-apple.c
Normal file
@ -0,0 +1,73 @@
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/* Copyright (c) 2021, Google Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
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#include <openssl/cpu.h>
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#if defined(OPENSSL_AARCH64) && defined(OPENSSL_APPLE) && \
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!defined(OPENSSL_STATIC_ARMCAP)
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#include <sys/sysctl.h>
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#include <sys/types.h>
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#include <openssl/arm_arch.h>
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#include "internal.h"
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extern uint32_t OPENSSL_armcap_P;
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static int has_hw_feature(const char *name) {
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int value;
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size_t len = sizeof(value);
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if (sysctlbyname(name, &value, &len, NULL, 0) != 0) {
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return 0;
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}
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if (len != sizeof(int)) {
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// This should not happen. All the values queried should be integer-valued.
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assert(0);
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return 0;
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}
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// Per sys/sysctl.h:
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//
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// Selectors that return errors are not support on the system. Supported
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// features will return 1 if they are recommended or 0 if they are supported
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// but are not expected to help performance. Future versions of these
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// selectors may return larger values as necessary so it is best to test for
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// non zero.
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return value != 0;
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}
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void OPENSSL_cpuid_setup(void) {
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// Apple ARM64 platforms have NEON and cryptography extensions available
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// statically, so we do not need to query them. In particular, there sometimes
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// are no sysctls corresponding to such features. See below.
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#if !defined(__ARM_NEON) || !defined(__ARM_FEATURE_CRYPTO)
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#error "NEON and crypto extensions should be statically available."
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#endif
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OPENSSL_armcap_P =
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ARMV7_NEON | ARMV8_AES | ARMV8_PMULL | ARMV8_SHA1 | ARMV8_SHA256;
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// macOS has sysctls named both like "hw.optional.arm.FEAT_SHA512" and like
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// "hw.optional.armv8_2_sha512". There does not appear to be documentation on
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// which to use. The "armv8_2_sha512" style omits statically-available
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// features, while the "FEAT_SHA512" style includes them. However, the
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// "FEAT_SHA512" style was added in macOS 12, so we use the older style for
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// better compatibility and handle static features above.
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if (has_hw_feature("hw.optional.armv8_2_sha512")) {
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OPENSSL_armcap_P |= ARMV8_SHA512;
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}
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}
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#endif // OPENSSL_AARCH64 && OPENSSL_APPLE && !OPENSSL_STATIC_ARMCAP
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@ -50,6 +50,9 @@ void OPENSSL_cpuid_setup(void) {
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if (hwcap & ZX_ARM64_FEATURE_ISA_SHA2) {
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OPENSSL_armcap_P |= ARMV8_SHA256;
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}
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// As of writing, Fuchsia does not have a flag for ARMv8.2 SHA-512
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// extensions. When it does, add it here. See
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// https://bugs.fuchsia.dev/p/fuchsia/issues/detail?id=90759.
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}
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#endif // OPENSSL_AARCH64 && !OPENSSL_STATIC_ARMCAP
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#endif // OPENSSL_AARCH64 && OPENSSL_FUCHSIA && !OPENSSL_STATIC_ARMCAP
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@ -36,6 +36,7 @@ void OPENSSL_cpuid_setup(void) {
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static const unsigned long kPMULL = 1 << 4;
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static const unsigned long kSHA1 = 1 << 5;
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static const unsigned long kSHA256 = 1 << 6;
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static const unsigned long kSHA512 = 1 << 21;
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if ((hwcap & kNEON) == 0) {
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// Matching OpenSSL, if NEON is missing, don't report other features
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@ -57,6 +58,9 @@ void OPENSSL_cpuid_setup(void) {
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if (hwcap & kSHA256) {
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OPENSSL_armcap_P |= ARMV8_SHA256;
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}
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if (hwcap & kSHA512) {
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OPENSSL_armcap_P |= ARMV8_SHA512;
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}
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}
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#endif // OPENSSL_AARCH64 && !OPENSSL_STATIC_ARMCAP
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#endif // OPENSSL_AARCH64 && OPENSSL_LINUX && !OPENSSL_STATIC_ARMCAP
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@ -36,6 +36,8 @@ void OPENSSL_cpuid_setup(void) {
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OPENSSL_armcap_P |= ARMV8_SHA1;
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OPENSSL_armcap_P |= ARMV8_SHA256;
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}
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// As of writing, Windows does not have a |PF_*| value for ARMv8.2 SHA-512
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// extensions. When it does, add it here.
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}
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#endif
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#endif // OPENSSL_AARCH64 && OPENSSL_WINDOWS && !OPENSSL_STATIC_ARMCAP
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@ -104,6 +104,9 @@ HIDDEN uint32_t OPENSSL_armcap_P =
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#endif
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#if defined(OPENSSL_STATIC_ARMCAP_PMULL) || defined(__ARM_FEATURE_CRYPTO)
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ARMV8_PMULL |
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#endif
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#if defined(__ARM_FEATURE_SHA512)
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ARMV8_SHA512 |
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#endif
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0;
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@ -185,8 +185,6 @@ $code.=<<___;
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.type $func,%function
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.align 6
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$func:
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___
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$code.=<<___ if ($SZ==4);
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AARCH64_VALID_CALL_TARGET
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#ifndef __KERNEL__
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#if __has_feature(hwaddress_sanitizer) && __clang_major__ >= 10
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@ -195,11 +193,17 @@ $code.=<<___ if ($SZ==4);
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adrp x16,:pg_hi21:OPENSSL_armcap_P
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#endif
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ldr w16,[x16,:lo12:OPENSSL_armcap_P]
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___
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$code.=<<___ if ($SZ==4);
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tst w16,#ARMV8_SHA256
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b.ne .Lv8_entry
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#endif
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___
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$code.=<<___ if ($SZ==8);
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tst w16,#ARMV8_SHA512
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b.ne .Lv8_entry
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___
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$code.=<<___;
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#endif
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AARCH64_SIGN_LINK_REGISTER
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stp x29,x30,[sp,#-128]!
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add x29,sp,#0
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@ -425,6 +429,110 @@ $code.=<<___;
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___
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}
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if ($SZ==8) {
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my $Ktbl="x3";
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my @H = map("v$_.16b",(0..4));
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my ($fg,$de,$m9_10)=map("v$_.16b",(5..7));
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my @MSG=map("v$_.16b",(16..23));
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my ($W0,$W1)=("v24.2d","v25.2d");
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my ($AB,$CD,$EF,$GH)=map("v$_.16b",(26..29));
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$code.=<<___;
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.text
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#ifndef __KERNEL__
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.type sha512_block_armv8,%function
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.align 6
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sha512_block_armv8:
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.Lv8_entry:
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stp x29,x30,[sp,#-16]!
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add x29,sp,#0
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ld1 {@MSG[0]-@MSG[3]},[$inp],#64 // load input
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ld1 {@MSG[4]-@MSG[7]},[$inp],#64
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ld1.64 {@H[0]-@H[3]},[$ctx] // load context
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adrp $Ktbl,:pg_hi21:.LK512
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add $Ktbl,$Ktbl,:lo12:.LK512
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rev64 @MSG[0],@MSG[0]
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rev64 @MSG[1],@MSG[1]
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rev64 @MSG[2],@MSG[2]
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rev64 @MSG[3],@MSG[3]
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rev64 @MSG[4],@MSG[4]
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rev64 @MSG[5],@MSG[5]
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rev64 @MSG[6],@MSG[6]
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rev64 @MSG[7],@MSG[7]
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b .Loop_hw
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.align 4
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.Loop_hw:
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ld1.64 {$W0},[$Ktbl],#16
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subs $num,$num,#1
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sub x4,$inp,#128
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orr $AB,@H[0],@H[0] // offload
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orr $CD,@H[1],@H[1]
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orr $EF,@H[2],@H[2]
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orr $GH,@H[3],@H[3]
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csel $inp,$inp,x4,ne // conditional rewind
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___
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for($i=0;$i<32;$i++) {
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$code.=<<___;
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add.i64 $W0,$W0,@MSG[0]
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ld1.64 {$W1},[$Ktbl],#16
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ext $W0,$W0,$W0,#8
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ext $fg,@H[2],@H[3],#8
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ext $de,@H[1],@H[2],#8
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add.i64 @H[3],@H[3],$W0 // "T1 + H + K512[i]"
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sha512su0 @MSG[0],@MSG[1]
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ext $m9_10,@MSG[4],@MSG[5],#8
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sha512h @H[3],$fg,$de
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sha512su1 @MSG[0],@MSG[7],$m9_10
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add.i64 @H[4],@H[1],@H[3] // "D + T1"
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sha512h2 @H[3],$H[1],@H[0]
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___
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($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
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@H = (@H[3],@H[0],@H[4],@H[2],@H[1]);
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}
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for(;$i<40;$i++) {
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$code.=<<___ if ($i<39);
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ld1.64 {$W1},[$Ktbl],#16
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___
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$code.=<<___ if ($i==39);
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sub $Ktbl,$Ktbl,#$rounds*$SZ // rewind
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___
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$code.=<<___;
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add.i64 $W0,$W0,@MSG[0]
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ld1 {@MSG[0]},[$inp],#16 // load next input
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ext $W0,$W0,$W0,#8
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ext $fg,@H[2],@H[3],#8
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ext $de,@H[1],@H[2],#8
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add.i64 @H[3],@H[3],$W0 // "T1 + H + K512[i]"
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sha512h @H[3],$fg,$de
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rev64 @MSG[0],@MSG[0]
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add.i64 @H[4],@H[1],@H[3] // "D + T1"
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sha512h2 @H[3],$H[1],@H[0]
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___
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($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
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@H = (@H[3],@H[0],@H[4],@H[2],@H[1]);
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}
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$code.=<<___;
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add.i64 @H[0],@H[0],$AB // accumulate
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add.i64 @H[1],@H[1],$CD
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add.i64 @H[2],@H[2],$EF
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add.i64 @H[3],@H[3],$GH
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cbnz $num,.Loop_hw
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st1.64 {@H[0]-@H[3]},[$ctx] // store context
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ldr x29,[sp],#16
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ret
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.size sha512_block_armv8,.-sha512_block_armv8
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#endif
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___
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}
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{ my %opcode = (
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"sha256h" => 0x5e004000, "sha256h2" => 0x5e005000,
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"sha256su0" => 0x5e282800, "sha256su1" => 0x5e006000 );
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@ -440,6 +548,21 @@ ___
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}
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}
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{ my %opcode = (
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"sha512h" => 0xce608000, "sha512h2" => 0xce608400,
|
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"sha512su0" => 0xcec08000, "sha512su1" => 0xce608800 );
|
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sub unsha512 {
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my ($mnemonic,$arg)=@_;
|
||||
|
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$arg =~ m/[qv]([0-9]+)[^,]*,\s*[qv]([0-9]+)[^,]*(?:,\s*[qv]([0-9]+))?/o
|
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&&
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sprintf ".inst\t0x%08x\t//%s %s",
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$opcode{$mnemonic}|$1|($2<<5)|($3<<16),
|
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$mnemonic,$arg;
|
||||
}
|
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}
|
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|
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open SELF,$0;
|
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while(<SELF>) {
|
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next if (/^#!/);
|
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@ -452,12 +575,15 @@ foreach(split("\n",$code)) {
|
||||
|
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s/\`([^\`]*)\`/eval($1)/ge;
|
||||
|
||||
s/\b(sha512\w+)\s+([qv].*)/unsha512($1,$2)/ge or
|
||||
s/\b(sha256\w+)\s+([qv].*)/unsha256($1,$2)/ge;
|
||||
|
||||
s/\bq([0-9]+)\b/v$1.16b/g; # old->new registers
|
||||
|
||||
s/\.[ui]?8(\s)/$1/;
|
||||
s/\.\w?64\b// and s/\.16b/\.2d/g or
|
||||
s/\.\w?32\b// and s/\.16b/\.4s/g;
|
||||
m/\bext\b/ and s/\.2d/\.16b/g or
|
||||
m/(ld|st)1[^\[]+\[0\]/ and s/\.4s/\.s/g;
|
||||
|
||||
print $_,"\n";
|
||||
|
||||
@ -117,6 +117,9 @@
|
||||
// ARMV8_PMULL indicates support for carryless multiplication.
|
||||
#define ARMV8_PMULL (1 << 5)
|
||||
|
||||
// ARMV8_SHA512 indicates support for hardware SHA-512 instructions.
|
||||
#define ARMV8_SHA512 (1 << 6)
|
||||
|
||||
#if defined(__ASSEMBLER__)
|
||||
|
||||
// Support macros for
|
||||
|
||||
@ -105,8 +105,9 @@ OPENSSL_INLINE const uint32_t *OPENSSL_ia32cap_get(void) {
|
||||
|
||||
#if defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64)
|
||||
|
||||
#if defined(OPENSSL_APPLE)
|
||||
// iOS builds use the static ARM configuration.
|
||||
#if defined(OPENSSL_APPLE) && defined(OPENSSL_ARM)
|
||||
// We do not detect any features at runtime for Apple's 32-bit ARM platforms. On
|
||||
// 64-bit ARM, we detect some post-ARMv8.0 features.
|
||||
#define OPENSSL_STATIC_ARMCAP
|
||||
#endif
|
||||
|
||||
|
||||
@ -89,9 +89,6 @@ posix_copts = [
|
||||
# ensure that binaries can be built with non-executable stack.
|
||||
"-Wa,--noexecstack",
|
||||
|
||||
# This is needed on Linux systems (at least) to get rwlock in pthread.
|
||||
"-D_XOPEN_SOURCE=700",
|
||||
|
||||
# This list of warnings should match those in the top-level CMakeLists.txt.
|
||||
"-Wall",
|
||||
"-Werror",
|
||||
@ -108,10 +105,17 @@ posix_copts = [
|
||||
# "-DOPENSSL_C11_ATOMIC",
|
||||
]
|
||||
|
||||
linux_copts = posix_copts + [
|
||||
# This is needed on Linux systems (at least) to get rwlock in pthread, but
|
||||
# it should not be set on Apple platforms, where it instead disables APIs
|
||||
# we use. See compat(5) and sys/cdefs.h.
|
||||
"-D_XOPEN_SOURCE=700",
|
||||
]
|
||||
|
||||
boringssl_copts = select({
|
||||
":linux_aarch64": posix_copts,
|
||||
":linux_ppc64le": posix_copts,
|
||||
":linux_x86_64": posix_copts,
|
||||
":linux_aarch64": linux_copts,
|
||||
":linux_ppc64le": linux_copts,
|
||||
":linux_x86_64": linux_copts,
|
||||
":mac_x86_64": posix_copts,
|
||||
":windows_x86_64": [
|
||||
"-DWIN32_LEAN_AND_MEAN",
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user