diff --git a/src/cpu/arm.rs b/src/cpu/arm.rs
index 63da6a6de..1e5e99795 100644
--- a/src/cpu/arm.rs
+++ b/src/cpu/arm.rs
@@ -17,6 +17,25 @@
     allow(dead_code)
 )]
 
+#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
+mod abi_assumptions {
+    // TODO: Support ARM64_32; see
+    // https://github.com/briansmith/ring/issues/1832#issuecomment-1892928147. This also requires
+    // replacing all `cfg(target_pointer_width)` logic for non-pointer/reference things
+    // (`N0`, `Limb`, `LimbMask`, `crypto_word_t` etc.).
+    #[cfg(target_arch = "aarch64")]
+    const _ASSUMED_POINTER_SIZE: usize = 8;
+    #[cfg(target_arch = "arm")]
+    const _ASSUMED_POINTER_SIZE: usize = 4;
+    const _ASSUMED_USIZE_SIZE: () = assert!(core::mem::size_of::<usize>() == _ASSUMED_POINTER_SIZE);
+    const _ASSUMED_REF_SIZE: () =
+        assert!(core::mem::size_of::<&'static u8>() == _ASSUMED_POINTER_SIZE);
+
+    // To support big-endian, we'd need to make several changes as described in
+    // https://github.com/briansmith/ring/issues/1832.
+    const _ASSUMED_ENDIANNESS: () = assert!(cfg!(target_endian = "little"));
+}
+
 // uclibc: When linked statically, uclibc doesn't provide getauxval.
 // When linked dynamically, recent versions do provide it, but we
 // want to support older versions too. Assume that if uclibc is being
diff --git a/src/cpu/intel.rs b/src/cpu/intel.rs
index 7d5aedffc..28546b4b0 100644
--- a/src/cpu/intel.rs
+++ b/src/cpu/intel.rs
@@ -17,6 +17,27 @@
     allow(dead_code)
 )]
 
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+mod abi_assumptions {
+    // TOOD: Support targets that do not have SSE and SSE2 enabled, such as
+    // x86_64-unknown-linux-none. See
+    // https://github.com/briansmith/ring/issues/1793#issuecomment-1793243725,
+    // https://github.com/briansmith/ring/issues/1832,
+    // https://github.com/briansmith/ring/issues/1833.
+    const _ASSUMES_SSE2: () =
+        assert!(cfg!(target_feature = "sse") && cfg!(target_feature = "sse2"));
+
+    #[cfg(target_arch = "x86_64")]
+    const _ASSUMED_POINTER_SIZE: usize = 8;
+    #[cfg(target_arch = "x86")]
+    const _ASSUMED_POINTER_SIZE: usize = 4;
+    const _ASSUMED_USIZE_SIZE: () = assert!(core::mem::size_of::<usize>() == _ASSUMED_POINTER_SIZE);
+    const _ASSUMED_REF_SIZE: () =
+        assert!(core::mem::size_of::<&'static u8>() == _ASSUMED_POINTER_SIZE);
+
+    const _ASSUMED_ENDIANNESS: () = assert!(cfg!(target_endian = "little"));
+}
+
 pub(crate) struct Feature {
     word: usize,
     mask: u32,