alnyan/rvx0
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3087975833e4d435f7b95dc7e56b4b3d705c068a
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alnyan 3087975833 Initial commit
2025-09-03 14:56:28 +03:00
firmware
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2025-09-03 14:56:28 +03:00
src
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tool
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.gitignore
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Makefile
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Description
Simple RISC-V (rv32i+Zicsr) core in SystemVerilog
84 KiB
Languages
SystemVerilog 90.5%
Assembly 4.1%
Rust 2.8%
Makefile 1.8%
Python 0.8%