alnyan/rvx0
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alnyan 97ae2dd172 Implement exception/fault encoder module
2025-09-05 09:02:18 +03:00
firmware
Add ecall/ebreak
2025-09-03 17:22:00 +03:00
src
Implement exception/fault encoder module
2025-09-05 09:02:18 +03:00
tool
Initial commit
2025-09-03 14:56:28 +03:00
.gitignore
Initial commit
2025-09-03 14:56:28 +03:00
Makefile
Implement exception/fault encoder module
2025-09-05 09:02:18 +03:00
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Description
Simple RISC-V (rv32i+Zicsr) core in SystemVerilog
84 KiB
Languages
SystemVerilog 90.5%
Assembly 4.1%
Rust 2.8%
Makefile 1.8%
Python 0.8%