alnyan/rvx0
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ee55a07e0a8590605ec092bafbe268d342d96d98
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alnyan ee55a07e0a Add ecall/ebreak
2025-09-03 17:22:00 +03:00
firmware
Add ecall/ebreak
2025-09-03 17:22:00 +03:00
src
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tool
Initial commit
2025-09-03 14:56:28 +03:00
.gitignore
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Makefile
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2025-09-03 17:22:00 +03:00
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Description
Simple RISC-V (rv32i+Zicsr) core in SystemVerilog
84 KiB
Languages
SystemVerilog 90.5%
Assembly 4.1%
Rust 2.8%
Makefile 1.8%
Python 0.8%