riscv: initial support for hifive unmatched
This commit is contained in:
@@ -0,0 +1,237 @@
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/dts-v1/;
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#define CLK_COREPLL 0
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#define CLK_DDRPLL 1
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#define CLK_GEMGXLPLL 2
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#define CLK_DVFSCOREPLL 3
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#define CLK_HFPCLKPLL 4
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#define CLK_CLTXPLL 5
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#define CLK_TLCLK 6
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#define CLK_PCLK 7
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#define CLK_PCIE_AUX 8
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740";
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model = "SiFive HiFive Unmatched";
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aliases {
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serial0 = "/soc/serial@10010000";
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serial1 = "/soc/serial@10011000";
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};
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chosen {
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stdout-path = "serial0";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu0: cpu@0 {
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compatible = "sifive,bullet0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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next-level-cache = <&ccache>;
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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device_type = "cpu";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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device_type = "cpu";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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device_type = "cpu";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu4: cpu@4 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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device_type = "cpu";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <40>;
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i-tlb-sets = <1>;
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i-tlb-size = <40>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&ccache>;
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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plic: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x00 0xc000000 0x00 0x4000000>;
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riscv,ndev = <69>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 0xffffffff>,
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<&cpu1_intc 0xffffffff>,
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<&cpu1_intc 0x09>,
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<&cpu2_intc 0xffffffff>,
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<&cpu2_intc 0x09>,
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<&cpu3_intc 0xffffffff>,
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<&cpu3_intc 0x09>,
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<&cpu4_intc 0xffffffff>,
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<&cpu4_intc 0x09>;
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};
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prci: clock-controller@10000000 {
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compatible = "sifive,fu740-c000-prci";
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reg = <0x00 0x10000000 0x00 0x1000>;
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clocks = <&clk_hfclk>, <&clk_rtcclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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uart0: serial@10010000 {
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compatible = "sifive,fu740-c000-uart", "sifive,uart0";
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reg = <0x00 0x10010000 0x00 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <39>;
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clocks = <&prci CLK_PCLK>;
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status = "okay";
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};
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uart1: serial@10011000 {
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compatible = "sifive,fu740-c000-uart", "sifive,uart0";
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reg = <0x00 0x10011000 0x00 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <40>;
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clocks = <&prci CLK_PCLK>;
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status = "disabled";
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};
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ccache: cache-controller@2010000 {
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compatible = "sifive,fu740-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <2048>;
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cache-size = <0x200000>;
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cache-unified;
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interrupt-parent = <&plic>;
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interrupts = <0x13>, <0x15>, <0x16>, <0x14>;
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reg = <0x00 0x2010000 0x00 0x1000>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00 0x80000000 0x04 0x00>;
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};
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clk_hfclk: hfclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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clock-output-names = "hfclk";
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};
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clk_rtcclk: rtcclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <1000000>;
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clock-output-names = "rtcclk";
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};
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};
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Binary file not shown.
@@ -0,0 +1,577 @@
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/dts-v1/;
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/ {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740";
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model = "SiFive HiFive Unmatched";
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aliases {
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serial0 = "/soc/serial@10010000";
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serial1 = "/soc/serial@10011000";
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ethernet0 = "/soc/ethernet@10090000";
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};
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chosen {
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stdout-path = "serial0";
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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timebase-frequency = <0xf4240>;
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cpu@0 {
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compatible = "sifive,bullet0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x80>;
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i-cache-size = <0x4000>;
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next-level-cache = <0x01>;
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reg = <0x00>;
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riscv,isa = "rv64imac";
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status = "disabled";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x02>;
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};
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};
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cpu@1 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x01>;
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reg = <0x01>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x03>;
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};
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};
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cpu@2 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x01>;
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reg = <0x02>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x04>;
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};
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};
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cpu@3 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x01>;
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reg = <0x03>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x05>;
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};
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};
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cpu@4 {
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compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x01>;
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d-tlb-size = <0x28>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x01>;
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i-tlb-size = <0x28>;
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mmu-type = "riscv,sv39";
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next-level-cache = <0x01>;
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reg = <0x04>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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interrupt-controller {
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#interrupt-cells = <0x01>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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phandle = <0x06>;
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};
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};
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};
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soc {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "simple-bus";
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ranges;
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interrupt-controller@c000000 {
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#interrupt-cells = <0x01>;
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#address-cells = <0x00>;
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x00 0xc000000 0x00 0x4000000>;
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riscv,ndev = <0x45>;
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interrupt-controller;
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interrupts-extended = <0x02 0xffffffff 0x03 0xffffffff 0x03 0x09 0x04 0xffffffff 0x04 0x09 0x05 0xffffffff 0x05 0x09 0x06 0xffffffff 0x06 0x09>;
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phandle = <0x09>;
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};
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prci: clock-controller@10000000 {
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compatible = "sifive,fu740-c000-prci";
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reg = <0x00 0x10000000 0x00 0x1000>;
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clocks = <&clk_hfclk>, <&clk_rtcclk>;
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#clock-cells = <0x01>;
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#reset-cells = <0x01>;
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};
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serial@10010000 {
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compatible = "sifive,fu740-c000-uart", "sifive,uart0";
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reg = <0x00 0x10010000 0x00 0x1000>;
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interrupt-parent = <0x09>;
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interrupts = <0x27>;
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clocks = <&prci 0x07>;
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status = "okay";
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};
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serial@10011000 {
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compatible = "sifive,fu740-c000-uart", "sifive,uart0";
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reg = <0x00 0x10011000 0x00 0x1000>;
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interrupt-parent = <0x09>;
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interrupts = <0x28>;
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clocks = <&prci 0x07>;
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status = "okay";
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};
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i2c@10030000 {
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compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
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reg = <0x00 0x10030000 0x00 0x1000>;
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interrupt-parent = <0x09>;
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interrupts = <0x34>;
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clocks = <&prci 0x07>;
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reg-shift = <0x02>;
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reg-io-width = <0x01>;
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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status = "okay";
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temperature-sensor@4c {
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compatible = "ti,tmp451";
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reg = <0x4c>;
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interrupt-parent = <0x0b>;
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interrupts = <0x06 0x08>;
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};
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pmic@58 {
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compatible = "dlg,da9063";
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reg = <0x58>;
|
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interrupt-parent = <0x0b>;
|
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interrupts = <0x01 0x08>;
|
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interrupt-controller;
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regulators {
|
||||
|
||||
bcore1 {
|
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regulator-min-microvolt = <0x100590>;
|
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regulator-max-microvolt = <0x100590>;
|
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regulator-min-microamp = <0x4c4b40>;
|
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regulator-max-microamp = <0x4c4b40>;
|
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regulator-always-on;
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};
|
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bcore2 {
|
||||
regulator-min-microvolt = <0x100590>;
|
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regulator-max-microvolt = <0x100590>;
|
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regulator-min-microamp = <0x4c4b40>;
|
||||
regulator-max-microamp = <0x4c4b40>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
bpro {
|
||||
regulator-min-microvolt = <0x1b7740>;
|
||||
regulator-max-microvolt = <0x1b7740>;
|
||||
regulator-min-microamp = <0x2625a0>;
|
||||
regulator-max-microamp = <0x2625a0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
bperi {
|
||||
regulator-min-microvolt = <0x100590>;
|
||||
regulator-max-microvolt = <0x100590>;
|
||||
regulator-min-microamp = <0x16e360>;
|
||||
regulator-max-microamp = <0x16e360>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
bmem {
|
||||
regulator-min-microvolt = <0x124f80>;
|
||||
regulator-max-microvolt = <0x124f80>;
|
||||
regulator-min-microamp = <0x2dc6c0>;
|
||||
regulator-max-microamp = <0x2dc6c0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
bio {
|
||||
regulator-min-microvolt = <0x124f80>;
|
||||
regulator-max-microvolt = <0x124f80>;
|
||||
regulator-min-microamp = <0x2dc6c0>;
|
||||
regulator-max-microamp = <0x2dc6c0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1 {
|
||||
regulator-min-microvolt = <0x1b7740>;
|
||||
regulator-max-microvolt = <0x1b7740>;
|
||||
regulator-min-microamp = <0x186a0>;
|
||||
regulator-max-microamp = <0x186a0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2 {
|
||||
regulator-min-microvolt = <0x1b7740>;
|
||||
regulator-max-microvolt = <0x1b7740>;
|
||||
regulator-min-microamp = <0x30d40>;
|
||||
regulator-max-microamp = <0x30d40>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3 {
|
||||
regulator-min-microvolt = <0x325aa0>;
|
||||
regulator-max-microvolt = <0x325aa0>;
|
||||
regulator-min-microamp = <0x30d40>;
|
||||
regulator-max-microamp = <0x30d40>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4 {
|
||||
regulator-min-microvolt = <0x2625a0>;
|
||||
regulator-max-microvolt = <0x2625a0>;
|
||||
regulator-min-microamp = <0x30d40>;
|
||||
regulator-max-microamp = <0x30d40>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5 {
|
||||
regulator-min-microvolt = <0x325aa0>;
|
||||
regulator-max-microvolt = <0x325aa0>;
|
||||
regulator-min-microamp = <0x186a0>;
|
||||
regulator-max-microamp = <0x186a0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6 {
|
||||
regulator-min-microvolt = <0x1b7740>;
|
||||
regulator-max-microvolt = <0x1b7740>;
|
||||
regulator-min-microamp = <0x30d40>;
|
||||
regulator-max-microamp = <0x30d40>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo7 {
|
||||
regulator-min-microvolt = <0x325aa0>;
|
||||
regulator-max-microvolt = <0x325aa0>;
|
||||
regulator-min-microamp = <0x30d40>;
|
||||
regulator-max-microamp = <0x30d40>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo8 {
|
||||
regulator-min-microvolt = <0x325aa0>;
|
||||
regulator-max-microvolt = <0x325aa0>;
|
||||
regulator-min-microamp = <0x30d40>;
|
||||
regulator-max-microamp = <0x30d40>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo9 {
|
||||
regulator-min-microvolt = <0x100590>;
|
||||
regulator-max-microvolt = <0x100590>;
|
||||
regulator-min-microamp = <0x30d40>;
|
||||
regulator-max-microamp = <0x30d40>;
|
||||
};
|
||||
|
||||
ldo10 {
|
||||
regulator-min-microvolt = <0xf4240>;
|
||||
regulator-max-microvolt = <0xf4240>;
|
||||
regulator-min-microamp = <0x493e0>;
|
||||
regulator-max-microamp = <0x493e0>;
|
||||
};
|
||||
|
||||
ldo11 {
|
||||
regulator-min-microvolt = <0x2625a0>;
|
||||
regulator-max-microvolt = <0x2625a0>;
|
||||
regulator-min-microamp = <0x493e0>;
|
||||
regulator-max-microamp = <0x493e0>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@10031000 {
|
||||
compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
|
||||
reg = <0x00 0x10031000 0x00 0x1000>;
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x35>;
|
||||
clocks = <&prci 0x07>;
|
||||
reg-shift = <0x02>;
|
||||
reg-io-width = <0x01>;
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@10040000 {
|
||||
compatible = "sifive,fu740-c000-spi", "sifive,spi0";
|
||||
reg = <0x00 0x10040000 0x00 0x1000 0x00 0x20000000 0x00 0x10000000>;
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x29>;
|
||||
clocks = <&prci 0x07>;
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "issi,is25wp256", "jedec,spi-nor";
|
||||
reg = <0x00>;
|
||||
spi-max-frequency = <0x2faf080>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <0x04>;
|
||||
spi-rx-bus-width = <0x04>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@10041000 {
|
||||
compatible = "sifive,fu740-c000-spi", "sifive,spi0";
|
||||
reg = <0x00 0x10041000 0x00 0x1000 0x00 0x30000000 0x00 0x10000000>;
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x2a>;
|
||||
clocks = <&prci 0x07>;
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@10050000 {
|
||||
compatible = "sifive,fu740-c000-spi", "sifive,spi0";
|
||||
reg = <0x00 0x10050000 0x00 0x1000>;
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x2b>;
|
||||
clocks = <&prci 0x07>;
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
status = "okay";
|
||||
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0x00>;
|
||||
spi-max-frequency = <0x1312d00>;
|
||||
voltage-ranges = <0xce4 0xce4>;
|
||||
disable-wp;
|
||||
};
|
||||
};
|
||||
|
||||
macb: ethernet@10090000 {
|
||||
compatible = "sifive,fu540-c000-gem";
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x37>;
|
||||
reg = <0x00 0x10090000 0x00 0x2000 0x00 0x100a0000 0x00 0x1000>;
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
clock-names = "pclk", "hclk";
|
||||
clocks = <&prci 0x02 &prci 0x02>;
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
status = "okay";
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <0x0c>;
|
||||
|
||||
ethernet-phy@0 {
|
||||
reg = <0x00>;
|
||||
phandle = <0x0c>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm@10020000 {
|
||||
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
|
||||
reg = <0x00 0x10020000 0x00 0x1000>;
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x2c 0x2d 0x2e 0x2f>;
|
||||
clocks = <&prci 0x07>;
|
||||
#pwm-cells = <0x03>;
|
||||
status = "okay";
|
||||
phandle = <0x0d>;
|
||||
};
|
||||
|
||||
pwm@10021000 {
|
||||
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
|
||||
reg = <0x00 0x10021000 0x00 0x1000>;
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x30 0x31 0x32 0x33>;
|
||||
clocks = <&prci 0x07>;
|
||||
#pwm-cells = <0x03>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cache-controller@2010000 {
|
||||
compatible = "sifive,fu740-c000-ccache", "cache";
|
||||
cache-block-size = <0x40>;
|
||||
cache-level = <0x02>;
|
||||
cache-sets = <0x800>;
|
||||
cache-size = <0x200000>;
|
||||
cache-unified;
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x13 0x15 0x16 0x14>;
|
||||
reg = <0x00 0x2010000 0x00 0x1000>;
|
||||
phandle = <0x01>;
|
||||
};
|
||||
|
||||
gpio@10060000 {
|
||||
compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
|
||||
interrupt-parent = <0x09>;
|
||||
interrupts = <0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26>;
|
||||
reg = <0x00 0x10060000 0x00 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x02>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x02>;
|
||||
clocks = <&prci 0x07>;
|
||||
status = "okay";
|
||||
phandle = <0x0b>;
|
||||
};
|
||||
|
||||
pcie@e00000000 {
|
||||
#address-cells = <0x03>;
|
||||
#interrupt-cells = <0x01>;
|
||||
#num-lanes = <0x08>;
|
||||
#size-cells = <0x02>;
|
||||
compatible = "sifive,fu740-pcie";
|
||||
reg = <0x0e 0x00 0x01 0x00 0x0d 0xf0000000 0x00 0x10000000 0x00 0x100d0000 0x00 0x1000>;
|
||||
reg-names = "dbi", "config", "mgmt";
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0x00 0x60080000 0x00 0x60080000 0x00 0x10000 0x82000000 0x00 0x60090000 0x00 0x60090000 0x00 0xff70000 0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0x1000000 0xc3000000 0x20 0x00 0x20 0x00 0x20 0x00>;
|
||||
num-lanes = <0x08>;
|
||||
interrupts = <0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>;
|
||||
interrupt-names = "msi", "inta", "intb", "intc", "intd";
|
||||
interrupt-parent = <0x09>;
|
||||
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
|
||||
interrupt-map = <0x00 0x00 0x00 0x01 0x09 0x39 0x00 0x00 0x00 0x02 0x09 0x3a 0x00 0x00 0x00 0x03 0x09 0x3b 0x00 0x00 0x00 0x04 0x09 0x3c>;
|
||||
clock-names = "pcie_aux";
|
||||
clocks = <&prci 0x08>;
|
||||
pwren-gpios = <0x0b 0x05 0x00>;
|
||||
perstn-gpios = <0x0b 0x08 0x00>;
|
||||
resets = <&prci 0x04>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 0x80000000 0x04 0x00>;
|
||||
};
|
||||
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
|
||||
green-d12 {
|
||||
label = "green:d12";
|
||||
pwms = <0x0d 0x00 0x773594 0x01>;
|
||||
active-low = <0x01>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
green-d2 {
|
||||
label = "green:d2";
|
||||
pwms = <0x0d 0x01 0x773594 0x01>;
|
||||
active-low = <0x01>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
red-d2 {
|
||||
label = "red:d2";
|
||||
pwms = <0x0d 0x02 0x773594 0x01>;
|
||||
active-low = <0x01>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
blue-d2 {
|
||||
label = "blue:d2";
|
||||
pwms = <0x0d 0x03 0x773594 0x01>;
|
||||
active-low = <0x01>;
|
||||
max-brightness = <0xff>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
};
|
||||
|
||||
clk_hfclk: hfclk {
|
||||
#clock-cells = <0x00>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "hfclk";
|
||||
};
|
||||
|
||||
clk_rtcclk: rtcclk {
|
||||
#clock-cells = <0x00>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000000>;
|
||||
clock-output-names = "rtcclk";
|
||||
};
|
||||
|
||||
gpio-poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <0x0b 0x02 0x01>;
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user