WIP: Fix TLS issues on riscv64

WIP: migrate to 1.94.0 toolchain, broken riscv64
i2c: improve i2c architecture, add sifive i2c driver
2026-03-28 01:58:09 +02:00 · 2026-03-27 17:10:20 +02:00 · 2026-03-25 19:07:59 +02:00 · 2026-03-23 14:02:02 +02:00 · 2026-03-20 16:01:26 +02:00 · 2026-03-20 15:24:55 +02:00
289 changed files with 7607 additions and 1878 deletions
@@ -25,7 +25,6 @@ dependencies = [
 name = "abi-lib"
 version = "0.1.0"
 dependencies = [
- "compiler_builtins",
 "rustc-std-workspace-core",
 ]

@@ -33,7 +32,6 @@ dependencies = [
 name = "abi-serde"
 version = "0.1.0"
 dependencies = [
- "compiler_builtins",
 "rustc-std-workspace-alloc",
 "rustc-std-workspace-core",
 ]
@@ -407,15 +405,6 @@ version = "1.0.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "5b63caa9aa9397e2d9480a9b13673856c78d8ac123288526c37d7839f2a86990"

-[[package]]
-name = "compiler_builtins"
-version = "0.1.146"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a97117b1434b79833f39a5fabdf82f890bd98c1988334dea1cb67f7e627fa311"
-dependencies = [
- "rustc-std-workspace-core",
-]
-
 [[package]]
 name = "console"
 version = "0.15.10"
@@ -1291,9 +1280,8 @@ dependencies = [
 [[package]]
 name = "libm"
 version = "0.2.8"
-source = "git+https://git.alnyan.me/yggdrasil/libm.git#ace5825d9683d2bf4a71c8f18f2c854660c297b2"
+source = "git+https://git.alnyan.me/yggdrasil/libm.git#78b62c33fc6a56b6c063c19bbffc5224616b7028"
 dependencies = [
- "compiler_builtins",
 "rustc-std-workspace-core",
 ]

@@ -1330,7 +1318,6 @@ version = "0.1.0"
 name = "libyalloc"
 version = "0.1.0"
 dependencies = [
- "compiler_builtins",
 "libc",
 "rustc-std-workspace-core",
 "yggdrasil-rt",
@@ -2723,6 +2710,25 @@ dependencies = [
 "yggdrasil-abi",
 ]

+[[package]]
+name = "ygg_driver_bsp_sifive"
+version = "0.1.0"
+dependencies = [
+ "async-trait",
+ "bytemuck",
+ "device-api",
+ "device-tree",
+ "futures-util",
+ "libk",
+ "libk-mm",
+ "libk-util",
+ "log",
+ "static_assertions",
+ "tock-registers",
+ "ygg_driver_net_core",
+ "yggdrasil-abi",
+]
+
 [[package]]
 name = "ygg_driver_fat32"
 version = "0.1.0"
@@ -2754,6 +2760,7 @@ version = "0.1.0"
 dependencies = [
 "async-trait",
 "bytemuck",
+ "device-api",
 "kernel-fs",
 "libk",
 "libk-mm",
@@ -2770,6 +2777,7 @@ name = "ygg_driver_net_igbe"
 version = "0.1.0"
 dependencies = [
 "device-api",
+ "futures-util",
 "libk",
 "libk-mm",
 "libk-util",
@@ -3002,7 +3010,6 @@ dependencies = [
 "abi-lib",
 "abi-serde",
 "bytemuck",
- "compiler_builtins",
 "prettyplease",
 "rustc-std-workspace-alloc",
 "rustc-std-workspace-core",
@@ -3053,6 +3060,7 @@ dependencies = [
 "ygg_driver_bsp_bcm283x",
 "ygg_driver_bsp_jh7110",
 "ygg_driver_bsp_riscv",
+ "ygg_driver_bsp_sifive",
 "ygg_driver_fat32",
 "ygg_driver_input",
 "ygg_driver_net_core",
@@ -3079,7 +3087,6 @@ dependencies = [
 "abi-lib",
 "abi-serde",
 "cc",
- "compiler_builtins",
 "libm",
 "prettyplease",
 "rustc-std-workspace-alloc",
@@ -89,6 +89,7 @@ features = ["no_std_stream"]

 [workspace.lints.rust]
 unexpected_cfgs = { level = "allow", check-cfg = ['cfg(rust_analyzer)'] }
+unsafe_op_in_unsafe_fn.level = "deny"
 [workspace.lints.clippy]
 derivable_impls = { level = "allow" }

@@ -0,0 +1,35 @@
+Booting Yggdrasil OS on SiFive HiFive Unmatched Rev B RISC-V board:
+
+* TODO: proper format for initrd image
+
+Prerequisites:
+
+* OpenSBI + u-boot (can use the u-boot from the Freedom U SDK that comes with the board)
+* yggdrasil-kernel.bin
+* initrd.img
+
+Steps:
+
+1. Copy yggdrasil-kernel.bin and initrd.img into some directory and start a TFTP server there
+2. Connect to HFU's serial port, ethernet and enter u-boot
+3. Run the following commands in u-boot:
+
+### If using DHCP
+
+=> setenv autoload no
+=> setenv initrd_addr_r 0x90000000
+=> dhcp
+=> tftpboot ${initrd_addr_r} <SERVER IP>:initrd.img
+=> tftpboot ${loadaddr} <SERVER IP>:yggdrasil-kernel.bin
+=> tftpboot ${fdt_addr_r} <SERVER IP>:hifive-unmatched-a00.dtb
+=> fdt resize
+=> booti ${loadaddr} ${initrd_addr_r}:60000000 ${fdt_addr_r}
+
+Two-liner (server is 13.0.0.1, board is 13.0.0.2):
+
+setenv ipaddr 13.0.0.2;setenv initrd_addr_r 0x90000000;tftpboot ${initrd_addr_r} 13.0.0.1:initrd.img;tftpboot ${loadaddr} 13.0.0.1:yggdrasil-kernel.bin;tftpboot ${fdt_addr_r} 13.0.0.1:hifive-unmatched-a00.dtb;fdt resize
+booti ${loadaddr} ${initrd_addr_r}:60000000 ${fdt_addr_r}
+
+One-liner without initrd
+
+setenv ipaddr 13.0.0.2;tftpboot ${loadaddr} 13.0.0.1:yggdrasil-kernel.bin;tftpboot ${fdt_addr_r} 13.0.0.1:hifive-unmatched-a00.dtb;fdt resize;booti ${loadaddr} - ${fdt_addr_r}
@@ -2,6 +2,7 @@
  "arch": "aarch64",
  "os": "none",
  "abi": "softfloat",
+  "rustc-abi": "softfloat",
  "llvm-target": "aarch64-unknown-none",
  "data-layout": "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32",
  "max-atomic-width": 128,
@@ -0,0 +1,319 @@
+/dts-v1/;
+
+#define CLK_COREPLL     0
+#define CLK_DDRPLL      1
+#define CLK_GEMGXLPLL   2
+#define CLK_DVFSCOREPLL 3
+#define CLK_HFPCLKPLL   4
+#define CLK_CLTXPLL     5
+#define CLK_TLCLK       6
+#define CLK_PCLK        7
+#define CLK_PCIE_AUX    8
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740";
+	model = "SiFive HiFive Unmatched";
+
+	aliases {
+		serial0 = "/soc/serial@10010000";
+		serial1 = "/soc/serial@10011000";
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <1000000>;
+
+		cpu0: cpu@0 {
+			compatible = "sifive,bullet0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			next-level-cache = <&ccache>;
+			reg = <0>;
+			riscv,isa = "rv64imac";
+			status = "disabled";
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			device_type = "cpu";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <1>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			device_type = "cpu";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <2>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			device_type = "cpu";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <3>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu4: cpu@4 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			device_type = "cpu";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
+			reg = <4>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			cpu4_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		plic: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
+			reg = <0x00 0xc000000 0x00 0x4000000>;
+			riscv,ndev = <69>;
+			interrupt-controller;
+			interrupts-extended = <&cpu0_intc 0xffffffff>,
+                                  <&cpu1_intc 0xffffffff>,
+                                  <&cpu1_intc 0x09>,
+                                  <&cpu2_intc 0xffffffff>,
+                                  <&cpu2_intc 0x09>,
+                                  <&cpu3_intc 0xffffffff>,
+                                  <&cpu3_intc 0x09>,
+                                  <&cpu4_intc 0xffffffff>,
+                                  <&cpu4_intc 0x09>;
+		};
+
+		prci: clock-controller@10000000 {
+			compatible = "sifive,fu740-c000-prci";
+			reg = <0x00 0x10000000 0x00 0x1000>;
+			clocks = <&clk_hfclk>, <&clk_rtcclk>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		uart0: serial@10010000 {
+			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+			reg = <0x00 0x10010000 0x00 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <39>;
+			clocks = <&prci CLK_PCLK>;
+			status = "okay";
+		};
+
+		uart1: serial@10011000 {
+			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+			reg = <0x00 0x10011000 0x00 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <40>;
+			clocks = <&prci CLK_PCLK>;
+			status = "disabled";
+		};
+
+		ccache: cache-controller@2010000 {
+			compatible = "sifive,fu740-c000-ccache", "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <0x200000>;
+			cache-unified;
+			interrupt-parent = <&plic>;
+			interrupts = <0x13>, <0x15>, <0x16>, <0x14>;
+			reg = <0x00 0x2010000 0x00 0x1000>;
+		};
+
+		pwm0: pwm@10020000 {
+			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+			reg = <0x00 0x10020000 0x00 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <44>, <45>, <46>, <47>;
+			clocks = <&prci CLK_PCLK>;
+			#pwm-cells = <3>;
+			status = "okay";
+		};
+
+		pwm1: pwm@10021000 {
+			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+			reg = <0x00 0x10021000 0x00 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <48>, <49>, <50>, <51>;
+			clocks = <&prci CLK_PCLK>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@10030000 {
+			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+			reg = <0x00 0x10030000 0x00 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <52>;
+			clocks = <&prci CLK_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+        };
+
+		i2c1: i2c@10031000 {
+			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+			reg = <0x00 0x10031000 0x00 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <53>;
+			clocks = <&prci CLK_PCLK>;
+			reg-shift = <2>;
+			reg-io-width = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00 0x80000000 0x04 0x00>;
+	};
+
+	leds: pwmleds {
+		compatible = "pwm-leds";
+
+		green-d12 {
+			label = "green:d12";
+			pwms = <&pwm0 0 7812500 0x01>;
+			active-low = <1>;
+			max-brightness = <255>;
+			linux,default-trigger = "none";
+		};
+
+		green-d2 {
+			label = "green:d2";
+			pwms = <&pwm0 1 7812500 0x01>;
+			active-low = <1>;
+			max-brightness = <255>;
+			linux,default-trigger = "none";
+		};
+
+		red-d2 {
+			label = "red:d2";
+			pwms = <&pwm0 2 7812500 0x01>;
+			active-low = <0x01>;
+			max-brightness = <0xff>;
+			linux,default-trigger = "none";
+		};
+
+		blue-d2 {
+			label = "blue:d2";
+			pwms = <&pwm0 3 7812500 0x01>;
+			active-low = <1>;
+			max-brightness = <255>;
+			linux,default-trigger = "none";
+		};
+	};
+
+	clk_hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		clock-output-names = "hfclk";
+	};
+
+	clk_rtcclk: rtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <1000000>;
+		clock-output-names = "rtcclk";
+	};
+};
@@ -0,0 +1,252 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	compatible = "sifive,hifive-unleashed-a00";
+	model = "SiFive HiFive Unleashed A00";
+
+	chosen {
+		linux,initrd-end = <0x00 0x87688400>;
+		linux,initrd-start = <0x00 0x84200000>;
+		stdout-path = "/soc/serial@10010000";
+	};
+
+	aliases {
+		serial0 = "/soc/serial@10010000";
+		serial1 = "/soc/serial@10011000";
+		ethernet0 = "/soc/ethernet@10090000";
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 0x0a 0x01>;
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		timebase-frequency = <0xf4240>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0x00>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", "zihpm", "sdtrig";
+			riscv,isa-base = "rv64i";
+			riscv,isa = "rv64imac_zicntr_zicsr_zifencei_zihpm_sdtrig";
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				phandle = <0x04>;
+			};
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			reg = <0x01>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm", "sdtrig";
+			riscv,isa-base = "rv64i";
+			riscv,isa = "rv64imafdc_zicntr_zicsr_zifencei_zihpm_sdtrig";
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				phandle = <0x03>;
+			};
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00 0x80000000 0x00 0x8000000>;
+	};
+
+	rtcclk: rtcclk {
+		#clock-cells = <0x00>;
+		compatible = "fixed-clock";
+		clock-frequency = <0xf4240>;
+		clock-output-names = "rtcclk";
+		phandle = <0x02>;
+	};
+
+	hfclk: hfclk {
+		#clock-cells = <0x00>;
+		compatible = "fixed-clock";
+		clock-frequency = <0x1fca055>;
+		clock-output-names = "hfclk";
+		phandle = <0x01>;
+	};
+
+	soc {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart0: serial@10010000 {
+			interrupts = <4>;
+			interrupt-parent = <&plic>;
+			clocks = <&prci 0x03>;
+			reg = <0x00 0x10010000 0x00 0x1000>;
+			compatible = "sifive,uart0";
+		};
+
+		uart1: serial@10011000 {
+			interrupts = <5>;
+			interrupt-parent = <&plic>;
+			clocks = <&prci 0x03>;
+			reg = <0x00 0x10011000 0x00 0x1000>;
+			compatible = "sifive,uart0";
+		};
+
+		pwm0: pwm@10020000 {
+			#pwm-cells = <0>;
+			clocks = <&prci 0x03>;
+			interrupts = <42>, <43>, <44>, <45>;
+			interrupt-parent = <&plic>;
+			reg = <0x00 0x10020000 0x00 0x1000>;
+			compatible = "sifive,pwm0";
+		};
+
+		pwm1: pwm@10021000 {
+			#pwm-cells = <0>;
+			clocks = <&prci 0x03>;
+			interrupts = <46>, <47>, <48>, <49>;
+			interrupt-parent = <&plic>;
+			reg = <0x00 0x10021000 0x00 0x1000>;
+			compatible = "sifive,pwm0";
+            status = "disabled";
+		};
+
+		gmac0: ethernet@10090000 {
+			#size-cells = <0x00>;
+			#address-cells = <0x01>;
+			local-mac-address = [52 54 00 12 34 56];
+			clock-names = "pclk", "hclk";
+			clocks = <&prci 0x02>, <&prci 0x02>;
+			interrupts = <0x35>;
+			interrupt-parent = <&plic>;
+			phy-handle = <&gmac0_phy>;
+			phy-mode = "gmii";
+			reg-names = "control";
+			reg = <0x00 0x10090000 0x00 0x2000>,
+                  <0x00 0x100a0000 0x00 0x1000>;
+			compatible = "sifive,fu540-c000-gem";
+
+			gmac0_phy: ethernet-phy@0 {
+				reg = <0x00>;
+			};
+		};
+
+		// spi@10040000 {
+		// 	compatible = "sifive,spi0";
+		// 	reg = <0x00 0x10040000 0x00 0x1000>;
+		// 	interrupt-parent = <0x06>;
+		// 	interrupts = <0x33>;
+		// 	clocks = <0x05 0x03>;
+		// 	#address-cells = <0x01>;
+		// 	#size-cells = <0x00>;
+
+		// 	flash@0 {
+		// 		compatible = "jedec,spi-nor";
+		// 		reg = <0x00>;
+		// 		spi-max-frequency = <0x2faf080>;
+		// 		m25p,fast-read;
+		// 		spi-tx-bus-width = <0x04>;
+		// 		spi-rx-bus-width = <0x04>;
+		// 	};
+		// };
+
+		// spi@10050000 {
+		// 	compatible = "sifive,spi0";
+		// 	reg = <0x00 0x10050000 0x00 0x1000>;
+		// 	interrupt-parent = <0x06>;
+		// 	interrupts = <0x06>;
+		// 	clocks = <0x05 0x03>;
+		// 	#address-cells = <0x01>;
+		// 	#size-cells = <0x00>;
+
+		// 	mmc@0 {
+		// 		compatible = "mmc-spi-slot";
+		// 		reg = <0x00>;
+		// 		spi-max-frequency = <0x1312d00>;
+		// 		voltage-ranges = <0xce4 0xce4>;
+		// 		disable-wp;
+		// 	};
+		// };
+
+		// cache-controller@2010000 {
+		// 	compatible = "sifive,fu540-c000-ccache";
+		// 	cache-block-size = <0x40>;
+		// 	cache-level = <0x02>;
+		// 	cache-sets = <0x400>;
+		// 	cache-size = <0x200000>;
+		// 	cache-unified;
+		// 	interrupt-parent = <0x06>;
+		// 	interrupts = <0x01 0x02 0x03>;
+		// 	reg = <0x00 0x2010000 0x00 0x1000>;
+		// };
+
+		// dma@3000000 {
+		// 	compatible = "sifive,fu540-c000-pdma";
+		// 	reg = <0x00 0x3000000 0x00 0x100000>;
+		// 	interrupt-parent = <0x06>;
+		// 	interrupts = <0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>;
+		// 	#dma-cells = <0x01>;
+		// };
+
+		gpio: gpio@10060000 {
+			compatible = "sifive,gpio0";
+			interrupt-parent = <&plic>;
+			interrupts = <0x07>, <0x08>, <0x09>, <0x0a>,
+                         <0x0b>, <0x0c>, <0x0d>, <0x0e>,
+                         <0x0f>, <0x10>, <0x11>, <0x12>,
+                         <0x13>, <0x14>, <0x15>, <0x16>;
+			reg = <0x00 0x10060000 0x00 0x1000>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			clocks = <&prci 0x03>;
+			phandle = <0x07>;
+		};
+
+		plic: interrupt-controller@c000000 {
+			phandle = <0x06>;
+			riscv,ndev = <0x35>;
+			reg = <0x00 0xc000000 0x00 0x4000000>;
+			interrupts-extended = <&cpu0_intc 0x0b>, <&cpu1_intc 0x0b>, <&cpu1_intc 0x09>;
+			interrupt-controller;
+			compatible = "sifive,plic-1.0.0", "riscv,plic0";
+			#interrupt-cells = <0x01>;
+		};
+
+		prci: clock-controller@10000000 {
+			compatible = "sifive,fu540-c000-prci";
+			reg = <0x00 0x10000000 0x00 0x1000>;
+			clocks = <&hfclk>, <&rtcclk>;
+			#clock-cells = <0x01>;
+			phandle = <0x05>;
+		};
+
+		// otp@10070000 {
+		// 	compatible = "sifive,fu540-c000-otp";
+		// 	reg = <0x00 0x10070000 0x00 0x1000>;
+		// 	fuse-count = <0x1000>;
+		// };
+
+		clint: clint@2000000 {
+			interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, <&cpu1_intc 0x03>, <&cpu1_intc 0x07>;
+			reg = <0x00 0x2000000 0x00 0x10000>;
+			compatible = "sifive,clint0", "riscv,clint0";
+		};
+	};
+};
@@ -0,0 +1,577 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740";
+	model = "SiFive HiFive Unmatched";
+
+	aliases {
+		serial0 = "/soc/serial@10010000";
+		serial1 = "/soc/serial@10011000";
+		ethernet0 = "/soc/ethernet@10090000";
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		timebase-frequency = <0xf4240>;
+
+		cpu@0 {
+			compatible = "sifive,bullet0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x4000>;
+			next-level-cache = <0x01>;
+			reg = <0x00>;
+			riscv,isa = "rv64imac";
+			status = "disabled";
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x02>;
+			};
+		};
+
+		cpu@1 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x01>;
+			d-tlb-size = <0x28>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x01>;
+			i-tlb-size = <0x28>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <0x01>;
+			reg = <0x01>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x03>;
+			};
+		};
+
+		cpu@2 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x01>;
+			d-tlb-size = <0x28>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x01>;
+			i-tlb-size = <0x28>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <0x01>;
+			reg = <0x02>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x04>;
+			};
+		};
+
+		cpu@3 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x01>;
+			d-tlb-size = <0x28>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x01>;
+			i-tlb-size = <0x28>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <0x01>;
+			reg = <0x03>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x05>;
+			};
+		};
+
+		cpu@4 {
+			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+			d-cache-block-size = <0x40>;
+			d-cache-sets = <0x40>;
+			d-cache-size = <0x8000>;
+			d-tlb-sets = <0x01>;
+			d-tlb-size = <0x28>;
+			device_type = "cpu";
+			i-cache-block-size = <0x40>;
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-tlb-sets = <0x01>;
+			i-tlb-size = <0x28>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <0x01>;
+			reg = <0x04>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				phandle = <0x06>;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "simple-bus";
+		ranges;
+
+		interrupt-controller@c000000 {
+			#interrupt-cells = <0x01>;
+			#address-cells = <0x00>;
+			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
+			reg = <0x00 0xc000000 0x00 0x4000000>;
+			riscv,ndev = <0x45>;
+			interrupt-controller;
+			interrupts-extended = <0x02 0xffffffff 0x03 0xffffffff 0x03 0x09 0x04 0xffffffff 0x04 0x09 0x05 0xffffffff 0x05 0x09 0x06 0xffffffff 0x06 0x09>;
+			phandle = <0x09>;
+		};
+
+		prci: clock-controller@10000000 {
+			compatible = "sifive,fu740-c000-prci";
+			reg = <0x00 0x10000000 0x00 0x1000>;
+			clocks = <&clk_hfclk>, <&clk_rtcclk>;
+			#clock-cells = <0x01>;
+			#reset-cells = <0x01>;
+		};
+
+		serial@10010000 {
+			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+			reg = <0x00 0x10010000 0x00 0x1000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x27>;
+			clocks = <&prci 0x07>;
+			status = "okay";
+		};
+
+		serial@10011000 {
+			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+			reg = <0x00 0x10011000 0x00 0x1000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x28>;
+			clocks = <&prci 0x07>;
+			status = "okay";
+		};
+
+		i2c@10030000 {
+			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+			reg = <0x00 0x10030000 0x00 0x1000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x34>;
+			clocks = <&prci 0x07>;
+			reg-shift = <0x02>;
+			reg-io-width = <0x01>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "okay";
+
+			temperature-sensor@4c {
+				compatible = "ti,tmp451";
+				reg = <0x4c>;
+				interrupt-parent = <0x0b>;
+				interrupts = <0x06 0x08>;
+			};
+
+			pmic@58 {
+				compatible = "dlg,da9063";
+				reg = <0x58>;
+				interrupt-parent = <0x0b>;
+				interrupts = <0x01 0x08>;
+				interrupt-controller;
+
+				regulators {
+
+					bcore1 {
+						regulator-min-microvolt = <0x100590>;
+						regulator-max-microvolt = <0x100590>;
+						regulator-min-microamp = <0x4c4b40>;
+						regulator-max-microamp = <0x4c4b40>;
+						regulator-always-on;
+					};
+
+					bcore2 {
+						regulator-min-microvolt = <0x100590>;
+						regulator-max-microvolt = <0x100590>;
+						regulator-min-microamp = <0x4c4b40>;
+						regulator-max-microamp = <0x4c4b40>;
+						regulator-always-on;
+					};
+
+					bpro {
+						regulator-min-microvolt = <0x1b7740>;
+						regulator-max-microvolt = <0x1b7740>;
+						regulator-min-microamp = <0x2625a0>;
+						regulator-max-microamp = <0x2625a0>;
+						regulator-always-on;
+					};
+
+					bperi {
+						regulator-min-microvolt = <0x100590>;
+						regulator-max-microvolt = <0x100590>;
+						regulator-min-microamp = <0x16e360>;
+						regulator-max-microamp = <0x16e360>;
+						regulator-always-on;
+					};
+
+					bmem {
+						regulator-min-microvolt = <0x124f80>;
+						regulator-max-microvolt = <0x124f80>;
+						regulator-min-microamp = <0x2dc6c0>;
+						regulator-max-microamp = <0x2dc6c0>;
+						regulator-always-on;
+					};
+
+					bio {
+						regulator-min-microvolt = <0x124f80>;
+						regulator-max-microvolt = <0x124f80>;
+						regulator-min-microamp = <0x2dc6c0>;
+						regulator-max-microamp = <0x2dc6c0>;
+						regulator-always-on;
+					};
+
+					ldo1 {
+						regulator-min-microvolt = <0x1b7740>;
+						regulator-max-microvolt = <0x1b7740>;
+						regulator-min-microamp = <0x186a0>;
+						regulator-max-microamp = <0x186a0>;
+						regulator-always-on;
+					};
+
+					ldo2 {
+						regulator-min-microvolt = <0x1b7740>;
+						regulator-max-microvolt = <0x1b7740>;
+						regulator-min-microamp = <0x30d40>;
+						regulator-max-microamp = <0x30d40>;
+						regulator-always-on;
+					};
+
+					ldo3 {
+						regulator-min-microvolt = <0x325aa0>;
+						regulator-max-microvolt = <0x325aa0>;
+						regulator-min-microamp = <0x30d40>;
+						regulator-max-microamp = <0x30d40>;
+						regulator-always-on;
+					};
+
+					ldo4 {
+						regulator-min-microvolt = <0x2625a0>;
+						regulator-max-microvolt = <0x2625a0>;
+						regulator-min-microamp = <0x30d40>;
+						regulator-max-microamp = <0x30d40>;
+						regulator-always-on;
+					};
+
+					ldo5 {
+						regulator-min-microvolt = <0x325aa0>;
+						regulator-max-microvolt = <0x325aa0>;
+						regulator-min-microamp = <0x186a0>;
+						regulator-max-microamp = <0x186a0>;
+						regulator-always-on;
+					};
+
+					ldo6 {
+						regulator-min-microvolt = <0x1b7740>;
+						regulator-max-microvolt = <0x1b7740>;
+						regulator-min-microamp = <0x30d40>;
+						regulator-max-microamp = <0x30d40>;
+						regulator-always-on;
+					};
+
+					ldo7 {
+						regulator-min-microvolt = <0x325aa0>;
+						regulator-max-microvolt = <0x325aa0>;
+						regulator-min-microamp = <0x30d40>;
+						regulator-max-microamp = <0x30d40>;
+						regulator-always-on;
+					};
+
+					ldo8 {
+						regulator-min-microvolt = <0x325aa0>;
+						regulator-max-microvolt = <0x325aa0>;
+						regulator-min-microamp = <0x30d40>;
+						regulator-max-microamp = <0x30d40>;
+						regulator-always-on;
+					};
+
+					ldo9 {
+						regulator-min-microvolt = <0x100590>;
+						regulator-max-microvolt = <0x100590>;
+						regulator-min-microamp = <0x30d40>;
+						regulator-max-microamp = <0x30d40>;
+					};
+
+					ldo10 {
+						regulator-min-microvolt = <0xf4240>;
+						regulator-max-microvolt = <0xf4240>;
+						regulator-min-microamp = <0x493e0>;
+						regulator-max-microamp = <0x493e0>;
+					};
+
+					ldo11 {
+						regulator-min-microvolt = <0x2625a0>;
+						regulator-max-microvolt = <0x2625a0>;
+						regulator-min-microamp = <0x493e0>;
+						regulator-max-microamp = <0x493e0>;
+						regulator-always-on;
+					};
+				};
+			};
+		};
+
+		i2c@10031000 {
+			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+			reg = <0x00 0x10031000 0x00 0x1000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x35>;
+			clocks = <&prci 0x07>;
+			reg-shift = <0x02>;
+			reg-io-width = <0x01>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "disabled";
+		};
+
+		spi@10040000 {
+			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+			reg = <0x00 0x10040000 0x00 0x1000 0x00 0x20000000 0x00 0x10000000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x29>;
+			clocks = <&prci 0x07>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "okay";
+
+			flash@0 {
+				compatible = "issi,is25wp256", "jedec,spi-nor";
+				reg = <0x00>;
+				spi-max-frequency = <0x2faf080>;
+				m25p,fast-read;
+				spi-tx-bus-width = <0x04>;
+				spi-rx-bus-width = <0x04>;
+			};
+		};
+
+		spi@10041000 {
+			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+			reg = <0x00 0x10041000 0x00 0x1000 0x00 0x30000000 0x00 0x10000000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x2a>;
+			clocks = <&prci 0x07>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "disabled";
+		};
+
+		spi@10050000 {
+			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+			reg = <0x00 0x10050000 0x00 0x1000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x2b>;
+			clocks = <&prci 0x07>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "okay";
+
+			mmc@0 {
+				compatible = "mmc-spi-slot";
+				reg = <0x00>;
+				spi-max-frequency = <0x1312d00>;
+				voltage-ranges = <0xce4 0xce4>;
+				disable-wp;
+			};
+		};
+
+		macb: ethernet@10090000 {
+			compatible = "sifive,fu540-c000-gem";
+			interrupt-parent = <0x09>;
+			interrupts = <0x37>;
+			reg = <0x00 0x10090000 0x00 0x2000 0x00 0x100a0000 0x00 0x1000>;
+			local-mac-address = [00 00 00 00 00 00];
+			clock-names = "pclk", "hclk";
+			clocks = <&prci 0x02 &prci 0x02>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			status = "okay";
+			phy-mode = "gmii";
+			phy-handle = <0x0c>;
+
+			ethernet-phy@0 {
+				reg = <0x00>;
+				phandle = <0x0c>;
+			};
+		};
+
+		pwm@10020000 {
+			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+			reg = <0x00 0x10020000 0x00 0x1000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x2c 0x2d 0x2e 0x2f>;
+			clocks = <&prci 0x07>;
+			#pwm-cells = <0x03>;
+			status = "okay";
+			phandle = <0x0d>;
+		};
+
+		pwm@10021000 {
+			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+			reg = <0x00 0x10021000 0x00 0x1000>;
+			interrupt-parent = <0x09>;
+			interrupts = <0x30 0x31 0x32 0x33>;
+			clocks = <&prci 0x07>;
+			#pwm-cells = <0x03>;
+			status = "okay";
+		};
+
+		cache-controller@2010000 {
+			compatible = "sifive,fu740-c000-ccache", "cache";
+			cache-block-size = <0x40>;
+			cache-level = <0x02>;
+			cache-sets = <0x800>;
+			cache-size = <0x200000>;
+			cache-unified;
+			interrupt-parent = <0x09>;
+			interrupts = <0x13 0x15 0x16 0x14>;
+			reg = <0x00 0x2010000 0x00 0x1000>;
+			phandle = <0x01>;
+		};
+
+		gpio@10060000 {
+			compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
+			interrupt-parent = <0x09>;
+			interrupts = <0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26>;
+			reg = <0x00 0x10060000 0x00 0x1000>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			clocks = <&prci 0x07>;
+			status = "okay";
+			phandle = <0x0b>;
+		};
+
+		pcie@e00000000 {
+			#address-cells = <0x03>;
+			#interrupt-cells = <0x01>;
+			#num-lanes = <0x08>;
+			#size-cells = <0x02>;
+			compatible = "sifive,fu740-pcie";
+			reg = <0x0e 0x00 0x01 0x00 0x0d 0xf0000000 0x00 0x10000000 0x00 0x100d0000 0x00 0x1000>;
+			reg-names = "dbi", "config", "mgmt";
+			device_type = "pci";
+			dma-coherent;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x60080000 0x00 0x60080000 0x00 0x10000 0x82000000 0x00 0x60090000 0x00 0x60090000 0x00 0xff70000 0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0x1000000 0xc3000000 0x20 0x00 0x20 0x00 0x20 0x00>;
+			num-lanes = <0x08>;
+			interrupts = <0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40>;
+			interrupt-names = "msi", "inta", "intb", "intc", "intd";
+			interrupt-parent = <0x09>;
+			interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+			interrupt-map = <0x00 0x00 0x00 0x01 0x09 0x39 0x00 0x00 0x00 0x02 0x09 0x3a 0x00 0x00 0x00 0x03 0x09 0x3b 0x00 0x00 0x00 0x04 0x09 0x3c>;
+			clock-names = "pcie_aux";
+			clocks = <&prci 0x08>;
+			pwren-gpios = <0x0b 0x05 0x00>;
+			perstn-gpios = <0x0b 0x08 0x00>;
+			resets = <&prci 0x04>;
+			status = "okay";
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00 0x80000000 0x04 0x00>;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		green-d12 {
+			label = "green:d12";
+			pwms = <0x0d 0x00 0x773594 0x01>;
+			active-low = <0x01>;
+			max-brightness = <0xff>;
+			linux,default-trigger = "none";
+		};
+
+		green-d2 {
+			label = "green:d2";
+			pwms = <0x0d 0x01 0x773594 0x01>;
+			active-low = <0x01>;
+			max-brightness = <0xff>;
+			linux,default-trigger = "none";
+		};
+
+		red-d2 {
+			label = "red:d2";
+			pwms = <0x0d 0x02 0x773594 0x01>;
+			active-low = <0x01>;
+			max-brightness = <0xff>;
+			linux,default-trigger = "none";
+		};
+
+		blue-d2 {
+			label = "blue:d2";
+			pwms = <0x0d 0x03 0x773594 0x01>;
+			active-low = <0x01>;
+			max-brightness = <0xff>;
+			linux,default-trigger = "none";
+		};
+	};
+
+	clk_hfclk: hfclk {
+		#clock-cells = <0x00>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		clock-output-names = "hfclk";
+	};
+
+	clk_rtcclk: rtcclk {
+		#clock-cells = <0x00>;
+		compatible = "fixed-clock";
+		clock-frequency = <1000000>;
+		clock-output-names = "rtcclk";
+	};
+
+	gpio-poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <0x0b 0x02 0x01>;
+	};
+};
@@ -0,0 +1,248 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	compatible = "sifive,hifive-unleashed-a00";
+	model = "SiFive HiFive Unleashed A00";
+
+	chosen {
+		linux,initrd-end = <0x00 0x87688400>;
+		linux,initrd-start = <0x00 0x84200000>;
+		stdout-path = "/soc/serial@10010000";
+	};
+
+	aliases {
+		serial0 = "/soc/serial@10010000";
+		serial1 = "/soc/serial@10011000";
+		ethernet0 = "/soc/ethernet@10090000";
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <0x07 0x0a 0x01>;
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		timebase-frequency = <0xf4240>;
+
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0x00>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", "zihpm", "sdtrig";
+			riscv,isa-base = "rv64i";
+			riscv,isa = "rv64imac_zicntr_zicsr_zifencei_zihpm_sdtrig";
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				phandle = <0x04>;
+			};
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			reg = <0x01>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm", "sdtrig";
+			riscv,isa-base = "rv64i";
+			riscv,isa = "rv64imafdc_zicntr_zicsr_zifencei_zihpm_sdtrig";
+			mmu-type = "riscv,sv39";
+
+			interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				phandle = <0x03>;
+			};
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00 0x80000000 0x00 0x8000000>;
+	};
+
+	rtcclk {
+		#clock-cells = <0x00>;
+		compatible = "fixed-clock";
+		clock-frequency = <0xf4240>;
+		clock-output-names = "rtcclk";
+		phandle = <0x02>;
+	};
+
+	hfclk {
+		#clock-cells = <0x00>;
+		compatible = "fixed-clock";
+		clock-frequency = <0x1fca055>;
+		clock-output-names = "hfclk";
+		phandle = <0x01>;
+	};
+
+	soc {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "simple-bus";
+		ranges;
+
+		serial@10010000 {
+			interrupts = <0x04>;
+			interrupt-parent = <0x06>;
+			clocks = <0x05 0x03>;
+			reg = <0x00 0x10010000 0x00 0x1000>;
+			compatible = "sifive,uart0";
+		};
+
+		serial@10011000 {
+			interrupts = <0x05>;
+			interrupt-parent = <0x06>;
+			clocks = <0x05 0x03>;
+			reg = <0x00 0x10011000 0x00 0x1000>;
+			compatible = "sifive,uart0";
+		};
+
+		pwm@10021000 {
+			#pwm-cells = <0x00>;
+			clocks = <0x05 0x03>;
+			interrupts = <0x2e 0x2f 0x30 0x31>;
+			interrupt-parent = <0x06>;
+			reg = <0x00 0x10021000 0x00 0x1000>;
+			compatible = "sifive,pwm0";
+		};
+
+		pwm@10020000 {
+			#pwm-cells = <0x00>;
+			clocks = <0x05 0x03>;
+			interrupts = <0x2a 0x2b 0x2c 0x2d>;
+			interrupt-parent = <0x06>;
+			reg = <0x00 0x10020000 0x00 0x1000>;
+			compatible = "sifive,pwm0";
+		};
+
+		ethernet@10090000 {
+			#size-cells = <0x00>;
+			#address-cells = <0x01>;
+			local-mac-address = [52 54 00 12 34 56];
+			clock-names = "pclk", "hclk";
+			clocks = <0x05 0x02 0x05 0x02>;
+			interrupts = <0x35>;
+			interrupt-parent = <0x06>;
+			phy-handle = <0x08>;
+			phy-mode = "gmii";
+			reg-names = "control";
+			reg = <0x00 0x10090000 0x00 0x2000 0x00 0x100a0000 0x00 0x1000>;
+			compatible = "sifive,fu540-c000-gem";
+
+			ethernet-phy@0 {
+				reg = <0x00>;
+				phandle = <0x08>;
+			};
+		};
+
+		spi@10040000 {
+			compatible = "sifive,spi0";
+			reg = <0x00 0x10040000 0x00 0x1000>;
+			interrupt-parent = <0x06>;
+			interrupts = <0x33>;
+			clocks = <0x05 0x03>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0x00>;
+				spi-max-frequency = <0x2faf080>;
+				m25p,fast-read;
+				spi-tx-bus-width = <0x04>;
+				spi-rx-bus-width = <0x04>;
+			};
+		};
+
+		spi@10050000 {
+			compatible = "sifive,spi0";
+			reg = <0x00 0x10050000 0x00 0x1000>;
+			interrupt-parent = <0x06>;
+			interrupts = <0x06>;
+			clocks = <0x05 0x03>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			mmc@0 {
+				compatible = "mmc-spi-slot";
+				reg = <0x00>;
+				spi-max-frequency = <0x1312d00>;
+				voltage-ranges = <0xce4 0xce4>;
+				disable-wp;
+			};
+		};
+
+		cache-controller@2010000 {
+			compatible = "sifive,fu540-c000-ccache";
+			cache-block-size = <0x40>;
+			cache-level = <0x02>;
+			cache-sets = <0x400>;
+			cache-size = <0x200000>;
+			cache-unified;
+			interrupt-parent = <0x06>;
+			interrupts = <0x01 0x02 0x03>;
+			reg = <0x00 0x2010000 0x00 0x1000>;
+		};
+
+		dma@3000000 {
+			compatible = "sifive,fu540-c000-pdma";
+			reg = <0x00 0x3000000 0x00 0x100000>;
+			interrupt-parent = <0x06>;
+			interrupts = <0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e>;
+			#dma-cells = <0x01>;
+		};
+
+		gpio@10060000 {
+			compatible = "sifive,gpio0";
+			interrupt-parent = <0x06>;
+			interrupts = <0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16>;
+			reg = <0x00 0x10060000 0x00 0x1000>;
+			gpio-controller;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			clocks = <0x05 0x03>;
+			phandle = <0x07>;
+		};
+
+		interrupt-controller@c000000 {
+			phandle = <0x06>;
+			riscv,ndev = <0x35>;
+			reg = <0x00 0xc000000 0x00 0x4000000>;
+			interrupts-extended = <0x04 0x0b 0x03 0x0b 0x03 0x09>;
+			interrupt-controller;
+			compatible = "sifive,plic-1.0.0", "riscv,plic0";
+			#interrupt-cells = <0x01>;
+		};
+
+		clock-controller@10000000 {
+			compatible = "sifive,fu540-c000-prci";
+			reg = <0x00 0x10000000 0x00 0x1000>;
+			clocks = <0x01 0x02>;
+			#clock-cells = <0x01>;
+			phandle = <0x05>;
+		};
+
+		otp@10070000 {
+			compatible = "sifive,fu540-c000-otp";
+			reg = <0x00 0x10070000 0x00 0x1000>;
+			fuse-count = <0x1000>;
+		};
+
+		clint@2000000 {
+			interrupts-extended = <0x04 0x03 0x04 0x07 0x03 0x03 0x03 0x07>;
+			reg = <0x00 0x2000000 0x00 0x10000>;
+			compatible = "sifive,clint0", "riscv,clint0";
+		};
+	};
+};
@@ -1,8 +1,8 @@
 {
  "arch": "riscv64",
  "os": "none",
-  "abi": "softfloat",
  "cpu": "generic-rv64",
+  "llvm-abiname": "lp64",
  "llvm-target": "riscv64",
  "data-layout": "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
  "max-atomic-width": 64,
@@ -20,7 +20,6 @@

  "crt-objects-fallback": "false",
  "emit-debug-gdb-scripts": false,
-  "llvm-abiname": "lp64",

  "linker": "rust-lld",
  "linker-flavor": "ld.lld"
@@ -67,6 +67,7 @@ ygg_driver_bsp_arm.path = "driver/bsp/arm"  # PrimeCell components
 ygg_driver_bsp_riscv.path = "driver/bsp/riscv"
 ygg_driver_net_stmmac.path = "driver/net/stmmac"
 ygg_driver_bsp_jh7110.path = "driver/bsp/jh7110"
+ygg_driver_bsp_sifive.path = "driver/bsp/sifive"

 [target.'cfg(target_arch = "x86_64")'.dependencies]
 yboot-proto.workspace = true
@@ -1,5 +1,4 @@
 #![no_std]
-#![feature(decl_macro)]
 #![allow(clippy::new_without_default)]

 extern crate alloc;
@@ -1,7 +1,7 @@
 [package]
 name = "kernel-arch-hosted"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 kernel-arch-interface.workspace = true
@@ -1,7 +1,7 @@
 [package]
 name = "kernel-arch-interface"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -94,7 +94,7 @@ impl<A: Architecture, S: Scheduler + 'static> CpuImpl<A, S> {
    ///
    /// See [Architecture::set_local_cpu].
    pub unsafe fn set_local(&'static mut self) {
-        A::set_local_cpu(self as *mut _ as *mut _)
+        unsafe { A::set_local_cpu(self as *mut _ as *mut _) }
    }

    pub fn try_local<'a>() -> Option<LocalCpuImpl<'a, A, S>> {
@@ -1,5 +1,5 @@
 #![no_std]
-#![feature(step_trait, const_trait_impl, never_type, decl_macro)]
+#![feature(never_type)]
 #![allow(clippy::new_without_default)]

 use core::ops::Range;
@@ -86,7 +86,7 @@ impl<A: KernelTableManager> RawDeviceMemoryMapping<A> {
        size: usize,
        attrs: DeviceMemoryAttributes,
    ) -> Result<Self, Error> {
-        A::map_device_pages(base, size, attrs)
+        unsafe { A::map_device_pages(base, size, attrs) }
    }

    /// Consumes the device mapping, leaking its address without deallocating the translation
@@ -1,3 +1,4 @@
+use device_api::{ResetDevice, device::Device};
 use yggdrasil_abi::{error::Error, primitive_enum};

 const EXT_HSM: u64 = 0x48534D;
@@ -6,6 +7,7 @@ const EXT_DBCN: u64 = 0x4442434E;
 const EXT_SPI: u64 = 0x735049;
 const EXT_SYSTEM_SHUTDOWN: u64 = 0x53525354;
 const EXT_SYSTEM_SHUTDOWN_LEGACY: u64 = 0x08;
+const EXT_SYSTEM_RESET: u64 = 0x53525354;

 primitive_enum! {
    pub enum Status: i64 {
@@ -52,6 +54,20 @@ impl From<i64> for SbiError {
    }
 }

+pub struct SbiResetMethod;
+
+impl Device for SbiResetMethod {
+    fn display_name(&self) -> &str {
+        "SBI reset"
+    }
+}
+
+impl ResetDevice for SbiResetMethod {
+    unsafe fn reset(&self) -> ! {
+        sbi_system_reset()
+    }
+}
+
 #[allow(clippy::too_many_arguments)]
 #[inline(always)]
 unsafe fn sbi_do_call(
@@ -107,6 +123,11 @@ pub fn sbi_set_timer(next_event: u64) {
    unsafe { sbi_do_call(EXT_TIME, 0x00, next_event, 0, 0, 0, 0, 0) }.ok();
 }

+pub fn sbi_system_reset() -> ! {
+    unsafe { sbi_do_call(EXT_SYSTEM_RESET, 0x00, 0x01, 0x00, 0, 0, 0, 0) }.ok();
+    unreachable!()
+}
+
 pub fn sbi_system_shutdown() -> ! {
    unsafe { sbi_do_call(EXT_SYSTEM_SHUTDOWN, 0x00, 0, 0, 0, 0, 0, 0) }.ok();
    unsafe { sbi_do_call(EXT_SYSTEM_SHUTDOWN_LEGACY, 0x00, 0, 0, 0, 0, 0, 0) }.ok();
@@ -1,7 +1,7 @@
 [package]
 name = "kernel-arch-x86"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 kernel-arch-interface.workspace = true
@@ -170,36 +170,40 @@ impl CpuFeatureSet for CpuFeatures {

 #[cfg(any(target_arch = "x86_64", rust_analyzer))]
 unsafe fn raw_cpuid(eax: u32, result: &mut [u32]) {
-    core::arch::asm!(
-        r#"
+    unsafe {
+        core::arch::asm!(
+            r#"
            push %rbx
            cpuid
            mov %ebx, {0:e}
            pop %rbx
        "#,
-        out(reg) result[0],
-        out("edx") result[1],
-        out("ecx") result[2],
-        in("eax") eax,
-        options(att_syntax)
-    );
+            out(reg) result[0],
+            out("edx") result[1],
+            out("ecx") result[2],
+            in("eax") eax,
+            options(att_syntax)
+        );
+    }
 }

 #[cfg(any(target_arch = "x86", rust_analyzer))]
 unsafe fn raw_cpuid(eax: u32, result: &mut [u32]) {
-    core::arch::asm!(
-        r#"
+    unsafe {
+        core::arch::asm!(
+            r#"
            push %ebx
            cpuid
            mov %ebx, {0:e}
            pop %ebx
        "#,
-        out(reg) result[0],
-        out("edx") result[1],
-        out("ecx") result[2],
-        in("eax") eax,
-        options(att_syntax)
-    );
+            out(reg) result[0],
+            out("edx") result[1],
+            out("ecx") result[2],
+            in("eax") eax,
+            options(att_syntax)
+        );
+    }
 }

 fn cpuid_features() -> (EcxFeatures, EdxFeatures, ExtEdxFeatures) {
@@ -225,42 +225,44 @@ mod imp {
            offset: gdt_addr,
        };

-        core::arch::asm!(
-            r#"
-        wbinvd
-        lgdt ({0})
+        unsafe {
+            core::arch::asm!(
+                r#"
+                wbinvd
+                lgdt ({0})

-        // Have to use iretq here
-        mov %rsp, %rcx
-        leaq 1f(%rip), %rax
+                // Have to use iretq here
+                mov %rsp, %rcx
+                leaq 1f(%rip), %rax

-        // SS:RSP
-        pushq $0x10
-        pushq %rcx
+                // SS:RSP
+                pushq $0x10
+                pushq %rcx

-        // RFLAGS
-        pushfq
+                // RFLAGS
+                pushfq

-        // CS:RIP
-        pushq $0x08
-        pushq %rax
-        iretq
-    1:
-        mov $0x10, %ax
-        mov %ax, %ds
-        mov %ax, %es
-        mov %ax, %fs
-        mov %ax, %gs
-        mov %ax, %ss
+                // CS:RIP
+                pushq $0x08
+                pushq %rax
+                iretq
+            1:
+                mov $0x10, %ax
+                mov %ax, %ds
+                mov %ax, %es
+                mov %ax, %fs
+                mov %ax, %gs
+                mov %ax, %ss

-        mov $0x28, %ax
-        ltr %ax
-    "#,
-            in(reg) &gdtr,
-            out("rax") _,
-            out("rcx") _,
-            options(att_syntax)
-        );
+                mov $0x28, %ax
+                ltr %ax
+            "#,
+                in(reg) &gdtr,
+                out("rax") _,
+                out("rcx") _,
+                options(att_syntax)
+            );
+        }
    }

    /// Initializes and loads the GDT data structure for the current CPU.
@@ -270,7 +272,7 @@ mod imp {
    /// Intended to be called once per each CPU during their early initialization.
    pub unsafe fn init() -> usize {
        let (gdt, tss) = create_gdt();
-        load_gdt(gdt);
+        unsafe { load_gdt(gdt) };
        (tss as *const Tss).addr()
    }
 }
@@ -76,7 +76,9 @@ impl IoPortAccess<u32> for IoPort<u32> {
 #[inline]
 pub unsafe fn inb(port: u16) -> u8 {
    let value: u8;
-    core::arch::asm!("inb %dx, %al", in("dx") port, out("al") value, options(att_syntax));
+    unsafe {
+        core::arch::asm!("inb %dx, %al", in("dx") port, out("al") value, options(att_syntax))
+    };
    value
 }

@@ -88,7 +90,9 @@ pub unsafe fn inb(port: u16) -> u8 {
 #[inline]
 pub unsafe fn inw(port: u16) -> u16 {
    let value: u16;
-    core::arch::asm!("inw %dx, %ax", in("dx") port, out("ax") value, options(att_syntax));
+    unsafe {
+        core::arch::asm!("inw %dx, %ax", in("dx") port, out("ax") value, options(att_syntax))
+    };
    value
 }

@@ -100,7 +104,9 @@ pub unsafe fn inw(port: u16) -> u16 {
 #[inline]
 pub unsafe fn inl(port: u16) -> u32 {
    let value: u32;
-    core::arch::asm!("inl %dx, %eax", in("dx") port, out("eax") value, options(att_syntax));
+    unsafe {
+        core::arch::asm!("inl %dx, %eax", in("dx") port, out("eax") value, options(att_syntax))
+    };
    value
 }

@@ -111,7 +117,9 @@ pub unsafe fn inl(port: u16) -> u32 {
 /// Provides direct access to port I/O, unsafe.
 #[inline]
 pub unsafe fn outb(port: u16, value: u8) {
-    core::arch::asm!("outb %al, %dx", in("dx") port, in("al") value, options(att_syntax));
+    unsafe {
+        core::arch::asm!("outb %al, %dx", in("dx") port, in("al") value, options(att_syntax))
+    };
 }

 /// Writes a 16-bit value to the I/O port.
@@ -121,7 +129,9 @@ pub unsafe fn outb(port: u16, value: u8) {
 /// Provides direct access to port I/O, unsafe.
 #[inline]
 pub unsafe fn outw(port: u16, value: u16) {
-    core::arch::asm!("outw %ax, %dx", in("dx") port, in("ax") value, options(att_syntax));
+    unsafe {
+        core::arch::asm!("outw %ax, %dx", in("dx") port, in("ax") value, options(att_syntax))
+    };
 }

 /// Writes a 32-bit value to the I/O port.
@@ -131,7 +141,9 @@ pub unsafe fn outw(port: u16, value: u16) {
 /// Provides direct access to port I/O, unsafe.
 #[inline]
 pub unsafe fn outl(port: u16, value: u32) {
-    core::arch::asm!("outl %eax, %dx", in("dx") port, in("eax") value, options(att_syntax));
+    unsafe {
+        core::arch::asm!("outl %eax, %dx", in("dx") port, in("eax") value, options(att_syntax))
+    };
 }

 #[inline]
@@ -1,7 +1,7 @@
 [package]
 name = "kernel-arch-x86_64"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -255,7 +255,7 @@ impl<K: KernelTableManager, PA: PhysicalMemoryAllocator<Address = PhysicalAddres
    type Context = TaskContextImpl<K, PA>;

    unsafe fn fork(&self, address_space: u64) -> Result<TaskContextImpl<K, PA>, Error> {
-        TaskContextImpl::from_syscall_frame(self, address_space)
+        unsafe { TaskContextImpl::from_syscall_frame(self, address_space) }
    }

    fn set_return_value(&mut self, value: u64) {
@@ -405,18 +405,20 @@ impl<K: KernelTableManager, PA: PhysicalMemoryAllocator<Address = PhysicalAddres
    }

    unsafe fn store_state(&self) {
-        FpuContext::store(self.fpu_context.get());
+        unsafe { FpuContext::store(self.fpu_context.get()) };
        // No need to save TSS/%cr3/%fs base back into the TCB, only the kernel
        // can make changes to those
    }

    unsafe fn load_state(&self) {
-        FpuContext::restore(self.fpu_context.get());
-        // When the task is interrupted from Ring 3, make the CPU load
-        // the top of its kernel stack
-        ArchitectureImpl::set_local_tss_sp0(self.tss_rsp0);
-        MSR_IA32_FS_BASE.set((*self.inner.get()).fs_base as u64);
-        CR3.set_address(self.cr3);
+        unsafe {
+            FpuContext::restore(self.fpu_context.get());
+            // When the task is interrupted from Ring 3, make the CPU load
+            // the top of its kernel stack
+            ArchitectureImpl::set_local_tss_sp0(self.tss_rsp0);
+            MSR_IA32_FS_BASE.set((*self.inner.get()).fs_base as u64);
+            CR3.set_address(self.cr3);
+        }
    }
 }

@@ -506,8 +508,10 @@ impl<K: KernelTableManager, PA: PhysicalMemoryAllocator<Address = PhysicalAddres
    }

    unsafe fn enter(&self) -> ! {
-        self.load_state();
-        __x86_64_enter_task(self.inner.get())
+        unsafe {
+            self.load_state();
+            __x86_64_enter_task(self.inner.get())
+        }
    }

    unsafe fn switch(&self, from: &Self) {
@@ -515,14 +519,18 @@ impl<K: KernelTableManager, PA: PhysicalMemoryAllocator<Address = PhysicalAddres
            return;
        }

-        from.store_state();
-        self.load_state();
-        __x86_64_switch_task(self.inner.get(), from.inner.get())
+        unsafe {
+            from.store_state();
+            self.load_state();
+            __x86_64_switch_task(self.inner.get(), from.inner.get())
+        }
    }

    unsafe fn switch_and_drop(&self, thread: *const ()) {
-        self.load_state();
-        __x86_64_switch_and_drop(self.inner.get(), thread)
+        unsafe {
+            self.load_state();
+            __x86_64_switch_and_drop(self.inner.get(), thread)
+        }
    }

    fn set_thread_pointer(&self, tp: usize) {
@@ -561,7 +569,7 @@ fn setup_common_context(builder: &mut StackBuilder, entry: usize) {
    builder.push(0); // %rbx
 }

-extern "C" {
+unsafe extern "C" {
    fn __x86_64_task_enter_kernel();
    fn __x86_64_task_enter_user();
    fn __x86_64_task_enter_from_fork();
@@ -103,7 +103,7 @@ impl Architecture for ArchitectureImpl {

    unsafe fn set_local_cpu(cpu: *mut ()) {
        MSR_IA32_KERNEL_GS_BASE.set(cpu as u64);
-        core::arch::asm!("wbinvd; swapgs");
+        unsafe { core::arch::asm!("wbinvd; swapgs") };
    }

    fn local_cpu() -> *mut () {
@@ -127,7 +127,7 @@ impl Architecture for ArchitectureImpl {
        )));
        cpu.this = cpu.deref_mut();

-        cpu.set_local();
+        unsafe { cpu.set_local() };
    }

    fn idle_task() -> extern "C" fn(usize) -> ! {
@@ -153,10 +153,12 @@ impl Architecture for ArchitectureImpl {

    unsafe fn set_interrupt_mask(mask: bool) -> bool {
        let old = Self::interrupt_mask();
-        if mask {
-            core::arch::asm!("cli");
-        } else {
-            core::arch::asm!("sti");
+        unsafe {
+            if mask {
+                core::arch::asm!("cli");
+            } else {
+                core::arch::asm!("sti");
+            }
        }
        old
    }
@@ -101,29 +101,33 @@ impl DevicePageTableLevel for L3DeviceMemory {
 }

 pub(super) unsafe fn setup(have_1gib_pages: bool) {
-    let phys = PhysicalAddress::from_usize(auto_lower_address(&raw const KERNEL_PDPT));
-    KERNEL_PML4[KERNEL_L0I] = PageEntry::table(phys, PageAttributes::WRITABLE);
+    unsafe {
+        let phys = PhysicalAddress::from_usize(auto_lower_address(&raw const KERNEL_PDPT));
+        KERNEL_PML4[KERNEL_L0I] = PageEntry::table(phys, PageAttributes::WRITABLE);

-    if have_1gib_pages {
-        for i in 0..IDENTITY_SIZE_L1 {
-            let phys = PhysicalAddress::from_usize(i * L1::SIZE);
-            KERNEL_PDPT[i] = PageEntry::<L1>::block(phys, PageAttributes::WRITABLE);
+        if have_1gib_pages {
+            for i in 0..IDENTITY_SIZE_L1 {
+                let phys = PhysicalAddress::from_usize(i * L1::SIZE);
+                KERNEL_PDPT[i] = PageEntry::<L1>::block(phys, PageAttributes::WRITABLE);
+            }
+        } else {
+            // TODO
+            ArchitectureImpl::halt();
        }
-    } else {
-        // TODO
-        ArchitectureImpl::halt();
-    }

-    // DEVICE_L1 -> Device L2 table
-    //               0..DEVICE_MAPPING_L3_COUNT -> Device L3 tables -> Device L3 pages
-    //               ..512                      -> Device L2 pages
-    for i in 0..DEVICE_MAPPING_L3_COUNT {
+        // DEVICE_L1 -> Device L2 table
+        //               0..DEVICE_MAPPING_L3_COUNT -> Device L3 tables -> Device L3 pages
+        //               ..512                      -> Device L2 pages
+        for i in 0..DEVICE_MAPPING_L3_COUNT {
+            let phys = PhysicalAddress::from_usize(auto_lower_address(
+                &raw const DEVICE_MEMORY.normal.0[i],
+            ));
+            DEVICE_MEMORY.large.0[i] = PageEntry::table(phys, PageAttributes::WRITABLE);
+        }
        let phys =
-            PhysicalAddress::from_usize(auto_lower_address(&raw const DEVICE_MEMORY.normal.0[i]));
-        DEVICE_MEMORY.large.0[i] = PageEntry::table(phys, PageAttributes::WRITABLE);
+            PhysicalAddress::from_usize(auto_lower_address(&raw const DEVICE_MEMORY.large.0));
+        KERNEL_PDPT[DEVICE_L1] = PageEntry::table(phys, PageAttributes::WRITABLE);
    }
-    let phys = PhysicalAddress::from_usize(auto_lower_address(&raw const DEVICE_MEMORY.large.0));
-    KERNEL_PDPT[DEVICE_L1] = PageEntry::table(phys, PageAttributes::WRITABLE);
 }

 pub(super) unsafe fn load() {
@@ -41,13 +41,17 @@ impl KernelTableManager for KernelTableManagerImpl {
    ) -> Result<RawDeviceMemoryMapping<Self>, Error> {
        let _lock = fixed::LOCK.lock();
        #[allow(static_mut_refs)]
-        fixed::DEVICE_MEMORY.map_device_pages(PhysicalAddress::from_u64(base), count, attrs)
+        unsafe {
+            fixed::DEVICE_MEMORY.map_device_pages(PhysicalAddress::from_u64(base), count, attrs)
+        }
    }

    unsafe fn unmap_device_pages(mapping: &RawDeviceMemoryMapping<Self>) {
        let _lock = fixed::LOCK.lock();
        #[allow(static_mut_refs)]
-        fixed::DEVICE_MEMORY.unmap_device_pages(mapping);
+        unsafe {
+            fixed::DEVICE_MEMORY.unmap_device_pages(mapping)
+        };
    }
 }

@@ -84,9 +88,11 @@ pub fn auto_lower_address<T>(pointer: *const T) -> usize {
 /// Unsafe, must only be called by BSP during its early init, must already be in "higher-half"
 #[inline(never)]
 pub unsafe fn init_fixed_tables(have_1gib_pages: bool, bsp: bool) {
-    fixed::setup(have_1gib_pages);
-    if bsp {
-        fixed::load();
+    unsafe {
+        fixed::setup(have_1gib_pages);
+        if bsp {
+            fixed::load();
+        }
    }
 }

@@ -95,5 +101,5 @@ pub unsafe fn init_fixed_tables(have_1gib_pages: bool, bsp: bool) {
 /// `address` must be page-aligned.
 #[inline]
 pub unsafe fn flush_tlb_entry(address: usize) {
-    core::arch::asm!("invlpg ({0})", in(reg) address, options(att_syntax));
+    unsafe { core::arch::asm!("invlpg ({0})", in(reg) address, options(att_syntax)) };
 }
@@ -85,8 +85,10 @@ impl<TA: TableAllocator> ProcessAddressSpaceManager<TA> for ProcessAddressSpaceI
    }

    unsafe fn clear(&mut self) {
-        self.l0
-            .drop_range::<TA>(0..((Self::UPPER_LIMIT_PFN * L3::SIZE).page_index::<L1>()));
+        unsafe {
+            self.l0
+                .drop_range::<TA>(0..((Self::UPPER_LIMIT_PFN * L3::SIZE).page_index::<L1>()));
+        }
    }
 }

@@ -220,7 +220,7 @@ impl<L: EntryLevel> PageTable<L> {
    /// Unsafe: the caller must ensure the provided reference is properly aligned and contains sane
    /// data.
    pub unsafe fn from_raw_slice_mut(data: &mut [PageEntry<L>; 512]) -> &mut Self {
-        core::mem::transmute(data)
+        unsafe { core::mem::transmute(data) }
    }

    /// Allocates a new page table, filling it with non-preset entries
@@ -243,8 +243,10 @@ impl<L: EntryLevel> PageTable<L> {
    ///
    /// The caller must ensure the table is no longer in use and is not referenced anymore.
    pub unsafe fn free<TA: TableAllocator>(this: PhysicalRefMut<Self, KernelTableManagerImpl>) {
-        let physical = this.as_physical_address();
-        TA::free_page_table(physical);
+        unsafe {
+            let physical = this.as_physical_address();
+            TA::free_page_table(physical);
+        }
    }

    // /// Returns the physical address of this table
@@ -303,25 +305,29 @@ where
    const FULL_RANGE: Range<usize> = 0..512;

    unsafe fn drop_range<TA: TableAllocator>(&mut self, range: Range<usize>) {
-        for index in range {
-            let entry = self[index];
+        unsafe {
+            for index in range {
+                let entry = self[index];

-            if let Some(table) = entry.as_table() {
-                let mut table_ref: PhysicalRefMut<PageTable<L::NextLevel>, KernelTableManagerImpl> =
-                    PhysicalRefMut::map(table);
+                if let Some(table) = entry.as_table() {
+                    let mut table_ref: PhysicalRefMut<
+                        PageTable<L::NextLevel>,
+                        KernelTableManagerImpl,
+                    > = PhysicalRefMut::map(table);

-                table_ref.drop_all::<TA>();
+                    table_ref.drop_all::<TA>();

-                TA::free_page_table(table);
-            } else if entry.is_present() {
-                // Memory must've been cleared beforehand, so no non-table entries must be present
-                panic!(
-                    "Expected a table containing only tables, got table[{}] = {:#x?}",
-                    index, entry.0
-                );
+                    TA::free_page_table(table);
+                } else if entry.is_present() {
+                    // Memory must've been cleared beforehand, so no non-table entries must be present
+                    panic!(
+                        "Expected a table containing only tables, got table[{}] = {:#x?}",
+                        index, entry.0
+                    );
+                }
+
+                self[index] = PageEntry::INVALID;
            }
-
-            self[index] = PageEntry::INVALID;
        }
    }
 }
@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_ahci"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 [dependencies]
@@ -115,7 +115,7 @@ impl AtaCommand for AtaIdentify {
    }

    unsafe fn into_response(self) -> Self::Response {
-        DmaBuffer::assume_init(self.buffer)
+        unsafe { DmaBuffer::assume_init(self.buffer) }
    }
 }

@@ -1,4 +1,4 @@
-#![feature(const_trait_impl, if_let_guard)]
+#![feature(const_trait_impl)]
 #![allow(missing_docs)]
 #![no_std]
 // TODO
@@ -1,15 +1,19 @@
-use alloc::sync::Arc;
+use alloc::{boxed::Box, sync::Arc};
+use async_trait::async_trait;
 use device_api::{
    clock::{ClockHandle, Hertz},
    device::{Device, DeviceInitContext},
-    i2c::{I2CAddress, I2CController},
+    i2c::{I2CAddress, I2CController, I2CMessage, I2CTransfer},
    interrupt::{InterruptHandler, IrqHandle, IrqVector},
 };
 use device_tree::driver::{Node, ProbeContext, device_tree_driver};
+use futures_util::task::AtomicWaker;
 use libk::{device::manager::DEVICE_REGISTRY, error::Error};
 use libk_mm::device::DeviceMemoryIo;
-use libk_util::{OneTimeInit, sync::spin_rwlock::IrqSafeRwLock};
+use libk_util::{OneTimeInit, event::BitmapEvent, sync::spin_rwlock::IrqSafeRwLock};
 use tock_registers::{
+    LocalRegisterCopy,
+    fields::FieldValue,
    interfaces::{ReadWriteable, Readable, Writeable},
    register_bitfields, register_structs,
    registers::ReadWrite,
@@ -56,6 +60,10 @@ register_structs! {
    }
 }

+struct I2CState {
+    status: BitmapEvent<AtomicWaker>,
+}
+
 struct I2C {
    name: &'static str,
    clock_frequency: Option<Hertz>,
@@ -63,87 +71,22 @@ struct I2C {
    clock: Option<ClockHandle>,
    regs: IrqSafeRwLock<DeviceMemoryIo<'static, Regs>>,
    index: OneTimeInit<u32>,
+    state: I2CState,
 }

-impl Regs {
-    fn start_transfer(&self, name: &str, buflen: u16, address: I2CAddress, read: bool) {
-        log::debug!(
-            "{}: start address={}, read={}, len={}",
-            name,
-            address,
-            read,
-            buflen
-        );
-
-        let address = address.as_8_bit().unwrap();
-        let read = if read { C::READ::SET } else { C::READ::CLEAR };
-
-        self.S.write(S::ERR::SET + S::DONE::SET);
-        self.DLEN.set(buflen as u32);
-        self.C.modify(C::ST::CLEAR + C::I2CEN::CLEAR);
-        self.A.set(address as u32);
-        self.C.modify(read + C::ST::SET + C::I2CEN::SET);
-    }
-
-    fn finish_transfer(&self, name: &str) -> Result<(), Error> {
-        log::debug!("{}: finish transfer", name);
-        let status = self.S.extract();
-        self.C.set(0);
-        if status.matches_all(S::ERR::SET) {
-            self.S.write(S::DONE::SET + S::ERR::SET);
-            return Err(Error::HostUnreachable);
-        }
-        if status.matches_all(S::DONE::SET) {
-            self.S.write(S::DONE::SET);
-        }
-
-        Ok(())
-    }
-
-    fn write_byte(&self, byte: u8) -> Result<bool, Error> {
-        loop {
-            let status = self.S.extract();
-            if status.matches_all(S::ERR::SET) {
-                self.C.write(C::CLEAR.val(1));
-                self.S.write(S::ERR::SET + S::DONE::SET);
-                // TODO better code
-                return Err(Error::HostUnreachable);
-            }
-            if status.matches_all(S::DONE::SET) {
-                self.C.set(0);
-                self.S.write(S::DONE::SET);
-                return Ok(false);
-            }
-            if status.matches_all(S::TXD::SET) {
-                self.FIFO.set(byte as u32);
-                return Ok(true);
-            }
-
-            core::hint::spin_loop();
+impl I2CState {
+    fn new() -> Self {
+        Self {
+            status: BitmapEvent::new(AtomicWaker::new()),
        }
    }
+}

-    fn read_byte(&self) -> Result<Option<u8>, Error> {
-        loop {
-            let status = self.S.extract();
-            if status.matches_all(S::ERR::SET) {
-                self.C.write(C::CLEAR.val(1));
-                self.S.write(S::ERR::SET + S::DONE::SET);
-                // TODO better code
-                return Err(Error::HostUnreachable);
-            }
-            if status.matches_all(S::DONE::SET) {
-                self.C.set(0);
-                self.S.write(S::DONE::SET);
-                return Ok(None);
-            }
-            if status.matches_all(S::RXD::SET) {
-                let val = self.FIFO.get() as u8;
-                return Ok(Some(val));
-            }
-
-            core::hint::spin_loop();
-        }
+// All of these are thread-unsafe, but I2C subsystem locks the peripheral by process
+impl I2C {
+    async fn wait_for_event(&self) -> LocalRegisterCopy<u32, S::Register> {
+        let event = self.state.status.wait().await;
+        LocalRegisterCopy::new(event as u32)
    }
 }

@@ -158,16 +101,13 @@ impl Device for I2C {

        let index = DEVICE_REGISTRY.i2c.register_bus(self.clone())?;
        self.index.init(index);
+
        Ok(())
    }

    unsafe fn init_irq(self: Arc<Self>) -> Result<(), Error> {
-        // TODO
-        let _ = &self.irq;
-        // self.irq.register(self.clone())?;
-        // self.irq.enable()?;
-        // let regs = self.regs.write();
-        // regs.C.modify(C::INTD::SET);
+        self.irq.register(self.clone())?;
+        self.irq.enable()?;
        Ok(())
    }

@@ -178,10 +118,26 @@ impl Device for I2C {

 impl InterruptHandler for I2C {
    fn handle_irq(self: Arc<Self>, _vector: IrqVector) -> bool {
-        todo!()
+        let regs = self.regs.write();
+        let event = regs.S.extract();
+        // log::info!("I2C irq {:#x}", event.get());
+        let mut clear = FieldValue::none();
+        if event.matches_all(S::RXR::SET) {
+            clear += C::INTR::CLEAR;
+        }
+        if event.matches_all(S::TXW::SET) {
+            clear += C::INTT::CLEAR;
+        }
+        if event.matches_all(S::DONE::SET) {
+            clear += C::INTD::CLEAR;
+        }
+        regs.C.modify(clear);
+        self.state.status.signal(event.get() as u64);
+        true
    }
 }

+#[async_trait]
 impl I2CController for I2C {
    fn bus_number(&self) -> u32 {
        *self.index.get()
@@ -217,47 +173,98 @@ impl I2CController for I2C {
        }
    }

-    fn i2c_write(&self, address: I2CAddress, buffer: &[u8]) -> Result<usize, Error> {
-        let buflen: u16 = buffer
-            .len()
-            .try_into()
-            .map_err(|_| Error::InvalidArgument)?;
-        let regs = self.regs.write();
-        // TODO DMA/interrupts
-        regs.start_transfer(self.name, buflen, address, false);
-        let mut bytes_written = 0;
-        // let mut done = false;
-        for &byte in buffer {
-            if regs.write_byte(byte)? {
-                bytes_written += 1;
-            } else {
-                break;
+    async fn i2c_transfer(
+        &self,
+        address: I2CAddress,
+        transfer: &mut I2CTransfer,
+    ) -> Result<usize, Error> {
+        // TODO validate transfer
+        let address = address.as_8_bit().ok_or(Error::NotImplemented)?;
+        let repeat_start = transfer.repeat_start;
+        let mut nbytes = 0;
+        let mut error = None;
+        for (i, message) in transfer.messages.iter_mut().enumerate() {
+            if i == 0 || repeat_start {
+                let (read, len) = match message {
+                    I2CMessage::Read(buffer) => (true, buffer.len()),
+                    I2CMessage::Write(buffer) => (false, buffer.len()),
+                };
+                // log::info!("{}: START {:#x} read={}", self.name, address, read);
+                let read = if read { C::READ::SET } else { C::READ::CLEAR };
+                let regs = self.regs.write();
+                regs.S.write(S::ERR::SET + S::DONE::SET);
+                regs.DLEN.set(len as u32);
+                regs.C.modify(C::ST::CLEAR);
+                regs.A.set(address as u32);
+                regs.C.modify(
+                    read + C::ST::SET + C::I2CEN::SET + C::INTD::SET + C::INTR::SET + C::INTT::SET,
+                );
            }
-        }
-        regs.finish_transfer(self.name)?;
-        Ok(bytes_written)
-    }

-    fn i2c_read(&self, address: I2CAddress, buffer: &mut [u8]) -> Result<usize, Error> {
-        let buflen: u16 = buffer
-            .len()
-            .try_into()
-            .map_err(|_| Error::InvalidArgument)?;
-        let regs = self.regs.write();
-        // TODO DMA/interrupts
-        regs.start_transfer(self.name, buflen, address, true);
-        let mut bytes_read = 0;
-        // let mut done = false;
-        for byte in buffer {
-            if let Some(val) = regs.read_byte()? {
-                *byte = val;
-                bytes_read += 1;
-            } else {
+            let mut pos = 0;
+            let status = loop {
+                let s = self.wait_for_event().await;
+                let regs = self.regs.write();
+                if s.matches_all(S::ERR::SET) || s.matches_all(S::DONE::SET) {
+                    break s;
+                }
+                match message {
+                    I2CMessage::Write(buffer) => {
+                        if s.matches_all(S::TXW::SET) {
+                            while regs.S.matches_all(S::TXD::SET) && pos < buffer.len() {
+                                let byte = buffer[pos];
+                                // log::info!("{}: tx {:#x}", self.name, byte);
+                                regs.FIFO.set(byte as u32);
+                                pos += 1;
+                                nbytes += 1;
+                            }
+                        }
+                        regs.C.modify(C::INTT::SET);
+                    }
+                    I2CMessage::Read(buffer) => {
+                        if s.matches_all(S::RXR::SET) {
+                            while regs.S.matches_all(S::RXD::SET) && pos < buffer.len() {
+                                let byte = regs.FIFO.get() as u8;
+                                // log::info!("{}: rx {:#x}", self.name, byte);
+                                buffer[pos] = byte;
+                                pos += 1;
+                                nbytes += 1;
+                            }
+                        }
+                        regs.C.modify(C::INTR::SET);
+                    }
+                }
+            };
+
+            // Finalize message
+            let regs = self.regs.write();
+            if status.matches_all(S::ERR::SET) {
+                regs.S.write(S::DONE::SET + S::ERR::SET);
+                error = Some(Error::HostUnreachable);
                break;
+            } else if status.matches_all(S::DONE::SET) {
+                regs.S.write(S::DONE::SET);
+            } else {
+                log::error!("{}: transfer finished without DONE or ERR set", self.name);
+                log::error!("{}: S = {:#x}", self.name, status.get());
+                todo!();
            }
        }
-        regs.finish_transfer(self.name)?;
-        Ok(bytes_read)
+
+        // Finish transfer
+        // log::info!(
+        //     "{}: finish xfer, error={:?}, nbytes={}",
+        //     self.name,
+        //     error,
+        //     nbytes
+        // );
+        let regs = self.regs.write();
+        regs.C.set(0);
+
+        match error {
+            Some(error) => Err(error),
+            None => Ok(nbytes),
+        }
    }
 }

@@ -279,7 +286,8 @@ device_tree_driver! {
                irq,
                clock,
                index: OneTimeInit::new(),
-                regs: IrqSafeRwLock::new(regs)
+                regs: IrqSafeRwLock::new(regs),
+                state: I2CState::new()
            });

            node.make_i2c_controller(i2c.clone());
@@ -1,4 +1,3 @@
-#![allow(unsafe_op_in_unsafe_fn)]
 #![no_std]

 extern crate alloc;
@@ -2,7 +2,8 @@ use alloc::{sync::Arc, vec::Vec};
 use device_api::{
    device::{Device, DeviceInitContext},
    interrupt::{
-        ExternalInterruptController, InterruptHandler, Irq, IrqHandle, IrqOptions, IrqVector,
+        ExternalInterruptController, InterruptHandler, Irq, IrqHandle, IrqOptions, IrqPriority,
+        IrqVector,
    },
 };
 use device_tree::{
@@ -96,13 +97,71 @@ struct HartContext {
 /// RISC-V Platform-Level Interrupt Controller (PLIC) device
 pub struct Plic {
    base: PhysicalAddress,
-    max_irqs: usize,
+    max_irq: usize,
    // hart id -> context map
    context_map: Vec<HartContext>,
    inner: OneTimeInit<Inner>,
 }

 impl Plic {
+    fn ensure_init(&self) -> Result<(), Error> {
+        self.inner.or_try_init_with(|| {
+            log::info!("Initialize RISC-V PLIC");
+
+            let common =
+                unsafe { DeviceMemoryIo::<CommonRegs>::map(self.base, Default::default())? };
+
+            for i in 0..self.max_irq {
+                common.PRIORITY[i].set(0);
+            }
+
+            for context in self.context_map.iter() {
+                let enable_offset = ENABLE_BASE + context.index * ENABLE_STRIDE;
+                let control_offset = CONTROL_BASE + context.index * CONTROL_STRIDE;
+
+                log::info!(
+                    "* HART {}: context {}, enable={:#x}, control={:#x}",
+                    context.hart,
+                    context.index,
+                    enable_offset,
+                    control_offset
+                );
+                let enable = unsafe {
+                    DeviceMemoryIo::<ContextEnableRegs>::map(
+                        self.base.add(enable_offset),
+                        Default::default(),
+                    )?
+                };
+                let control = unsafe {
+                    DeviceMemoryIo::<ContextControlRegs>::map(
+                        self.base.add(control_offset),
+                        Default::default(),
+                    )?
+                };
+
+                for i in 0..self.max_irq.div_ceil(32) {
+                    enable.ENABLE[i].set(0);
+                }
+                control.THRESHOLD.set(0);
+
+                context.context.init(Context {
+                    enable: IrqSafeRwLock::new(enable),
+                    control: IrqSafeRwLock::new(control),
+                    table: FixedInterruptTable::new(MAX_IRQS), // table: IrqSafeRwLock::new(FixedInterruptTable::new()),
+                });
+            }
+
+            // self.inner.init(Inner {
+            //     common: IrqSafeRwLock::new(common),
+            // });
+
+            Ok(Inner {
+                common: IrqSafeRwLock::new(common),
+            })
+        })?;
+        Ok(())
+    }
+
    fn hart_context(&self, hart: u32) -> Option<&HartContext> {
        self.context_map.iter().find(|c| c.hart == hart)
    }
@@ -116,8 +175,8 @@ impl Plic {
            log::error!("plic: irq cannot be zero");
            return Err(Error::InvalidArgument);
        }
-        if irq as usize >= self.max_irqs {
-            log::error!("plic: irq ({}) >= max_irqs ({})", irq, self.max_irqs);
+        if irq as usize > self.max_irq {
+            log::error!("plic: irq ({}) > max_irq ({})", irq, self.max_irq);
            return Err(Error::InvalidArgument);
        }
        Ok(irq)
@@ -153,11 +212,20 @@ impl ExternalInterruptController for Plic {
    fn register_irq(
        &self,
        irq: Irq,
-        _options: IrqOptions,
+        options: IrqOptions,
        handler: Arc<dyn InterruptHandler>,
    ) -> Result<(), Error> {
+        self.ensure_init()?;
        let bsp_hart_id = boot_hart_id() as u32;
        let irq = self.validate_irq(irq)?;
+        let prioval = match options.priority {
+            IrqPriority::Low => 3,
+            IrqPriority::Normal => 5,
+            IrqPriority::High => 7,
+        };
+        let inner = self.inner.get();
+        let common = inner.common.write();
+        common.PRIORITY[irq as usize - 1].set(prioval);
        let context = self
            .hart_context(bsp_hart_id)
            .ok_or(Error::InvalidArgument)
@@ -186,68 +254,24 @@ impl ExternalInterruptController for Plic {
        let control = context.control.write();
        // let table = context.table.read();

-        loop {
-            let irq = control.CLAIM.get();
-            if irq == 0 {
-                break;
-            }
-            let vector = IrqVector::Irq(Irq::External(irq));
-
-            if !context.table.handle_irq_line(irq as usize, vector) {
-                log::warn!("plic: no handler for IRQ #{irq}");
-            }
-
-            // Done servicing
-            control.CLAIM.set(irq);
+        let irq = control.CLAIM.get();
+        if irq == 0 {
+            return;
        }
+        let vector = IrqVector::Irq(Irq::External(irq));
+
+        if !context.table.handle_irq_line(irq as usize, vector) {
+            log::warn!("plic: no handler for IRQ #{irq}");
+        }
+
+        // Done servicing
+        control.CLAIM.set(irq);
    }
 }

 impl Device for Plic {
    unsafe fn init(self: Arc<Self>, _cx: DeviceInitContext) -> Result<(), Error> {
-        log::info!("Initialize RISC-V PLIC");
-
-        let common = DeviceMemoryIo::<CommonRegs>::map(self.base, Default::default())?;
-
-        for i in 0..self.max_irqs - 1 {
-            common.PRIORITY[i].set(3);
-        }
-
-        for context in self.context_map.iter() {
-            let enable_offset = ENABLE_BASE + context.index * ENABLE_STRIDE;
-            let control_offset = CONTROL_BASE + context.index * CONTROL_STRIDE;
-
-            log::info!(
-                "* HART {}: context {}, enable={:#x}, control={:#x}",
-                context.hart,
-                context.index,
-                enable_offset,
-                control_offset
-            );
-            let enable = DeviceMemoryIo::<ContextEnableRegs>::map(
-                self.base.add(enable_offset),
-                Default::default(),
-            )?;
-            let control = DeviceMemoryIo::<ContextControlRegs>::map(
-                self.base.add(control_offset),
-                Default::default(),
-            )?;
-
-            for i in 0..self.max_irqs.div_ceil(32) {
-                enable.ENABLE[i].set(0);
-            }
-            control.THRESHOLD.set(0);
-
-            context.context.init(Context {
-                enable: IrqSafeRwLock::new(enable),
-                control: IrqSafeRwLock::new(control),
-                table: FixedInterruptTable::new(MAX_IRQS), // table: IrqSafeRwLock::new(FixedInterruptTable::new()),
-            });
-        }
-
-        self.inner.init(Inner {
-            common: IrqSafeRwLock::new(common),
-        });
+        self.ensure_init()?;

        register_external_interrupt_controller(self);

@@ -289,7 +313,7 @@ device_tree_driver! {
            let ndev = node.prop_usize("riscv,ndev")?;
            let iext = node.property("interrupts-extended")?;

-            let max_irqs = MAX_IRQS.min(ndev);
+            let max_irq = MAX_IRQS.min(ndev);

            // Parse the context -> hart mapping, only select S-mode external interrupts
            let mut context_map = Vec::new();
@@ -301,6 +325,7 @@ device_tree_driver! {
                ) else {
                    continue;
                };
+                log::info!("Context #{context}: mode={mode:?}, hart={hart_id}");
                if mode != ContextMode::ExternalS {
                    continue;
                }
@@ -322,7 +347,7 @@ device_tree_driver! {

            let intc = Arc::new(Plic {
                base,
-                max_irqs,
+                max_irq,
                context_map,
                inner: OneTimeInit::new(),
            });
@@ -0,0 +1,20 @@
+[package]
+name = "ygg_driver_bsp_sifive"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+device-tree.workspace = true
+device-api.workspace = true
+yggdrasil-abi.workspace = true
+libk-mm.workspace = true
+libk-util.workspace = true
+libk.workspace = true
+ygg_driver_net_core.path = "../../net/core"
+
+static_assertions.workspace = true
+tock-registers.workspace = true
+log.workspace = true
+bytemuck.workspace = true
+futures-util.workspace = true
+async-trait.workspace = true
@@ -0,0 +1,190 @@
+use alloc::sync::Arc;
+use device_api::{
+    clock::{ClockController, ClockHandle, Hertz},
+    device::{Device, DeviceInitContext},
+};
+use device_tree::{
+    DeviceTreePropertyRead, TProp,
+    driver::{DeviceTreeClockController, Node, ProbeContext, device_tree_driver},
+};
+use libk::error::Error;
+use libk_mm::device::DeviceMemoryIo;
+use libk_util::{OneTimeInit, sync::IrqSafeSpinlock};
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_structs,
+    registers::ReadWrite,
+};
+
+use crate::pll::{PllCfg, WrpllData};
+
+const CLK_COREPLL: u32 = 0;
+const CLK_DDRPLL: u32 = 1;
+const CLK_GEMGXLPLL: u32 = 2;
+const CLK_TLCLK: u32 = 3;
+
+register_structs! {
+    Regs {
+        (0x000 => hfxosccfg: ReadWrite<u32>),
+        (0x004 => corepllcfg0: ReadWrite<u32, PllCfg::Register>),
+        (0x008 => _0),
+        (0x00C => ddrpllcfg0: ReadWrite<u32>),
+        (0x010 => ddrpllcfg1: ReadWrite<u32>),
+        (0x014 => _1),
+        (0x01C => gemgxlpllcfg0: ReadWrite<u32>),
+        (0x020 => gemgxlpllcfg1: ReadWrite<u32>),
+        (0x024 => coreclksel: ReadWrite<u32>),
+        (0x028 => deviceresetreg: ReadWrite<u32>),
+        (0x02C => _2),
+        (0x100 => @END),
+    }
+}
+
+struct Prci {
+    clk_osc: ClockHandle,
+    clk_rtc: ClockHandle,
+    regs: IrqSafeSpinlock<DeviceMemoryIo<'static, Regs>>,
+    init: OneTimeInit<()>,
+}
+
+impl Regs {
+    fn read_core_pll(&self) -> WrpllData {
+        let pll = self.corepllcfg0.extract();
+        let divr = pll.read(PllCfg::PLLR);
+        let divf = pll.read(PllCfg::PLLF);
+        let divq = pll.read(PllCfg::PLLQ);
+        WrpllData {
+            divq,
+            divr,
+            divf,
+            int_feedback: true,
+        }
+    }
+}
+
+impl Prci {
+    fn ensure_init(&self) {
+        // U-Boot should configure coreclk to 1GHz, but when booting
+        // in QEMU, there is not U-Boot stage, and some peripherals
+        // like PWM expect the clock to be configured this way. So
+        // this needs to be done manually here
+        self.init.or_init_with(|| {
+            let regs = self.regs.lock();
+            if regs.coreclksel.get() != 0 {
+                // coreclk configured to hfclk
+                // configure corepll to output 1GHz and switch to it
+                // divf = 150
+                // divr = 4
+                // divq = 1
+                regs.corepllcfg0.write(
+                    PllCfg::PLLF.val(150)
+                        + PllCfg::PLLR.val(4)
+                        + PllCfg::PLLQ.val(1)
+                        + PllCfg::PLLFSEBYPASS::SET,
+                );
+                while !regs.corepllcfg0.matches_all(PllCfg::PLLLOCK::SET) {
+                    core::hint::spin_loop();
+                }
+                regs.coreclksel.set(0);
+            }
+        });
+    }
+}
+
+impl Device for Prci {
+    unsafe fn init(self: Arc<Self>, _cx: DeviceInitContext) -> Result<(), Error> {
+        self.ensure_init();
+        if let Ok(coreclk) = self.clock_rate(Some(CLK_COREPLL)) {
+            log::info!("coreclk = {coreclk}");
+        }
+        Ok(())
+    }
+
+    fn display_name(&self) -> &str {
+        "sifive,fu540-c000-prci"
+    }
+}
+
+impl ClockController for Prci {
+    fn clock_rate(&self, clock: Option<u32>) -> Result<Hertz, Error> {
+        self.ensure_init();
+        let _ = &self.clk_rtc;
+        match clock {
+            Some(CLK_COREPLL) => {
+                let regs = self.regs.lock();
+                let hfclk = self.clk_osc.rate()?;
+                // == 0 -> use corepll
+                // == 1 -> use hfclk
+                let coreclksel = regs.coreclksel.get() != 0;
+                let coreclk = match coreclksel {
+                    true => hfclk,
+                    false => {
+                        let pll = regs.read_core_pll();
+                        pll.output_rate(hfclk)
+                    }
+                };
+                Ok(coreclk)
+            }
+            Some(CLK_TLCLK) => {
+                let coreclk = self.clock_rate(Some(CLK_COREPLL))?;
+                Ok(coreclk / 2)
+            }
+            Some(_) => todo!(),
+            None => Err(Error::InvalidArgument),
+        }
+    }
+
+    fn set_clock_rate(&self, _clock: Option<u32>, _rate: Hertz) -> Result<Hertz, Error> {
+        Err(Error::NotImplemented)
+    }
+
+    fn enable_clock(&self, clock: Option<u32>) -> Result<(), Error> {
+        self.ensure_init();
+        match clock {
+            Some(CLK_GEMGXLPLL) | Some(CLK_DDRPLL) | Some(CLK_COREPLL) => todo!(),
+            Some(CLK_TLCLK) => Ok(()),
+            _ => Err(Error::InvalidArgument),
+        }
+    }
+
+    fn disable_clock(&self, _clock: Option<u32>) -> Result<(), Error> {
+        Err(Error::NotImplemented)
+    }
+}
+
+impl DeviceTreeClockController for Prci {
+    fn map_clock(self: Arc<Self>, property: &TProp, offset: usize) -> Option<(ClockHandle, usize)> {
+        let clock = property.read_cell(offset, 1)? as u32;
+        Some((
+            ClockHandle {
+                parent: self.clone(),
+                clock: Some(clock),
+            },
+            1,
+        ))
+    }
+}
+
+device_tree_driver! {
+    compatible: ["sifive,fu540-c000-prci"],
+    driver: {
+        fn probe(&self, node: &Arc<Node>, context: &mut ProbeContext) -> Option<Arc<dyn Device>> {
+            let base = node.map_base(context, 0)?;
+            let clk_osc = node.clock(0)?;
+            let clk_rtc = node.clock(1)?;
+
+            let regs = unsafe { DeviceMemoryIo::map(base, Default::default()) }.ok()?;
+
+            let prci = Arc::new(Prci {
+                regs: IrqSafeSpinlock::new(regs),
+                clk_osc,
+                clk_rtc,
+                init: OneTimeInit::new()
+            });
+
+            node.make_clock_controller(prci.clone());
+
+            Some(prci)
+        }
+    }
+}
@@ -0,0 +1,171 @@
+use alloc::sync::Arc;
+use device_api::{
+    clock::{ClockController, ClockHandle, Hertz},
+    device::Device,
+};
+use device_tree::{
+    DeviceTreePropertyRead, TProp,
+    driver::{DeviceTreeClockController, Node, ProbeContext, device_tree_driver},
+};
+use libk::error::Error;
+use libk_mm::device::DeviceMemoryIo;
+use libk_util::sync::IrqSafeSpinlock;
+use tock_registers::{
+    interfaces::Readable,
+    register_structs,
+    registers::{ReadOnly, ReadWrite},
+};
+
+use crate::pll::{PllCfg, WrpllData};
+
+// const CLK_COREPLL: u32 = 0;
+// const CLK_DDRPLL: u32 = 1;
+// const CLK_GEMGXLPLL: u32 = 2;
+// const CLK_DVFSCOREPLL: u32 = 3;
+// const CLK_HFPCLKPLL: u32 = 4;
+// const CLK_CLTXPLL: u32 = 5;
+// const CLK_TLCLK: u32 = 6;
+const CLK_PCLK: u32 = 7;
+// const CLK_PCIE_AUX: u32 = 8;
+
+register_structs! {
+    Regs {
+        (0x00 => hfxosccfg: ReadWrite<u32>),
+        (0x04 => core_pllcfg: ReadWrite<u32>),
+        (0x08 => core_plloutdiv: ReadWrite<u32>),
+        (0x0C => ddr_pllcfg: ReadWrite<u32>),
+        (0x10 => ddr_plloutdiv: ReadWrite<u32>),
+        (0x14 => _0),
+        (0x1C => gemgxl_pllcfg: ReadWrite<u32, PllCfg::Register>),
+        (0x20 => gemgxl_plloutdiv: ReadWrite<u32>),
+        (0x24 => core_clk_sel_reg: ReadWrite<u32>),
+        (0x28 => devices_reset_n: ReadWrite<u32>),
+        (0x2C => clk_mux_status: ReadOnly<u32>),
+        (0x30 => _1),
+        (0x38 => dvfs_core_pllcfg: ReadWrite<u32>),
+        (0x3C => dvfs_core_plloutdiv: ReadWrite<u32>),
+        (0x40 => corepllsel: ReadWrite<u32>),
+        (0x44 => _2),
+        (0x50 => hfpclk_pllcfg: ReadWrite<u32, PllCfg::Register>),
+        (0x54 => hfpclk_plloutdiv: ReadWrite<u32>),
+        (0x58 => hfpclkpllsel: ReadWrite<u32>),
+        (0x5C => hfpclk_div_reg: ReadWrite<u32>),
+        (0x60 => _3),
+        (0xE0 => prci_plls: ReadOnly<u32>),
+        (0xE4 => _4),
+        (0x100 => @END),
+    }
+}
+
+struct Prci {
+    clk_hfclk: ClockHandle,
+    clk_rtcclk: ClockHandle,
+    regs: IrqSafeSpinlock<DeviceMemoryIo<'static, Regs>>,
+}
+
+impl Regs {
+    fn read_hfpclk_pll(&self) -> WrpllData {
+        let reg = self.hfpclk_pllcfg.extract();
+        let divr = reg.read(PllCfg::PLLR);
+        let divq = reg.read(PllCfg::PLLQ);
+        let divf = reg.read(PllCfg::PLLF);
+        WrpllData {
+            divq,
+            divr,
+            divf,
+            int_feedback: true,
+        }
+    }
+}
+
+impl Device for Prci {
+    fn display_name(&self) -> &str {
+        "sifive,fu740-c000-prci"
+    }
+}
+
+impl ClockController for Prci {
+    fn clock_rate(&self, clock: Option<u32>) -> Result<Hertz, Error> {
+        // hart frequency: coreclk, supplied either by corepll or dvfscorepll, selected by
+        // corepllsel
+        // hfpclkpll: clock for SPI, UART, GPIO, I2C, PWM
+        //
+        let _ = &self.clk_rtcclk;
+        let regs = self.regs.lock();
+        match clock {
+            Some(CLK_PCLK) => {
+                // PCLK calculation:
+                // pclk <- X / hfpclkdiv
+                // case [hfpclkpllsel]:
+                //  1: X <- (hfclk)
+                //  0: X <- hfpclkpllcfg/out & hfpclkpll
+                // hfpclkdiv <- [hfpclk_div_reg] + 2
+
+                let hfpclkpllsel = regs.hfpclkpllsel.get() & 1 != 0;
+                let hfpclk_div_reg = regs.hfpclk_div_reg.get() + 2;
+                let x = match hfpclkpllsel {
+                    true => self.clk_hfclk.rate()?,
+                    false => {
+                        let pclk_pll = regs.read_hfpclk_pll();
+                        pclk_pll.output_rate(self.clk_hfclk.rate()?)
+                    }
+                };
+                Ok(x / hfpclk_div_reg)
+            }
+            Some(_) => {
+                todo!();
+            }
+            None => {
+                todo!();
+            }
+        }
+    }
+
+    fn set_clock_rate(&self, _clock: Option<u32>, _rate: Hertz) -> Result<Hertz, Error> {
+        Err(Error::NotImplemented)
+    }
+
+    fn enable_clock(&self, _clock: Option<u32>) -> Result<(), Error> {
+        Ok(())
+    }
+
+    fn disable_clock(&self, _clock: Option<u32>) -> Result<(), Error> {
+        Err(Error::NotImplemented)
+    }
+}
+
+impl DeviceTreeClockController for Prci {
+    fn map_clock(self: Arc<Self>, property: &TProp, offset: usize) -> Option<(ClockHandle, usize)> {
+        let clock = property.read_cell(offset, 1)? as u32;
+        Some((
+            ClockHandle {
+                parent: self.clone(),
+                clock: Some(clock),
+            },
+            1,
+        ))
+    }
+}
+
+device_tree_driver! {
+    compatible: ["sifive,fu740-c000-prci"],
+    driver: {
+        fn probe(&self, node: &Arc<Node>, context: &mut ProbeContext) -> Option<Arc<dyn Device>> {
+            let base = node.map_base(context, 0)?;
+            let clk_hfclk = node.clock(0)?;
+            let clk_rtcclk = node.clock(1)?;
+
+            let regs = unsafe { DeviceMemoryIo::map(base, Default::default()) }.ok()?;
+
+            let prci = Arc::new(Prci {
+                regs: IrqSafeSpinlock::new(regs),
+                clk_hfclk,
+                clk_rtcclk
+            });
+
+            node.make_clock_controller(prci.clone());
+
+            Some(prci)
+        }
+    }
+}
@@ -0,0 +1,278 @@
+use core::{mem::MaybeUninit, time::Duration};
+
+use alloc::sync::Arc;
+use device_api::{
+    clock::ClockHandle,
+    device::{Device, DeviceInitContext},
+    dma::DmaAllocator,
+    interrupt::{InterruptHandler, IrqHandle, IrqVector},
+};
+use device_tree::driver::{
+    InitSequence, Node, ProbeContext, device_tree_driver, util::read_mac_address,
+};
+use futures_util::task::AtomicWaker;
+use libk::{
+    dma::DmaBuffer,
+    error::Error,
+    task::runtime::{self, with_timeout},
+};
+use libk_mm::device::DeviceMemoryIo;
+use libk_util::{OneTimeInit, event::BitmapEvent, sync::IrqSafeSpinlock};
+use tock_registers::{
+    LocalRegisterCopy,
+    interfaces::{ReadWriteable, Readable, Writeable},
+};
+use ygg_driver_net_core::{
+    RxPacket,
+    ephy::PhyAccess,
+    interface::{NetworkDevice, NetworkInterfaceType},
+    util::GenericQueue,
+};
+use yggdrasil_abi::net::{MacAddress, link::LinkState};
+
+use crate::ethernet::{
+    queue::Descriptor,
+    regs::{ControlRegs, Regs},
+};
+
+const RX_BUF_SIZE_MUL: usize = 64;
+
+mod queue;
+mod regs;
+
+// TODO multiqueue
+struct Ethernet {
+    // Device tree info
+    name: &'static str,
+    irq: IrqHandle,
+    clk_pclk: ClockHandle,
+    clk_hclk: ClockHandle,
+    local_mac_address: Option<MacAddress>,
+
+    // Memory/HW
+    // caps: Capabilities,
+    dma: OneTimeInit<Arc<dyn DmaAllocator>>,
+    control_regs: IrqSafeSpinlock<DeviceMemoryIo<'static, ControlRegs>>,
+    regs: IrqSafeSpinlock<DeviceMemoryIo<'static, Regs>>,
+
+    // Operation
+    queue: OneTimeInit<GenericQueue<Descriptor, Descriptor>>,
+    softirq: BitmapEvent<AtomicWaker>,
+    iface_id: OneTimeInit<u32>,
+}
+
+// bitflags! {
+//     pub struct CapFlags: u32 {
+//         const MACB_IS_GEM: bit 0;
+//     }
+// }
+
+// struct Capabilities {
+//     flags: CapFlags,
+//     queue_mask: u32,
+//     queue_count: usize,
+// }
+
+impl Ethernet {
+    fn probe(node: &Arc<Node>, context: &mut ProbeContext) -> Option<Arc<dyn Device>> {
+        let name = node.name().unwrap_or("gemgxl");
+        let irq = node.interrupt(0)?;
+        let clk_pclk = node.named_clock("pclk")?;
+        let clk_hclk = node.named_clock("hclk")?;
+        let base = node.map_base(context, 0)?;
+        let base_control = node.map_base(context, 1)?;
+        let local_mac_address = read_mac_address(node);
+
+        let regs = unsafe { DeviceMemoryIo::<Regs>::map(base, Default::default()) }.ok()?;
+        let control_regs = unsafe { DeviceMemoryIo::map(base_control, Default::default()) }.ok()?;
+
+        // let caps = regs.probe_capabilities();
+
+        let gem = Arc::new(Ethernet {
+            name,
+            clk_pclk,
+            clk_hclk,
+            irq,
+            local_mac_address,
+
+            // caps,
+            dma: OneTimeInit::new(),
+            regs: IrqSafeSpinlock::new(regs),
+            control_regs: IrqSafeSpinlock::new(control_regs),
+
+            queue: OneTimeInit::new(),
+            softirq: BitmapEvent::new(AtomicWaker::new()),
+            iface_id: OneTimeInit::new(),
+        });
+
+        context.sequence = Some(InitSequence::Late);
+
+        Some(gem)
+    }
+
+    async fn softirq(self: Arc<Self>) {
+        let iface = *self.iface_id.get();
+        let queue = self.queue.get();
+
+        loop {
+            let event_fut = self.softirq.wait();
+            let bits = match with_timeout(event_fut, Duration::from_millis(100)).await {
+                Ok(bits) => bits as u32,
+                Err(_) => {
+                    queue.consume_tx().ok();
+                    continue;
+                }
+            };
+            let status = LocalRegisterCopy::<_, regs::Interrupt::Register>::new(bits);
+
+            if status.matches_all(regs::Interrupt::RCOMP::SET) {
+                queue
+                    .consume_rx(&**self.dma.get(), None, |packet, _len| {
+                        let packet = RxPacket::new(packet, 0, iface);
+                        ygg_driver_net_core::receive_packet(packet).ok();
+                    })
+                    .ok();
+
+                let regs = self.regs.lock();
+                regs.interrupt_enable.write(regs::Interrupt::RCOMP::SET);
+            }
+            if status.matches_all(regs::Interrupt::TCOMP::SET) {
+                queue.consume_tx().ok();
+
+                let regs = self.regs.lock();
+                regs.interrupt_enable.write(regs::Interrupt::RCOMP::SET);
+            }
+            if status.matches_all(regs::Interrupt::LINK::SET) {
+                log::info!("Link status changed");
+                let regs = self.regs.lock();
+                regs.interrupt_enable.write(regs::Interrupt::LINK::SET);
+            }
+        }
+    }
+
+    fn start_xmit(&self, frame: DmaBuffer<[u8]>) -> Result<(), Error> {
+        let queue = self.queue.get();
+
+        queue.try_push_xmit(frame)?;
+
+        let regs = self.regs.lock();
+        regs.network_control
+            .modify(regs::NetworkControl::TSTART::SET);
+
+        Ok(())
+    }
+}
+
+impl Device for Ethernet {
+    unsafe fn init(self: Arc<Self>, cx: DeviceInitContext) -> Result<(), Error> {
+        let _ = (&self.clk_pclk, &self.clk_hclk, &self.control_regs);
+        log::info!("{}: hw address {:?}", self.name, self.local_mac_address);
+        // TODO enable clocks
+        let dma = self.dma.init(cx.dma_allocator);
+        let regs = self.regs.lock();
+
+        let queue = self.queue.init(GenericQueue::with_capacity(
+            &**dma,
+            256,
+            256,
+            queue::RX_BUFFER_SIZE,
+        )?);
+
+        let rx_queue_base = queue.rx_buffer_base().try_into_u32().unwrap();
+        let tx_queue_base = queue.tx_buffer_base().try_into_u32().unwrap();
+
+        regs.interrupt_disable.set(0xFFFFFFFF);
+
+        regs.rx_buffer_queue_base.set(rx_queue_base);
+        regs.tx_buffer_queue_base.set(tx_queue_base);
+        regs.dma_config.write(
+            regs::DmaConfig::RX_BUF_SIZE.val((queue::RX_BUFFER_SIZE / RX_BUF_SIZE_MUL) as _),
+        );
+
+        regs.network_control.modify(regs::NetworkControl::MPE::SET);
+
+        {
+            let phy = PhyAccess::new(&**regs, 0);
+            let phy_id = phy.id()?;
+            log::info!("{}: PHY {:04x}:{:04x}", self.name, phy_id.0, phy_id.1);
+            phy.setup_link(false, None)?;
+        }
+
+        regs.network_config.write(regs::NetworkConfig::PROMISC::SET);
+        regs.network_control
+            .modify(regs::NetworkControl::TE::SET + regs::NetworkControl::RE::SET);
+
+        // if (GEM_BFEXT(DAW64, gem_readl(...)))
+        //      hw_dma_cap |= HW_DMA_CAP_64B
+
+        regs.interrupt_enable.write(
+            regs::Interrupt::LINK::SET + regs::Interrupt::RCOMP::SET + regs::Interrupt::TCOMP::SET,
+        );
+
+        let iface =
+            ygg_driver_net_core::register_interface(NetworkInterfaceType::Ethernet, self.clone());
+        self.iface_id.init(iface.id());
+
+        runtime::spawn(self.clone().softirq())?;
+
+        Ok(())
+    }
+
+    unsafe fn init_irq(self: Arc<Self>) -> Result<(), Error> {
+        self.irq.register(self.clone())?;
+        self.irq.enable()?;
+        Ok(())
+    }
+
+    fn display_name(&self) -> &str {
+        self.name
+    }
+}
+
+impl NetworkDevice for Ethernet {
+    fn allocate_transmit_buffer(&self, len: usize) -> Result<DmaBuffer<[MaybeUninit<u8>]>, Error> {
+        DmaBuffer::new_uninit_slice(&**self.dma.get(), len)
+    }
+
+    fn transmit_buffer(&self, buffer: DmaBuffer<[u8]>) -> Result<(), Error> {
+        self.start_xmit(buffer)
+    }
+
+    fn packet_prefix_size(&self) -> usize {
+        0
+    }
+
+    fn read_hardware_address(&self) -> MacAddress {
+        // TODO from registers
+        self.local_mac_address.unwrap()
+    }
+
+    fn link_state(&self) -> LinkState {
+        self.regs.lock().link_state()
+    }
+}
+
+impl InterruptHandler for Ethernet {
+    fn handle_irq(self: Arc<Self>, _vector: IrqVector) -> bool {
+        const MASK: u32 = regs::Interrupt::RCOMP::SET.value
+            | regs::Interrupt::TCOMP::SET.value
+            | regs::Interrupt::LINK::SET.value;
+
+        let regs = self.regs.lock();
+        let status = regs.interrupt_status.get();
+        // Mask the IRQ and send it to softirq handler
+        regs.interrupt_disable.set(MASK & status);
+        self.softirq.signal(status as u64);
+
+        status != 0
+    }
+}
+
+device_tree_driver! {
+    compatible: ["sifive,fu540-c000-gem"],
+    driver: {
+        fn probe(&self, node: &Arc<Node>, context: &mut ProbeContext) -> Option<Arc<dyn Device>> {
+            Ethernet::probe(node, context)
+        }
+    }
+}
@@ -0,0 +1,87 @@
+use libk::{dma::BusAddress, error::Error};
+use ygg_driver_net_core::util::{GenericRxDescriptor, GenericTxDescriptor};
+
+pub const RX_BUFFER_SIZE: usize = 4096;
+
+static_assertions::const_assert_eq!(RX_BUFFER_SIZE % super::RX_BUF_SIZE_MUL, 0);
+static_assertions::const_assert_ne!(RX_BUFFER_SIZE / super::RX_BUF_SIZE_MUL, 0);
+
+#[derive(Clone, Copy, Debug)]
+#[repr(C)]
+pub(crate) struct Descriptor {
+    address: u32,
+    control: u32,
+}
+
+impl GenericTxDescriptor for Descriptor {
+    // USED = 0: owned by hardware
+    // USED = 1: owned by software
+    const EMPTY: Self = Self {
+        address: 0,
+        control: Self::DESC_1_USED,
+    };
+    const EMPTY_LAST: Self = Self {
+        address: 0,
+        control: Self::DESC_1_USED | Self::DESC_1_TX_WRAP,
+    };
+
+    fn consume(&mut self) -> Option<Result<(), Error>> {
+        if self.control & Self::DESC_1_USED != 0 && self.address != 0 {
+            Some(Ok(()))
+        } else {
+            None
+        }
+    }
+
+    fn setup_tx(
+        &mut self,
+        buffer_address: BusAddress,
+        size: usize,
+        index: usize,
+        capacity: usize,
+    ) -> Result<(), Error> {
+        let buffer_address = buffer_address.try_into_u32()?;
+        if !(8..8192).contains(&size) {
+            return Err(Error::InvalidArgument);
+        }
+        let mut control = size as u32 | Self::DESC_1_TX_LAST;
+        if index == capacity - 1 {
+            control |= Self::DESC_1_TX_WRAP;
+        }
+        self.address = buffer_address;
+        self.control = control;
+        Ok(())
+    }
+}
+
+impl GenericRxDescriptor for Descriptor {
+    fn consume(&mut self) -> Option<Result<usize, Error>> {
+        if self.address & Self::DESC_0_RX_OWNERSHIP != 0 {
+            Some(Ok((self.control & Self::LENGTH) as usize))
+        } else {
+            None
+        }
+    }
+
+    fn setup_rx(buffer_address: BusAddress, _size: usize, last: bool) -> Result<Self, Error> {
+        let mut address = buffer_address.try_into_u32()?;
+        if last {
+            address |= Self::DESC_0_RX_WRAP;
+        }
+        Ok(Self {
+            control: 0,
+            address,
+        })
+    }
+}
+
+impl Descriptor {
+    const DESC_1_USED: u32 = 1 << 31;
+    const LENGTH: u32 = 0x1FFF;
+
+    const DESC_1_TX_WRAP: u32 = 1 << 30;
+    const DESC_1_TX_LAST: u32 = 1 << 15;
+
+    const DESC_0_RX_OWNERSHIP: u32 = 1 << 0;
+    const DESC_0_RX_WRAP: u32 = 1 << 1;
+}
@@ -0,0 +1,197 @@
+use core::time::Duration;
+
+use libk::{error::Error, task::runtime::pwait};
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields, register_structs,
+    registers::{ReadOnly, ReadWrite, WriteOnly},
+};
+use ygg_driver_net_core::ephy::MdioBus;
+use yggdrasil_abi::net::link::LinkState;
+
+// use crate::ethernet::{CapFlags, Capabilities};
+
+register_structs! {
+    pub ControlRegs {
+        (0x00 => pub tx_clk_sel: ReadWrite<u32>),
+        (0x04 => _0),
+        (0x20 => pub control_status_speed_mode: ReadWrite<u32>),
+        (0x24 => _1),
+        (0x40 => @END),
+    }
+}
+
+register_bitfields! {
+    u32,
+    pub NetworkControl [
+        // Rx enable
+        RE          OFFSET(2)   NUMBITS(1)  [],
+        // Tx enable
+        TE          OFFSET(3)   NUMBITS(1)  [],
+        // MDIO enable
+        MPE         OFFSET(4)   NUMBITS(1)  [],
+        // Start Tx
+        TSTART      OFFSET(9)   NUMBITS(1)  [],
+        // Halt Tx
+        THALT       OFFSET(10)  NUMBITS(1)  [],
+    ],
+    pub NetworkConfig [
+        // Speed
+        SPD         OFFSET(0)   NUMBITS(1)  [],
+        // Full duplex
+        FD          OFFSET(1)   NUMBITS(1)  [],
+        PROMISC     OFFSET(4)   NUMBITS(1)  [],
+        // Gigabit mode enable
+        GBE         OFFSET(10)  NUMBITS(1)  [],
+    ],
+    pub NetworkStatus [
+        LINK        OFFSET(0)   NUMBITS(1)  [],
+        MDIO_IDLE   OFFSET(2)   NUMBITS(1)  [],
+    ],
+    pub DmaConfig [
+        RX_BUF_SIZE OFFSET(16)  NUMBITS(8)  [],
+    ],
+    pub Interrupt [
+        // Rx complete
+        RCOMP       OFFSET(1)   NUMBITS(1)  [],
+        // Tx complete
+        TCOMP       OFFSET(7)   NUMBITS(1)  [],
+        // Link change
+        LINK        OFFSET(8)   NUMBITS(1)  [],
+    ],
+    pub PhyMaintenance [
+        DATA        OFFSET(0)   NUMBITS(16) [],
+        CODE        OFFSET(16)  NUMBITS(2)  [],
+        REGA        OFFSET(18)  NUMBITS(5)  [],
+        PHYA        OFFSET(23)  NUMBITS(5)  [],
+        RW          OFFSET(28)  NUMBITS(2)  [
+            Read = 0b10,
+            Write = 0b01,
+        ],
+        SOF         OFFSET(30)  NUMBITS(1)  [],
+    ],
+    pub ModuleId [
+        IDNUM       OFFSET(16)  NUMBITS(12) [],
+        REV         OFFSET(0)   NUMBITS(16) [],
+    ]
+}
+
+register_structs! {
+    pub Regs {
+        (0x000 => pub network_control: ReadWrite<u32, NetworkControl::Register>),
+        (0x004 => pub network_config: ReadWrite<u32, NetworkConfig::Register>),
+        (0x008 => pub network_status: ReadOnly<u32, NetworkStatus::Register>),
+        (0x00C => pub user_io: ReadWrite<u32>),
+        (0x010 => pub dma_config: ReadWrite<u32, DmaConfig::Register>),
+        (0x014 => pub transmit_status: ReadWrite<u32>),
+        (0x018 => pub rx_buffer_queue_base: ReadWrite<u32>),
+        (0x01C => pub tx_buffer_queue_base: ReadWrite<u32>),
+        (0x020 => pub rx_status: ReadWrite<u32>),
+        (0x024 => pub interrupt_status: ReadWrite<u32, Interrupt::Register>),
+        (0x028 => pub interrupt_enable: WriteOnly<u32, Interrupt::Register>),
+        (0x02C => pub interrupt_disable: WriteOnly<u32, Interrupt::Register>),
+        (0x030 => pub interrupt_mask: ReadOnly<u32, Interrupt::Register>),
+        (0x034 => pub phy_maintenance: ReadWrite<u32, PhyMaintenance::Register>),
+        (0x038 => pub rx_pause_quantum: ReadOnly<u32>),
+        (0x03C => pub tx_pause_quantum: ReadWrite<u32>),
+        (0x040 => pub tx_partial_store_fwd: ReadWrite<u32>),
+        (0x044 => pub rx_partial_store_fwd: ReadWrite<u32>),
+        (0x048 => _0),
+        (0x080 => pub hash_register_bottom: ReadWrite<u32>),
+        (0x084 => pub hash_register_top: ReadWrite<u32>),
+        (0x088 => pub specific_address_x: [ReadWrite<u32>; 8]),
+        (0x0A8 => pub type_id_match: [ReadWrite<u32>; 4]),
+        (0x0B8 => pub wake_on_lan: ReadWrite<u32>),
+        (0x0BC => pub ipg_stretch: ReadWrite<u32>),
+        (0x0C0 => pub stacked_vlan: ReadWrite<u32>),
+        (0x0C4 => pub tx_pfc_pause: ReadWrite<u32>),
+        (0x0C8 => pub specific_address_mask: [ReadWrite<u32>; 2]),
+        (0x0D0 => pub rx_buffer_ahb_mask: ReadWrite<u32>),
+        (0x0D4 => pub ptp_rx_unicast_dst_ip: ReadWrite<u32>),
+        (0x0D8 => pub ptp_tx_unicast_dst_ip: ReadWrite<u32>),
+        (0x0DC => pub tsu_timer_cval_nanos: ReadWrite<u32>),
+        (0x0E0 => pub tsu_timer_cval_sec: ReadWrite<u32>),
+        (0x0E4 => _1),
+        (0x0FC => pub module_id: ReadOnly<u32, ModuleId::Register>),
+        (0x100 => _2),
+        (0x200 => pub pcs_control: ReadWrite<u32>),
+        (0x204 => pub pcs_status: ReadOnly<u32>),
+        (0x208 => pub pcs_phy_id_upper: ReadOnly<u32>),
+        (0x20C => pub pcs_phy_id_lower: ReadOnly<u32>),
+        (0x210 => pub pcs_aneg_adv: ReadWrite<u32>),
+        (0x214 => pub pcs_aneg_link_ability: ReadOnly<u32>),
+        (0x218 => pub pcs_aneg_expansion: ReadOnly<u32>),
+        (0x21C => pub pcs_aneg_next_page: ReadWrite<u32>),
+        (0x220 => pub pcs_aneg_link_next_page: ReadOnly<u32>),
+        (0x224 => _3),
+        (0x280 => pub design_config_1: ReadOnly<u32>),
+        (0x284 => pub design_config_2: ReadOnly<u32>),
+        (0x288 => pub design_config_3: ReadOnly<u32>),
+        (0x28C => pub design_config_4: ReadOnly<u32>),
+        (0x290 => pub design_config_5: ReadOnly<u32>),
+        (0x294 => pub design_config_6: ReadOnly<u32>),
+        (0x298 => pub design_config_7: ReadOnly<u32>),
+        (0x29C => _4),
+        (0x400 => @END),
+    }
+}
+
+impl Regs {
+    // pub fn probe_capabilities(&self) -> Capabilities {
+    //     let mut flags = CapFlags::empty();
+    //     let mut queue_mask = 0x1;
+    //     let mut queue_count = 1;
+    //     let module_id = self.module_id.read(ModuleId::IDNUM);
+
+    //     if module_id >= 0x2 {
+    //         flags |= CapFlags::MACB_IS_GEM;
+
+    //         queue_mask |= self.design_config_6.get() & 0xFF;
+    //         queue_count = queue_mask.count_ones() as usize;
+    //     }
+
+    //     Capabilities {
+    //         flags,
+    //         queue_mask,
+    //         queue_count,
+    //     }
+    // }
+
+    pub fn link_state(&self) -> LinkState {
+        todo!()
+    }
+
+    fn wait_mdio_idle(&self, timeout: Duration) -> Result<(), Error> {
+        pwait(timeout, Duration::from_millis(20), || {
+            self.network_status
+                .matches_all(NetworkStatus::MDIO_IDLE::SET)
+        })
+    }
+}
+impl MdioBus for Regs {
+    fn mii_read(&self, phyaddr: u8, regaddr: u8) -> Result<u16, Error> {
+        self.wait_mdio_idle(Duration::from_secs(1))?;
+        self.phy_maintenance.write(
+            PhyMaintenance::CODE.val(2)
+                + PhyMaintenance::PHYA.val(phyaddr as _)
+                + PhyMaintenance::REGA.val(regaddr as _)
+                + PhyMaintenance::SOF.val(1)
+                + PhyMaintenance::RW::Read,
+        );
+        self.wait_mdio_idle(Duration::from_secs(1))?;
+        let value = self.phy_maintenance.read(PhyMaintenance::DATA);
+        Ok(value as u16)
+    }
+    fn mii_write(&self, phyaddr: u8, regaddr: u8, value: u16) -> Result<(), Error> {
+        self.wait_mdio_idle(Duration::from_secs(1))?;
+        self.phy_maintenance.write(
+            PhyMaintenance::CODE.val(2)
+                + PhyMaintenance::PHYA.val(phyaddr as _)
+                + PhyMaintenance::REGA.val(regaddr as _)
+                + PhyMaintenance::SOF.val(1)
+                + PhyMaintenance::DATA.val(value as _)
+                + PhyMaintenance::RW::Write,
+        );
+        self.wait_mdio_idle(Duration::from_secs(1))
+    }
+}
@@ -0,0 +1,523 @@
+use alloc::{boxed::Box, sync::Arc};
+use async_trait::async_trait;
+use device_api::{
+    clock::{ClockHandle, Hertz, IntoHertz},
+    device::{Device, DeviceInitContext},
+    i2c::{I2CAddress, I2CController, I2CMessage, I2CTransfer},
+    interrupt::{InterruptHandler, IrqHandle, IrqVector},
+};
+use device_tree::driver::{Node, ProbeContext, device_tree_driver};
+use futures_util::task::AtomicWaker;
+use libk::{block, device::manager::DEVICE_REGISTRY, error::Error};
+use libk_mm::device::DeviceMemoryIo;
+use libk_util::{OneTimeInit, event::BitmapEvent, sync::IrqSafeSpinlock};
+use tock_registers::{
+    LocalRegisterCopy,
+    interfaces::{ReadWriteable, Readable, Writeable},
+    register_bitfields, register_structs,
+    registers::{Aliased, ReadWrite},
+};
+use yggdrasil_abi::io::device::i2c::I2CMasterInfo;
+
+const CMD_START: u32 = 0x91;
+const CMD_STOP: u32 = 0x41;
+const CMD_WRITE: u32 = 0x11;
+const CMD_READ_ACK: u32 = 0x21;
+const CMD_READ_NACK: u32 = 0x29;
+const CMD_IACK: u32 = 0x01;
+
+register_bitfields! {
+    u32,
+    CTR [
+        EN      OFFSET(7)   NUMBITS(1)  [],
+        IEN     OFFSET(6)   NUMBITS(1)  [],
+    ],
+    SR [
+        RXACK   OFFSET(7)   NUMBITS(1)  [],
+        BUSY    OFFSET(6)   NUMBITS(1)  [],
+        AL      OFFSET(5)   NUMBITS(1)  [],
+        TIP     OFFSET(1)   NUMBITS(1)  [],
+        IF      OFFSET(0)   NUMBITS(1)  [],
+    ],
+}
+
+register_structs! {
+    #[allow(non_snake_case)]
+    Regs {
+        (0x000 => PRER_LO: ReadWrite<u32>),
+        (0x004 => PRER_HI: ReadWrite<u32>),
+        (0x008 => CTR: ReadWrite<u32, CTR::Register>),
+        (0x00C => TXR_RXR: ReadWrite<u32>),
+        (0x010 => CR_SR: Aliased<u32, SR::Register, ()>),
+        (0x014 => _0),
+        (0x020 => @END),
+    }
+}
+
+struct AbortGuard<'a> {
+    i2c: &'a I2C,
+    abort: bool,
+}
+
+impl<'a> AbortGuard<'a> {
+    pub fn new(i2c: &'a I2C) -> Self {
+        Self { i2c, abort: true }
+    }
+
+    pub fn consume(mut self) {
+        self.abort = false;
+    }
+}
+
+impl Drop for AbortGuard<'_> {
+    fn drop(&mut self) {
+        if self.abort {
+            block!(self.i2c.finish_transfer(Err(Error::Interrupted)).await).ok();
+        }
+    }
+}
+
+pub struct I2C {
+    name: &'static str,
+    clock: ClockHandle,
+    irq: IrqHandle,
+    regs: IrqSafeSpinlock<DeviceMemoryIo<'static, Regs>>,
+    index: OneTimeInit<u32>,
+    sr: BitmapEvent<AtomicWaker>,
+}
+
+impl Regs {
+    fn set_clock_rate(&self, input_rate: Hertz, clock_rate: Hertz) -> Result<Hertz, Error> {
+        let divider = Hertz::divider(input_rate / 5, clock_rate).ok_or(Error::InvalidArgument)?;
+        if divider == 0 || divider > 0xFFFF {
+            return Err(Error::InvalidArgument);
+        }
+        log::info!("input_rate = {input_rate}, desired = {clock_rate}, divider = {divider}");
+        let divider = divider - 1;
+        self.PRER_LO.set(divider & 0xFF);
+        self.PRER_HI.set(divider >> 8);
+        let real_rate = input_rate / (5 * (divider + 1));
+        Ok(real_rate)
+    }
+}
+
+impl I2C {
+    async fn wait_for_event(&self) -> LocalRegisterCopy<u32, SR::Register> {
+        let value = self.sr.wait().await;
+        LocalRegisterCopy::new(value as u32)
+    }
+
+    async fn finish_transfer(&self, status: Result<usize, Error>) -> Result<usize, Error> {
+        if status == Err(Error::Interrupted) {
+            log::warn!("{}: transfer aborted", self.name);
+
+            let regs = self.regs.lock();
+            let stopped = {
+                if regs.CR_SR.matches_all(SR::TIP::CLEAR) {
+                    true
+                } else {
+                    false
+                }
+            };
+
+            if !stopped {
+                regs.CTR.modify(CTR::IEN::SET);
+                drop(regs);
+
+                loop {
+                    let sr = self.wait_for_event().await;
+                    if sr.matches_all(SR::TIP::CLEAR) {
+                        break;
+                    }
+                    let regs = self.regs.lock();
+                    regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+                }
+            }
+        }
+        // Generate stop condition
+        {
+            let regs = self.regs.lock();
+            regs.CR_SR.set(CMD_STOP);
+            regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+        }
+
+        loop {
+            let sr = self.wait_for_event().await;
+            if sr.matches_all(SR::BUSY::CLEAR) {
+                break;
+            }
+            let regs = self.regs.lock();
+            regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+        }
+
+        let regs = self.regs.lock();
+        regs.CTR.modify(CTR::IEN::CLEAR); // Mask IRQs
+        regs.CR_SR.set(CMD_IACK);
+
+        match status {
+            Ok(count) => Ok(count),
+            Err(err) => Err(err),
+        }
+    }
+}
+
+impl Device for I2C {
+    unsafe fn init(self: Arc<Self>, _cx: DeviceInitContext) -> Result<(), Error> {
+        let input_clk = self.clock.rate()?;
+        let regs = self.regs.lock();
+        regs.CTR.set(0);
+        regs.set_clock_rate(input_clk, 100u64.khz())?;
+        regs.CTR.write(CTR::EN::SET);
+        regs.CR_SR.set(CMD_IACK);
+        let index = DEVICE_REGISTRY.i2c.register_bus(self.clone())?;
+        self.index.init(index);
+        Ok(())
+    }
+
+    unsafe fn init_irq(self: Arc<Self>) -> Result<(), Error> {
+        self.irq.register(self.clone())?;
+        self.irq.enable()?;
+        Ok(())
+    }
+
+    fn display_name(&self) -> &str {
+        self.name
+    }
+}
+
+impl InterruptHandler for I2C {
+    fn handle_irq(self: Arc<Self>, _vector: IrqVector) -> bool {
+        let regs = self.regs.lock();
+        let status = regs.CR_SR.extract();
+        self.sr.signal(status.get() as u64);
+        regs.CTR.modify(CTR::IEN::CLEAR);
+        true
+    }
+}
+
+#[async_trait]
+impl I2CController for I2C {
+    fn bus_number(&self) -> u32 {
+        *self.index.get()
+    }
+
+    fn child_number(&self) -> Option<u32> {
+        None
+    }
+
+    fn capabilities(&self) -> I2CMasterInfo {
+        let scl_max = self.clock.rate().expect("Couldn't get input clock rate") / 5;
+        I2CMasterInfo {
+            max_speed_hz: scl_max.0 as u32,
+            supports_10bit_addresses: true,
+        }
+    }
+
+    async fn i2c_transfer(
+        &self,
+        address: I2CAddress,
+        transfer: &mut I2CTransfer,
+    ) -> Result<usize, Error> {
+        // TODO validate transfer
+        let address = address.as_8_bit().ok_or(Error::NotImplemented)?;
+        let repeat_start = transfer.repeat_start;
+        let mut nbytes = 0;
+        let mut error = None;
+        let mut abort = None;
+        for (i, message) in transfer.messages.iter_mut().enumerate() {
+            let (read, buffer_len) = match message {
+                I2CMessage::Read(buffer) => (true, buffer.len()),
+                I2CMessage::Write(buffer) => (false, buffer.len()),
+            };
+
+            if i == 0 || repeat_start {
+                //log::info!("{}: START {:#x} read={}", self.name, address, read);
+                let read_bit = if read { 1 << 0 } else { 0 << 0 };
+                let regs = self.regs.lock();
+                regs.TXR_RXR.set(((address as u32) << 1) | read_bit);
+                regs.CR_SR.set(CMD_START);
+                regs.CTR.modify(CTR::IEN::SET);
+                if abort.is_none() {
+                    abort = Some(AbortGuard::new(self));
+                }
+            }
+
+            let mut pos = 0;
+            let mut start = true;
+            loop {
+                if pos == buffer_len {
+                    break;
+                }
+                let sr = self.wait_for_event().await;
+                let regs = self.regs.lock();
+                if sr.matches_all(SR::AL::SET) {
+                    error = Some(Error::HostUnreachable);
+                    break;
+                }
+
+                match message {
+                    I2CMessage::Read(buffer) => {
+                        if pos == 0 && sr.matches_all(SR::RXACK::SET) {
+                            error = Some(Error::HostUnreachable);
+                            break;
+                        }
+                        if start {
+                            regs.CR_SR.set(CMD_READ_ACK);
+                            start = false;
+                        } else if sr.matches_all(SR::TIP::CLEAR) {
+                            let byte = regs.TXR_RXR.get() as u8;
+                            //log::info!("{}: rx {:#x}", self.name, byte);
+                            buffer[pos] = byte;
+                            pos += 1;
+                            nbytes += 1;
+                            if pos >= buffer.len() {
+                                regs.CR_SR.set(CMD_READ_NACK);
+                            } else {
+                                regs.CR_SR.set(CMD_READ_ACK);
+                            }
+                        }
+                    }
+                    I2CMessage::Write(buffer) => {
+                        if sr.matches_all(SR::RXACK::SET) {
+                            error = Some(Error::HostUnreachable);
+                            break;
+                        }
+                        regs.TXR_RXR.set(buffer[pos] as u32);
+                        //log::info!("{}: tx {:#x}", self.name, buffer[pos]);
+                        pos += 1;
+                        nbytes += 1;
+                        regs.CR_SR.set(CMD_WRITE);
+                    }
+                }
+                regs.CTR.modify(CTR::IEN::SET);
+            }
+
+            if error.is_some() {
+                break;
+            }
+
+            {
+                let regs = self.regs.lock();
+                if regs.CR_SR.matches_all(SR::TIP::CLEAR) {
+                    regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+                    continue;
+                }
+
+                regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+            }
+
+            loop {
+                let sr = self.wait_for_event().await;
+                if sr.matches_all(SR::TIP::CLEAR) {
+                    break;
+                }
+                let regs = self.regs.lock();
+                regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+            }
+        }
+
+        // Generate stop condition
+        {
+            //log::info!("{}: STOP", self.name);
+            let regs = self.regs.lock();
+            regs.CR_SR.set(CMD_STOP);
+            regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+        }
+
+        loop {
+            let sr = self.wait_for_event().await;
+            if sr.matches_all(SR::BUSY::CLEAR) {
+                break;
+            }
+            let regs = self.regs.lock();
+            regs.CTR.modify(CTR::IEN::SET); // Reenable IRQs
+        }
+
+        if let Some(abort) = abort.take() {
+            abort.consume();
+        }
+
+        let regs = self.regs.lock();
+        regs.CTR.modify(CTR::IEN::CLEAR); // Mask IRQs
+        regs.CR_SR.set(CMD_IACK);
+
+        // log::info!(
+        //     "{}: finish xfer, error={:?}, nbytes={}",
+        //     self.name,
+        //     error,
+        //     nbytes
+        // );
+        match error {
+            Some(err) => Err(err),
+            None => Ok(nbytes),
+        }
+    }
+    // async fn i2c_read(&self, address: I2CAddress, buffer: &mut [u8]) -> Result<usize, Error> {
+    //     self.start_transfer(address, true)?;
+    //     let mut pos = 0;
+    //     let status = loop {
+    //         if pos >= buffer.len() {
+    //             break Ok(pos);
+    //         }
+    //         let sr = self.wait_for_event().await;
+    //         let regs = self.regs.lock();
+    //         if sr.matches_all(SR::RXACK::SET) || sr.matches_all(SR::AL::SET) {
+    //             break Err(sr);
+    //         }
+    //     };
+    //     self.finish_transfer(status).await
+    // }
+
+    // async fn i2c_write(&self, address: I2CAddress, buffer: &[u8]) -> Result<usize, Error> {
+    //     self.start_transfer(address, false)?;
+    //     let mut pos = 0;
+    //     let status = loop {
+    //         if pos >= buffer.len() {
+    //             break Ok(pos);
+    //         }
+    //         let sr = self.wait_for_event().await;
+    //         let regs = self.regs.lock();
+    //         if sr.matches_all(SR::RXACK::SET) || sr.matches_all(SR::AL::SET) {
+    //             break Err(sr);
+    //         }
+    //     };
+    //     self.finish_transfer(status).await
+    // }
+
+    // fn i2c_read(&self, address: I2CAddress, buffer: &mut [u8]) -> Result<usize, Error> {
+    //     let address = address.as_8_bit().ok_or(Error::NotImplemented)?;
+    //     let regs = self.regs.lock();
+    //     log::info!(":::: start {:#x} read", address);
+    //     regs.poll_wait(SR::BUSY::SET);
+    //     regs.TXR_RXR.set(((address as u32) << 1) | 1);
+    //     regs.CR_SR.set(CMD_START);
+
+    //     let mut read = 0;
+    //     let mut error = None;
+    //     let mut start = true;
+    //     loop {
+    //         let sr = regs.poll_wait(SR::TIP::SET);
+    //         if read == buffer.len() {
+    //             break;
+    //         }
+    //         if sr.matches_all(SR::AL::SET) {
+    //             error = Some(Error::WouldBlock);
+    //             break;
+    //         }
+    //         if sr.matches_all(SR::RXACK::SET) {
+    //             error = Some(Error::DoesNotExist);
+    //             break;
+    //         }
+
+    //         if !start {
+    //             let val = regs.TXR_RXR.get() as u8;
+    //             buffer[read] = val;
+    //             read += 1;
+    //             if read >= buffer.len() {
+    //                 log::info!(":::: read_ack {:02x}", val);
+    //                 regs.CR_SR.set(CMD_READ_NACK);
+    //             } else {
+    //                 log::info!(":::: read {:02x}", val);
+    //                 regs.CR_SR.set(CMD_READ_ACK);
+    //             }
+    //         } else {
+    //             log::info!(":::: begin read");
+    //             regs.CR_SR.set(CMD_READ);
+    //             start = false;
+    //         }
+    //     }
+
+    //     log::info!(":::: stop {:#x}", address);
+    //     // Generate stop condition
+    //     regs.CR_SR.set(CMD_STOP);
+    //     regs.poll_wait(SR::BUSY::SET);
+    //     regs.CR_SR.set(CMD_IACK);
+
+    //     log::info!(":::: xfer finish {error:?}, read {read}");
+    //     if let Some(error) = error {
+    //         Err(error)
+    //     } else {
+    //         Ok(read)
+    //     }
+    // }
+
+    // fn i2c_write(&self, address: I2CAddress, buffer: &[u8]) -> Result<usize, Error> {
+    //     let address = address.as_8_bit().ok_or(Error::NotImplemented)?;
+    //     let regs = self.regs.lock();
+    //     log::info!(":::: start {:#x} write", address);
+    //     regs.poll_wait(SR::BUSY::SET);
+    //     regs.TXR_RXR.set((address as u32) << 1);
+    //     regs.CR_SR.set(CMD_START);
+
+    //     let mut sent = 0;
+    //     let mut error = None;
+    //     loop {
+    //         let sr = regs.poll_wait(SR::TIP::SET);
+    //         if sent == buffer.len() {
+    //             // Generate stop condition
+    //             regs.CR_SR.set(CMD_STOP);
+    //             break;
+    //         }
+    //         if sr.matches_all(SR::AL::SET) {
+    //             regs.CR_SR.set(CMD_STOP);
+    //             error = Some(Error::WouldBlock);
+    //             break;
+    //         }
+    //         if sr.matches_all(SR::RXACK::SET) {
+    //             // Generate stop condition
+    //             regs.CR_SR.set(CMD_STOP);
+    //             error = Some(Error::DoesNotExist);
+    //             break;
+    //         }
+
+    //         log::info!(":::: send {:#x}", buffer[sent]);
+    //         regs.TXR_RXR.set(buffer[sent] as u32);
+    //         regs.CR_SR.set(CMD_WRITE);
+    //         sent += 1;
+    //     }
+
+    //     log::info!(":::: stop {:#x}", address);
+    //     regs.poll_wait(SR::BUSY::SET);
+    //     regs.CR_SR.set(CMD_IACK);
+
+    //     log::info!(":::: xfer finish {error:?}, sent {sent}");
+    //     if let Some(error) = error {
+    //         Err(error)
+    //     } else {
+    //         Ok(sent)
+    //     }
+    // }
+
+    fn set_speed(&self, speed: Hertz) -> Result<Hertz, Error> {
+        let input_rate = self.clock.rate()?;
+        let regs = self.regs.lock();
+        regs.set_clock_rate(input_rate, speed)
+    }
+}
+
+device_tree_driver! {
+    compatible: ["sifive,i2c0"],
+    driver: {
+        fn probe(&self, node: &Arc<Node>, context: &mut ProbeContext) -> Option<Arc<dyn Device>> {
+            let name = node.name().unwrap_or("i2c");
+            let base = node.map_base(context, 0)?;
+            let clock = node.clock(0)?;
+            let irq = node.interrupt(0)?;
+
+            let regs = unsafe { DeviceMemoryIo::map(base, Default::default()) }.ok()?;
+
+            let i2c = Arc::new(I2C {
+                name,
+                regs: IrqSafeSpinlock::new(regs),
+                clock,
+                irq,
+                index: OneTimeInit::new(),
+                sr: BitmapEvent::new(AtomicWaker::new()),
+            });
+
+            node.make_i2c_controller(i2c.clone());
+
+            Some(i2c)
+        }
+    }
+}
@@ -0,0 +1,11 @@
+#![no_std]
+
+extern crate alloc;
+
+mod clock_fu540;
+mod clock_fu740;
+mod ethernet;
+mod i2c;
+mod pll;
+mod pwm;
+mod uart;
@@ -0,0 +1,35 @@
+use device_api::clock::Hertz;
+use tock_registers::register_bitfields;
+
+#[derive(Debug)]
+pub(crate) struct WrpllData {
+    pub(crate) divr: u32,
+    pub(crate) divf: u32,
+    pub(crate) divq: u32,
+    pub(crate) int_feedback: bool,
+}
+
+register_bitfields! {
+    u32,
+    pub PllCfg [
+        PLLR            OFFSET(0)   NUMBITS(6)  [],
+        PLLF            OFFSET(6)   NUMBITS(9)  [],
+        PLLQ            OFFSET(15)  NUMBITS(3)  [],
+        PLLBYPASS       OFFSET(24)  NUMBITS(1)  [],
+        PLLFSEBYPASS    OFFSET(25)  NUMBITS(1)  [],
+        PLLLOCK         OFFSET(31)  NUMBITS(1)  [],
+    ]
+}
+
+impl WrpllData {
+    fn fbdiv(&self) -> u32 {
+        if self.int_feedback { 2 } else { 1 }
+    }
+
+    pub(crate) fn output_rate(&self, input_rate: Hertz) -> Hertz {
+        let fbdiv = self.fbdiv();
+        let n = input_rate * fbdiv * (self.divf + 1);
+        let n = n / (self.divr + 1);
+        n >> self.divq
+    }
+}
@@ -0,0 +1,206 @@
+use alloc::sync::Arc;
+use device_api::{
+    clock::{ClockHandle, Hertz},
+    device::{Device, DeviceInitContext},
+    pwm::{PwmController, PwmControllerInfo},
+};
+use device_tree::driver::{Node, ProbeContext, device_tree_driver};
+use libk::{device::manager::DEVICE_REGISTRY, error::Error};
+use libk_mm::device::DeviceMemoryIo;
+use libk_util::sync::IrqSafeSpinlock;
+use tock_registers::{
+    interfaces::{ReadWriteable, Readable, Writeable},
+    register_bitfields, register_structs,
+    registers::ReadWrite,
+};
+use yggdrasil_abi::time::NANOSECONDS_IN_SECOND;
+
+const CHANNEL_COUNT: usize = 4;
+const CMPWIDTH: usize = 16;
+const SCALE_MAX: u32 = (1 << 4) - 1;
+const MAX_PERIOD_CYCLES: u64 = (1u64 << (CMPWIDTH + 16)) - 1;
+const MAX_COMPARE_VALUE: u32 = (1u32 << 16) - 1;
+
+register_bitfields! {
+    u32,
+    PwmCfg [
+        SCALE       OFFSET(0)   NUMBITS(4)  [],
+        STICKY      OFFSET(8)   NUMBITS(1)  [],
+        ZEROCMP     OFFSET(9)   NUMBITS(1)  [],
+        DEGLITCH    OFFSET(10)  NUMBITS(1)  [],
+        ENALWAYS    OFFSET(12)  NUMBITS(1)  [],
+        ENONESHOT   OFFSET(13)  NUMBITS(1)  [],
+        CMP_CENTER  OFFSET(16)  NUMBITS(4)  [],
+        CMP_GANG    OFFSET(24)  NUMBITS(4)  [],
+        CMP_IP      OFFSET(28)  NUMBITS(4)  [],
+    ]
+}
+
+register_structs! {
+    Regs {
+        (0x00 => pwmcfg: ReadWrite<u32, PwmCfg::Register>),
+        (0x04 => _0),
+        (0x08 => pwmcount: ReadWrite<u32>),
+        (0x0C => _1),
+        (0x10 => pwms: ReadWrite<u32>),
+        (0x14 => _2),
+        (0x20 => pwmcmp: [ReadWrite<u32>; CHANNEL_COUNT]),
+        (0x30 => @END),
+    }
+}
+
+struct Pwm {
+    name: &'static str,
+    clock: ClockHandle,
+    regs: IrqSafeSpinlock<DeviceMemoryIo<'static, Regs>>,
+}
+
+impl Regs {
+    fn ns_to_compare_value(&self, input_clk: Hertz, ns: u64) -> Option<u32> {
+        let scale = self.pwmcfg.read(PwmCfg::SCALE);
+        let tick_duration_ns = NANOSECONDS_IN_SECOND / (input_clk.0 >> scale);
+        let ticks = ns / tick_duration_ns;
+        if ticks < MAX_COMPARE_VALUE as u64 {
+            Some(ticks as u32)
+        } else {
+            None
+        }
+    }
+
+    fn compare_value_to_ns(&self, input_clk: Hertz, cval: u32) -> u64 {
+        let scale = self.pwmcfg.read(PwmCfg::SCALE);
+        let tick_duration_ns = NANOSECONDS_IN_SECOND / (input_clk.0 >> scale);
+        tick_duration_ns * cval as u64
+    }
+}
+
+impl Device for Pwm {
+    unsafe fn init(self: Arc<Self>, _cx: DeviceInitContext) -> Result<(), Error> {
+        // pwm counter registers are (cmpwidth + 15) bits wide
+        self.clock.enable()?;
+        // Set all channels to max value and channel 0 sets the period
+        {
+            let regs = self.regs.lock();
+
+            regs.pwmcfg
+                .write(PwmCfg::ZEROCMP::SET + PwmCfg::ENALWAYS::SET);
+            for channel in 0..CHANNEL_COUNT {
+                regs.pwmcmp[channel].set(MAX_COMPARE_VALUE);
+            }
+        }
+
+        DEVICE_REGISTRY.pwm.register_controller(self)?;
+
+        Ok(())
+    }
+
+    fn display_name(&self) -> &str {
+        self.name
+    }
+}
+
+impl PwmController for Pwm {
+    fn controller_info(&self) -> Result<PwmControllerInfo, Error> {
+        Ok(PwmControllerInfo {
+            channel_count: CHANNEL_COUNT,
+            per_channel_period: false,
+        })
+    }
+
+    fn channel_period(&self, _channel: u32) -> Result<u64, Error> {
+        let input_clk = self.clock.rate()?;
+        let regs = self.regs.lock();
+        let compare_value = regs.pwmcmp[0].get();
+        if compare_value == MAX_COMPARE_VALUE {
+            return Ok(0);
+        }
+        let period_ns = regs.compare_value_to_ns(input_clk, compare_value);
+        Ok(period_ns)
+    }
+
+    fn set_channel_period(&self, _channel: u32, period: u64) -> Result<u64, Error> {
+        // Channel 0 sets the period
+        let input_clk = self.clock.rate()?;
+        let period_cycles = period * u64::from(input_clk) / NANOSECONDS_IN_SECOND;
+        let mut prescaler = 0;
+        if period_cycles > MAX_PERIOD_CYCLES {
+            return Err(Error::InvalidArgument);
+        }
+
+        while (period_cycles >> prescaler) >= MAX_COMPARE_VALUE as u64 {
+            prescaler += 1;
+        }
+
+        if prescaler > SCALE_MAX {
+            log::warn!("Cannot fit {prescaler} into 4-bit prescaler");
+            return Err(Error::InvalidArgument);
+        }
+
+        let period_ticks = period_cycles >> prescaler;
+
+        let regs = self.regs.lock();
+
+        regs.pwmcfg
+            .modify(PwmCfg::SCALE.val(prescaler) + PwmCfg::ZEROCMP::SET);
+        regs.pwmcmp[0].set(period_ticks as u32);
+
+        let tick_duration_ns = NANOSECONDS_IN_SECOND / (input_clk.0 >> prescaler);
+        let real_period_ns = tick_duration_ns * period_ticks;
+
+        Ok(real_period_ns)
+    }
+
+    fn set_duty_cycle(&self, channel: u32, t: u64) -> Result<(), Error> {
+        // Channel 0 sets the period
+        if channel == 0 {
+            return Ok(());
+        }
+        let input_clk = self.clock.rate()?;
+        let regs = self.regs.lock();
+        let cval = regs
+            .ns_to_compare_value(input_clk, t)
+            .ok_or(Error::InvalidArgument)?;
+        // If the cval exceeds the "period" comparator, the PWM will never fire
+        let cval = cval.min(regs.pwmcmp[0].get().saturating_sub(1));
+        regs.pwmcmp[channel as usize].set(cval);
+        Ok(())
+    }
+
+    fn duty_cycle(&self, channel: u32) -> Result<u64, Error> {
+        if channel == 0 {
+            return Ok(0);
+        }
+        let input_clk = self.clock.rate()?;
+        let regs = self.regs.lock();
+        Ok(regs.compare_value_to_ns(input_clk, regs.pwmcmp[channel as usize].get()))
+    }
+
+    fn stop_channel(&self, channel: u32) -> Result<(), Error> {
+        if channel == 0 {
+            return Ok(());
+        }
+        self.regs.lock().pwmcmp[channel as usize].set(MAX_COMPARE_VALUE);
+        Ok(())
+    }
+}
+
+device_tree_driver! {
+    compatible: ["sifive,pwm0"],
+    driver: {
+        fn probe(&self, node: &Arc<Node>, context: &mut ProbeContext) -> Option<Arc<dyn Device>> {
+            let name = node.name().unwrap_or("pwm");
+            let base = node.map_base(context, 0)?;
+            let clock = node.clock(0)?;
+
+            let regs = unsafe { DeviceMemoryIo::map(base, Default::default()) }.ok()?;
+
+            let pwm = Arc::new(Pwm {
+                name,
+                regs: IrqSafeSpinlock::new(regs),
+                clock,
+            });
+
+            Some(pwm)
+        }
+    }
+}
@@ -0,0 +1,282 @@
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use alloc::sync::Arc;
+use device_api::{
+    clock::{ClockHandle, Hertz},
+    device::{Device, DeviceInitContext},
+    interrupt::{InterruptHandler, IrqHandle, IrqPriority, IrqVector},
+};
+use device_tree::driver::{Node, ProbeContext, device_tree_driver};
+use libk::{
+    debug::{self, DebugSink},
+    device::manager::DEVICE_REGISTRY,
+    error::Error,
+    vfs::{Terminal, TerminalInput, TerminalOutput},
+};
+use libk_mm::{address::PhysicalAddress, device::DeviceMemoryIo};
+use libk_util::{OneTimeInit, sync::IrqSafeSpinlock};
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields, register_structs,
+    registers::{ReadOnly, ReadWrite},
+};
+use yggdrasil_abi::{
+    io::{TerminalOptions, TerminalOutputOptions},
+    process::ProcessId,
+};
+
+register_bitfields! {
+    u32,
+    txctrl [
+        txen    OFFSET(0)   NUMBITS(1)  [],
+        nstop   OFFSET(1)   NUMBITS(1)  [
+            One = 0,
+            Two = 1
+        ],
+        txcnt   OFFSET(16)  NUMBITS(3)  [],
+    ],
+    rxctrl [
+        rxen    OFFSET(0)   NUMBITS(1)  [],
+        rxcnt   OFFSET(16)  NUMBITS(3)  [],
+    ],
+    interrupt [
+        txwm    OFFSET(0)   NUMBITS(1)  [],
+        rxwm    OFFSET(1)   NUMBITS(1)  [],
+    ],
+}
+
+register_structs! {
+    Regs {
+        (0x00 => txdata: ReadWrite<u32>),
+        (0x04 => rxdata: ReadOnly<u32>),
+        (0x08 => txctrl: ReadWrite<u32, txctrl::Register>),
+        (0x0C => rxctrl: ReadWrite<u32, rxctrl::Register>),
+        (0x10 => ie: ReadWrite<u32, interrupt::Register>),
+        (0x14 => ip: ReadOnly<u32, interrupt::Register>),
+        (0x18 => div: ReadWrite<u32>),
+        (0x1C => _0),
+        (0x20 => @END),
+    }
+}
+
+struct Inner {
+    clock: ClockHandle,
+    regs: IrqSafeSpinlock<DeviceMemoryIo<'static, Regs>>,
+    active: AtomicBool,
+}
+
+struct Uart {
+    name: &'static str,
+    irq: IrqHandle,
+    clock: ClockHandle,
+    base: PhysicalAddress,
+    inner: OneTimeInit<Arc<Terminal<Inner>>>,
+}
+
+impl Regs {
+    fn set_baud_rate(&self, input_clk: Hertz, baud: u32) -> Result<(), Error> {
+        // Check: given f_in=130MHz, baud=115200 should give div = 0x468
+        let div = Hertz::divider(input_clk, Hertz::from(baud)).ok_or(Error::InvalidArgument)?;
+        if div >= (1 << 20) || div == 0 {
+            return Err(Error::InvalidArgument);
+        }
+        let div = div - 1;
+        self.div.set(div);
+
+        Ok(())
+    }
+
+    fn baud_rate(&self, input_clk: Hertz) -> u32 {
+        let div = self.div.get() + 1;
+        (input_clk / div).0 as u32
+    }
+
+    #[inline]
+    fn is_txfifo_full(&self) -> bool {
+        self.txdata.get() & (1 << 31) != 0
+    }
+
+    fn read(&self) -> Option<u8> {
+        let val = self.rxdata.get();
+        if val & (1 << 31) == 0 {
+            Some(val as u8)
+        } else {
+            None
+        }
+    }
+
+    fn write(&self, byte: u8) {
+        while self.is_txfifo_full() {
+            for _ in 0..10000 {
+                core::hint::spin_loop();
+            }
+        }
+        self.txdata.set(byte as u32);
+    }
+}
+
+impl Device for Uart {
+    unsafe fn init(self: Arc<Self>, _cx: DeviceInitContext) -> Result<(), Error> {
+        let regs = unsafe { DeviceMemoryIo::<Regs>::map(self.base, Default::default()) }?;
+
+        self.clock.enable()?;
+        let input_clk = self.clock.rate()?;
+        log::info!("input_clk = {input_clk}");
+
+        {
+            let _guard = debug::MuteGuard::acquire();
+
+            regs.txctrl.write(txctrl::txen::CLEAR);
+            regs.rxctrl.write(rxctrl::rxen::CLEAR);
+            regs.set_baud_rate(input_clk, 115200)?;
+            regs.txctrl.write(txctrl::txen::SET + txctrl::txcnt.val(3));
+        }
+
+        // Drain Rx FIFO
+        while regs.read().is_some() {
+            core::hint::spin_loop();
+        }
+
+        let input = TerminalInput::with_capacity(64)?;
+        let output = Inner {
+            regs: IrqSafeSpinlock::new(regs),
+            clock: self.clock.clone(),
+            active: AtomicBool::new(false),
+        };
+
+        let terminal = self.inner.init(Arc::new(Terminal::from_parts(
+            TerminalOptions::const_default(),
+            input,
+            output,
+        )));
+
+        DEVICE_REGISTRY
+            .serial_terminal
+            .register(terminal.clone(), Some(self.clone()))
+            .ok();
+
+        Ok(())
+    }
+
+    unsafe fn init_irq(self: Arc<Self>) -> Result<(), Error> {
+        self.irq
+            .register_with_priority(IrqPriority::Low, self.clone())?;
+        self.irq.enable()?;
+        Ok(())
+    }
+
+    fn display_name(&self) -> &str {
+        self.name
+    }
+}
+
+impl InterruptHandler for Uart {
+    fn handle_irq(self: Arc<Self>, _vector: IrqVector) -> bool {
+        let terminal = self.inner.get();
+        let regs = terminal.output().regs.lock();
+        let ip = regs.ip.extract();
+        if ip.get() == 0 {
+            return false;
+        }
+
+        let mut count = 0;
+        let mut bytes = [0; 32];
+        // if ip.matches_all(interrupt::rxwm::SET) {
+        while let Some(byte) = regs.read() {
+            bytes[count] = byte;
+            count += 1;
+        }
+        // }
+        drop(regs);
+        for &byte in &bytes[..count] {
+            if byte != 0 {
+                terminal.write_to_input(byte);
+            }
+        }
+
+        true
+    }
+}
+
+impl DebugSink for Uart {
+    fn putc(&self, c: u8) -> Result<(), Error> {
+        self.inner.get().putc_to_output(c)
+    }
+    fn puts(&self, s: &str) -> Result<(), Error> {
+        self.inner.get().write_to_output(s.as_bytes())?;
+        Ok(())
+    }
+    fn supports_control_sequences(&self) -> bool {
+        true
+    }
+}
+
+impl TerminalOutput for Inner {
+    fn open(&self, _pid: ProcessId) -> Result<(), Error> {
+        if !self.active.swap(true, Ordering::Acquire) {
+            log::info!("sifive-uart: start");
+            let regs = self.regs.lock();
+            regs.rxctrl.write(rxctrl::rxen::SET + rxctrl::rxcnt.val(0));
+            // Drain Rx FIFO
+            while regs.read().is_some() {
+                core::hint::spin_loop();
+            }
+            regs.ie.write(interrupt::rxwm::SET);
+        }
+        Ok(())
+    }
+
+    fn write(&self, byte: u8, options: &TerminalOutputOptions) -> Result<(), Error> {
+        let regs = self.regs.lock();
+        if byte == b'\n' && options.contains(TerminalOutputOptions::NL_TO_CRNL) {
+            regs.write(b'\r');
+        }
+        regs.write(byte);
+        Ok(())
+    }
+    fn write_multiple(
+        &self,
+        bytes: &[u8],
+        options: &TerminalOutputOptions,
+    ) -> Result<usize, Error> {
+        let regs = self.regs.lock();
+        for &byte in bytes {
+            if byte == b'\n' && options.contains(TerminalOutputOptions::NL_TO_CRNL) {
+                regs.write(b'\r');
+            }
+            regs.write(byte);
+        }
+        Ok(bytes.len())
+    }
+
+    fn baud_rate(&self) -> u32 {
+        let input_clk = self.clock.rate().unwrap();
+        self.regs.lock().baud_rate(input_clk)
+    }
+    fn set_baud_rate(&self, baud: u32) -> Result<(), Error> {
+        let input_clk = self.clock.rate().unwrap();
+        self.regs.lock().set_baud_rate(input_clk, baud)
+    }
+}
+
+device_tree_driver! {
+    compatible: ["sifive,uart0"],
+    driver: {
+        fn probe(&self, node: &Arc<Node>, context: &mut ProbeContext) -> Option<Arc<dyn Device>> {
+            let name = node.name().unwrap_or("uart");
+            let base = node.map_base(context, 0)?;
+            let clock = node.clock(0)?;
+            let irq = node.interrupt(0)?;
+
+            let uart = Arc::new(Uart {
+                name,
+                irq,
+                clock,
+                base,
+                inner: OneTimeInit::new()
+            });
+
+            Some(uart)
+        }
+    }
+}
@@ -5,7 +5,7 @@ use device_api::{
    device::Device,
    interrupt::{
        ExternalInterruptController, InterruptAffinity, InterruptHandler, Irq, IrqOptions,
-        MessageInterruptController, MsiInfo,
+        IrqPriority, MessageInterruptController, MsiInfo,
    },
 };
 use libk::device::external_interrupt_controller;
@@ -215,9 +215,10 @@ impl PciDeviceInfo {
        }
    }

-    pub fn map_interrupt(
+    pub fn map_interrupt_with_priority(
        &self,
        affinity: InterruptAffinity,
+        priority: IrqPriority,
        handler: Arc<dyn InterruptHandler>,
    ) -> Result<Option<MsiInfo>, Error> {
        let mut irq = self.interrupt_config.get().write();
@@ -238,17 +239,25 @@ impl PciDeviceInfo {
                Ok(Some(info[0]))
            }
            ConfiguredInterruptMode::LegacyPin(intc, pin) => {
-                self.try_map_legacy(intc.as_ref(), *pin, handler)?;
+                self.try_map_legacy(intc.as_ref(), *pin, priority, handler)?;
                Ok(None)
            }
            ConfiguredInterruptMode::LegacyLine(intc, irq) => {
-                self.try_map_legacy_line(intc.as_ref(), *irq, handler)?;
+                self.try_map_legacy_line(intc.as_ref(), *irq, priority, handler)?;
                Ok(None)
            }
            ConfiguredInterruptMode::None => Err(Error::InvalidOperation),
        }
    }

+    pub fn map_interrupt(
+        &self,
+        affinity: InterruptAffinity,
+        handler: Arc<dyn InterruptHandler>,
+    ) -> Result<Option<MsiInfo>, Error> {
+        self.map_interrupt_with_priority(affinity, IrqPriority::Normal, handler)
+    }
+
    pub fn map_interrupt_multiple(
        &self,
        vector_range: Range<usize>,
@@ -271,6 +280,7 @@ impl PciDeviceInfo {
        &self,
        intc: &dyn ExternalInterruptController,
        pin: PciInterruptPin,
+        priority: IrqPriority,
        handler: Arc<dyn InterruptHandler>,
    ) -> Result<(), Error> {
        let src = PciInterrupt {
@@ -280,7 +290,7 @@ impl PciDeviceInfo {
        let route = self
            .segment
            .irq_translation_map
-            .map_interrupt(&src)
+            .map_interrupt(&src, priority)
            .inspect_err(|e| log::warn!("Could not map PCI IRQ {pin:?}: {e:?}"))?;

        log::debug!(
@@ -299,12 +309,20 @@ impl PciDeviceInfo {
        &self,
        intc: &dyn ExternalInterruptController,
        line: u8,
+        priority: IrqPriority,
        handler: Arc<dyn InterruptHandler>,
    ) -> Result<(), Error> {
        log::debug!("PCI {} -> IRQ#{}", self.address, line);

        let irq = Irq::External(line as u32);
-        intc.register_irq(irq, Default::default(), handler)?;
+        intc.register_irq(
+            irq,
+            IrqOptions {
+                priority,
+                ..Default::default()
+            },
+            handler,
+        )?;
        intc.enable_irq(irq)
    }
 }
@@ -1,7 +1,7 @@
 use core::fmt;

 use alloc::{collections::btree_map::BTreeMap, sync::Arc, vec::Vec};
-use device_api::interrupt::MessageInterruptController;
+use device_api::interrupt::{IrqPriority, MessageInterruptController};
 use libk::error::Error;

 use crate::{
@@ -36,7 +36,11 @@ pub enum PciMsiMap {
 }

 impl PciInterruptMap {
-    pub fn map_interrupt(&self, interrupt: &PciInterrupt) -> Result<PciInterruptRoute, Error> {
+    pub fn map_interrupt(
+        &self,
+        interrupt: &PciInterrupt,
+        #[allow(unused)] priority: IrqPriority,
+    ) -> Result<PciInterruptRoute, Error> {
        match self {
            Self::Fixed(map) => map.get(interrupt).cloned().ok_or(Error::DoesNotExist),
            #[cfg(any(target_arch = "x86_64", rust_analyzer))]
@@ -77,7 +81,11 @@ impl PciInterruptMap {
                };

                Ok(PciInterruptRoute {
-                    options: IrqOptions { trigger, level },
+                    options: IrqOptions {
+                        trigger,
+                        level,
+                        priority,
+                    },
                    number: aml_route.irq,
                })
            }
@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_usb"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 [dependencies]
@@ -4,7 +4,6 @@
    generic_const_exprs,
    iter_array_chunks,
    maybe_uninit_as_bytes,
-    maybe_uninit_fill,
    maybe_uninit_array_assume_init
 )]

@@ -1,7 +1,7 @@
 [package]
 name = "ext2"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 [dependencies]
@@ -1,4 +1,3 @@
-#![feature(if_let_guard, impl_trait_in_assoc_type)]
 #![cfg_attr(not(test), no_std)]
 #![allow(clippy::new_ret_no_self)]

@@ -1,7 +1,7 @@
 [package]
 name = "kernel-fs"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 [dependencies]
@@ -1,7 +1,7 @@
 [package]
 name = "memfs"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 [dependencies]
@@ -159,7 +159,7 @@ impl<'a, A: BlockAllocator> BlockRaw<'a, A> {
            panic!("Null block dereference");
        }

-        &mut *(self.inner.ptr as *mut _)
+        unsafe { &mut *(self.inner.ptr as *mut _) }
    }

    #[inline]
@@ -197,7 +197,7 @@ impl<A: BlockAllocator> BlockData<'_, A> {
    pub unsafe fn copy_on_write(address: usize) -> Self {
        Self {
            inner: BlockRaw {
-                inner: BlockRef::copy_on_write(address),
+                inner: unsafe { BlockRef::copy_on_write(address) },
            },
        }
    }
@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_input"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -8,6 +8,7 @@ yggdrasil-abi = { workspace = true, features = ["serde_kernel", "bytemuck"] }
 libk-mm.workspace = true
 libk-util.workspace = true
 libk.workspace = true
+device-api.workspace = true

 kernel-fs = { path = "../../fs/kernel-fs" }

@@ -1,4 +1,3 @@
-#![feature(map_try_insert)]
 #![allow(clippy::type_complexity, clippy::new_without_default)]
 #![no_std]

@@ -0,0 +1,5 @@
+pub use queue::*;
+pub use reassembler::*;
+
+mod queue;
+mod reassembler;
@@ -0,0 +1,290 @@
+use core::mem::{self, MaybeUninit};
+
+use alloc::vec::Vec;
+use device_api::dma::DmaAllocator;
+use libk::{
+    dma::{BusAddress, DmaBuffer},
+    error::Error,
+};
+use libk_util::{sync::IrqSafeSpinlock, waker::QueueWaker};
+
+pub trait GenericTxDescriptor: Sized {
+    const EMPTY: Self;
+    const EMPTY_LAST: Self = Self::EMPTY;
+
+    fn consume(&mut self) -> Option<Result<(), Error>>;
+    fn setup_tx(
+        &mut self,
+        buffer_address: BusAddress,
+        size: usize,
+        index: usize,
+        capacity: usize,
+    ) -> Result<(), Error>;
+}
+
+pub trait GenericRxDescriptor: Sized {
+    // TODO Rx flags (short, runt, etc)
+    fn consume(&mut self) -> Option<Result<usize, Error>>;
+    fn setup_rx(buffer_address: BusAddress, buffer_size: usize, last: bool) -> Result<Self, Error>;
+}
+
+struct TxInFlight {
+    #[allow(unused)]
+    buffer: DmaBuffer<[u8]>,
+}
+
+struct TxRingInner<T: GenericTxDescriptor> {
+    entries: DmaBuffer<[T]>,
+    in_flight: Vec<Option<TxInFlight>>,
+
+    wr: usize,
+    rd: usize,
+}
+
+struct RxRingInner<T: GenericRxDescriptor> {
+    entries: DmaBuffer<[T]>,
+    buffers: Vec<DmaBuffer<[MaybeUninit<u8>]>>,
+
+    rd: usize,
+}
+
+pub struct GenericTxRing<T: GenericTxDescriptor> {
+    inner: IrqSafeSpinlock<TxRingInner<T>>,
+
+    buffer_base: BusAddress,
+    capacity: usize,
+    free_notify: QueueWaker,
+}
+
+pub struct GenericRxRing<T: GenericRxDescriptor> {
+    inner: IrqSafeSpinlock<RxRingInner<T>>,
+
+    rx_buffer_size: usize,
+    buffer_base: BusAddress,
+    capacity: usize,
+}
+
+pub struct GenericQueue<Tx: GenericTxDescriptor, Rx: GenericRxDescriptor> {
+    pub tx_ring: GenericTxRing<Tx>,
+    pub rx_ring: GenericRxRing<Rx>,
+}
+
+impl<Tx: GenericTxDescriptor, Rx: GenericRxDescriptor> GenericQueue<Tx, Rx> {
+    pub fn with_capacity(
+        dma: &dyn DmaAllocator,
+        tx_capacity: usize,
+        rx_capacity: usize,
+        rx_buffer_size: usize,
+    ) -> Result<Self, Error> {
+        let tx_ring = GenericTxRing::with_capacity(dma, tx_capacity)?;
+        let rx_ring = GenericRxRing::with_capacity(dma, rx_capacity, rx_buffer_size)?;
+        Ok(Self { tx_ring, rx_ring })
+    }
+
+    pub fn tx_buffer_base(&self) -> BusAddress {
+        self.tx_ring.buffer_base
+    }
+    pub fn rx_buffer_base(&self) -> BusAddress {
+        self.rx_ring.buffer_base
+    }
+
+    pub fn try_push_xmit(&self, frame: DmaBuffer<[u8]>) -> Result<usize, Error> {
+        self.tx_ring.try_push_xmit(frame)
+    }
+
+    pub fn drop_tx_until(&self, head: usize) {
+        self.tx_ring.drop_until(head);
+    }
+    pub fn consume_tx(&self) -> Result<usize, Error> {
+        self.tx_ring.consume()
+    }
+    pub fn consume_rx<F: Fn(DmaBuffer<[u8]>, usize)>(
+        &self,
+        dma: &dyn DmaAllocator,
+        head: Option<usize>,
+        handler: F,
+    ) -> Result<usize, Error> {
+        self.rx_ring.consume(dma, head, handler)
+    }
+}
+
+impl<T: GenericTxDescriptor> GenericTxRing<T> {
+    pub fn with_capacity(dma: &dyn DmaAllocator, capacity: usize) -> Result<Self, Error> {
+        let entries = DmaBuffer::new_slice_with(
+            dma,
+            |i| {
+                if i == capacity - 1 {
+                    T::EMPTY_LAST
+                } else {
+                    T::EMPTY
+                }
+            },
+            capacity,
+        )?;
+        let in_flight = (0..capacity).map(|_| None).collect();
+        let buffer_base = entries.bus_address();
+        let inner = TxRingInner {
+            entries,
+            in_flight,
+            wr: 0,
+            rd: 0,
+        };
+        Ok(Self {
+            inner: IrqSafeSpinlock::new(inner),
+            buffer_base,
+            capacity,
+            free_notify: QueueWaker::new(),
+        })
+    }
+
+    pub fn base(&self) -> BusAddress {
+        self.buffer_base
+    }
+    pub fn capacity(&self) -> usize {
+        self.capacity
+    }
+
+    pub async fn push_xmit(&self, _frame: DmaBuffer<[u8]>) -> Result<usize, Error> {
+        todo!()
+    }
+
+    pub fn try_push_xmit(&self, frame: DmaBuffer<[u8]>) -> Result<usize, Error> {
+        let mut inner = self.inner.lock();
+        if inner.wr.wrapping_add(1) % self.capacity == inner.rd % self.capacity {
+            return Err(Error::WouldBlock);
+        }
+
+        let buffer_address = frame.bus_address();
+        let buffer_len = frame.len();
+
+        let index = inner.wr % self.capacity;
+
+        frame.cache_flush_all(true);
+        inner.entries[index].setup_tx(buffer_address, buffer_len, index, self.capacity)?;
+        inner.entries.cache_flush_element(index, true);
+
+        inner.in_flight[index] = Some(TxInFlight { buffer: frame });
+        inner.wr = inner.wr.wrapping_add(1);
+
+        Ok(inner.wr % self.capacity)
+    }
+
+    pub fn drop_until(&self, head: usize) {
+        self.inner.lock().rd = head % self.capacity;
+    }
+
+    pub fn consume(&self) -> Result<usize, Error> {
+        let mut count = 0;
+
+        {
+            let mut inner = self.inner.lock();
+
+            while inner.rd != inner.wr {
+                let index = inner.rd % self.capacity;
+                inner.entries.cache_flush_element(index, false);
+                let entry = &mut inner.entries[index];
+
+                if let Some(_status) = entry.consume() {
+                    let _ = inner.in_flight[index].take().unwrap();
+                    inner.rd = inner.rd.wrapping_add(1);
+                    count += 1;
+                } else {
+                    break;
+                }
+            }
+        }
+
+        if count != 0 {
+            self.free_notify.wake_all();
+        }
+
+        Ok(count)
+    }
+}
+
+impl<T: GenericRxDescriptor> GenericRxRing<T> {
+    pub fn with_capacity(
+        dma: &dyn DmaAllocator,
+        capacity: usize,
+        rx_buffer_size: usize,
+    ) -> Result<Self, Error> {
+        let buffers = (0..capacity)
+            .map(|_| DmaBuffer::new_uninit_slice(dma, rx_buffer_size))
+            .collect::<Result<Vec<_>, _>>()?;
+        let entries = DmaBuffer::new_slice_with(
+            dma,
+            |i| {
+                let buffer = buffers[i].bus_address();
+                let last = i == capacity - 1;
+                T::setup_rx(buffer, rx_buffer_size, last).expect("Rx buffer descriptor setup error")
+            },
+            capacity,
+        )?;
+        let buffer_base = entries.bus_address();
+        let inner = RxRingInner {
+            entries,
+            buffers,
+
+            rd: 0,
+        };
+        Ok(Self {
+            inner: IrqSafeSpinlock::new(inner),
+            rx_buffer_size,
+            buffer_base,
+            capacity,
+        })
+    }
+
+    pub fn base(&self) -> BusAddress {
+        self.buffer_base
+    }
+    pub fn capacity(&self) -> usize {
+        self.capacity
+    }
+
+    pub fn consume<F: Fn(DmaBuffer<[u8]>, usize)>(
+        &self,
+        dma: &dyn DmaAllocator,
+        head: Option<usize>,
+        handler: F,
+    ) -> Result<usize, Error> {
+        let mut inner = self.inner.lock();
+
+        while head.is_none_or(|tail| tail != inner.rd) {
+            let index = inner.rd % self.capacity;
+
+            inner.entries.cache_flush_element(index, false);
+
+            if let Some(status) = inner.entries[index].consume() {
+                // Grab the current buffer (the one just written to by the DMA), replace it
+                // with the newly allocated one, and mark the descriptor as DMA-owned again
+                let new_buffer = DmaBuffer::new_uninit_slice(dma, self.rx_buffer_size)?;
+                let new_buffer_address = new_buffer.bus_address();
+                let buffer = mem::replace(&mut inner.buffers[index], new_buffer);
+                let old_buffer_address = buffer.bus_address();
+                let buffer = unsafe { DmaBuffer::assume_init_slice(buffer) };
+
+                match status {
+                    Ok(len) => {
+                        handler(buffer, len);
+                    }
+                    Err(_error) => {
+                        log::warn!("Drop error packet {old_buffer_address:#x}");
+                    }
+                }
+
+                inner.entries[index] = T::setup_rx(
+                    new_buffer_address,
+                    self.rx_buffer_size,
+                    index == self.capacity - 1,
+                )?;
+
+                inner.rd = inner.rd.wrapping_add(1);
+            } else {
+                break;
+            }
+        }
+
+        Ok(inner.rd)
+    }
+}
@@ -14,4 +14,5 @@ ygg_driver_pci.path = "../../bus/pci"
 ygg_driver_net_core.path = "../core"

 log.workspace = true
+futures-util.workspace = true
 tock-registers.workspace = true
@@ -8,17 +8,16 @@ use device_api::{
    dma::DmaAllocator,
    interrupt::{InterruptAffinity, InterruptHandler, IrqVector},
 };
-use libk::{dma::DmaBuffer, error::Error};
-use libk_util::{
-    OneTimeInit,
-    sync::{IrqSafeSpinlock, Spinlock},
-};
-use regs::{ICR, Regs};
-use ring::{RxRing, TxRing};
+use futures_util::task::AtomicWaker;
+use libk::{dma::DmaBuffer, error::Error, task::runtime};
+use libk_util::{OneTimeInit, event::BitmapEvent, sync::IrqSafeSpinlock};
+use regs::Regs;
+use tock_registers::{LocalRegisterCopy, fields::FieldValue};
 use ygg_driver_net_core::{
    RxPacket,
    interface::{NetworkDevice, NetworkInterfaceType},
    register_interface,
+    util::GenericQueue,
 };
 use ygg_driver_pci::{
    PciBaseAddress, PciConfigurationSpace,
@@ -27,7 +26,10 @@ use ygg_driver_pci::{
 };
 use yggdrasil_abi::net::{MacAddress, link::LinkState};

-use crate::regs::Revision;
+use crate::{
+    regs::Revision,
+    ring::{RxDescriptor, TxDescriptor},
+};

 extern crate alloc;

@@ -41,8 +43,8 @@ struct Igbe {
    pci: PciDeviceInfo,

    mac: OneTimeInit<MacAddress>,
-    rx_ring: OneTimeInit<Spinlock<RxRing>>,
-    tx_ring: OneTimeInit<IrqSafeSpinlock<TxRing>>,
+    queue: OneTimeInit<GenericQueue<TxDescriptor, RxDescriptor>>,
+    softirq: BitmapEvent<AtomicWaker>,
    nic: OneTimeInit<u32>,
 }

@@ -55,11 +57,55 @@ impl Igbe {
            mac: OneTimeInit::new(),
            regs: IrqSafeSpinlock::new(regs),

-            rx_ring: OneTimeInit::new(),
-            tx_ring: OneTimeInit::new(),
+            queue: OneTimeInit::new(),
+            softirq: BitmapEvent::new(AtomicWaker::new()),
            nic: OneTimeInit::new(),
        }
    }
+
+    async fn softirq(self: Arc<Self>) {
+        let queue = self.queue.get();
+        let rx_capacity = queue.rx_ring.capacity();
+        let nic = *self.nic.get();
+
+        loop {
+            let event = self.softirq.wait().await as u32;
+            let event = LocalRegisterCopy::<_, regs::ICR::Register>::new(event);
+
+            if event.matches_all(regs::ICR::LSC::SET) {
+                let status = self.regs.lock().read_link();
+                log::info!("igbe: link is {status}");
+                self.interrupt_handled(regs::ICR::LSC::SET);
+            }
+            if event.matches_any(&[regs::ICR::TXQE::SET, regs::ICR::TXDW::SET]) {
+                let head = self.regs.lock().tx_queue_head();
+                queue.drop_tx_until(head as usize);
+                // queue.consume_tx(Some(head as usize)).ok();
+                self.interrupt_handled(regs::ICR::TXQE::SET + regs::ICR::TXDW::SET);
+            }
+            if event.matches_any(&[regs::ICR::RXDMT0::SET, regs::ICR::RXT0::SET]) {
+                {
+                    let mut regs = self.regs.lock();
+                    let head = regs.rx_queue_head() as usize;
+                    let tail = queue
+                        .consume_rx(&*self.dma, Some(head), |packet, _| {
+                            let packet = RxPacket::new(packet, 0, nic);
+                            ygg_driver_net_core::receive_packet(packet).ok();
+                        })
+                        .expect("Rx ring handle error");
+                    let tail = (tail + rx_capacity - 1) & (rx_capacity - 1);
+                    regs.set_rx_queue_tail(tail as u16);
+                }
+                self.interrupt_handled(regs::ICR::RXDMT0::SET + regs::ICR::RXT0::SET);
+            }
+        }
+    }
+
+    fn interrupt_handled(&self, icr: FieldValue<u32, regs::ICR::Register>) {
+        let mut regs = self.regs.lock();
+        regs.clear_interrupts(icr.value);
+        regs.enable_interrupts(icr.value);
+    }
 }

 impl Device for Igbe {
@@ -68,33 +114,44 @@ impl Device for Igbe {
            .pci
            .map_interrupt(InterruptAffinity::Any, self.clone())?;

-        let rx_ring = RxRing::with_capacity(&*self.dma, 128, 2048 + 16)?;
-        let tx_ring = TxRing::with_capacity(&*self.dma, 128)?;
+        let queue = self.queue.init(GenericQueue::with_capacity(
+            &*self.dma,
+            128,
+            128,
+            2048 + 16,
+        )?);

        let mut regs = self.regs.lock();

-        regs.disable_interrupts();
+        regs.disable_interrupts(0xFFFFFFFF);
        let mac = regs.read_mac()?;
        self.mac.init(mac);
        regs.reset(Duration::from_millis(200))?;
        // Intel 8257x manuals say an additional interrupt disable is needed after a global reset
-        regs.disable_interrupts();
+        regs.disable_interrupts(0xFFFFFFFF);
        regs.set_link_up(self.chip)?;

        // Initialize Rx
-        regs.initialize_receiver(&rx_ring);
-        regs.initialize_transmitter(&tx_ring);
+        regs.initialize_receiver(&queue.rx_ring);
+        regs.initialize_transmitter(&queue.tx_ring);
        // If MSI(-x) was initialized, notify the NIC about it
        if let Some(msi_info) = msi_info {
            regs.initialize_ivar(msi_info.vector);
        }

-        self.rx_ring.init(Spinlock::new(rx_ring));
-        self.tx_ring.init(IrqSafeSpinlock::new(tx_ring));
        let nic = register_interface(NetworkInterfaceType::Ethernet, self.clone());
        self.nic.init(nic.id());

-        regs.enable_interrupts();
+        regs.enable_interrupts(
+            (regs::IMS::TXDW::SET
+                + regs::IMS::TXQE::SET
+                + regs::IMS::LSC::SET
+                + regs::IMS::RXT0::SET
+                + regs::IMS::RXDMT0::SET)
+                .value,
+        );
+
+        runtime::spawn(self.clone().softirq())?;

        Ok(())
    }
@@ -107,43 +164,13 @@ impl Device for Igbe {
 impl InterruptHandler for Igbe {
    fn handle_irq(self: Arc<Self>, _vector: IrqVector) -> bool {
        let mut regs = self.regs.lock();
-        let cause = regs.interrupt_cause();
-        if cause.get() == 0 {
+        let cause = regs.interrupt_cause().get();
+        if cause == 0 {
            return false;
        }
-        regs.clear_interrupts(cause.get());
-        let mut any = false;
-
-        if cause.matches_all(ICR::LSC::SET) {
-            let status = regs.read_link();
-            log::info!("igbe: link is {status}");
-            any = true;
-        }
-
-        if cause.matches_all(ICR::RXT0::SET) {
-            let mut rx = self.rx_ring.get().lock();
-            let nic = *self.nic.get();
-            let head = regs.rx_queue_head();
-            let tail = rx.handle_rx(&*self.dma, head, |packet, _| {
-                let packet = RxPacket::new(packet, 0, nic);
-                ygg_driver_net_core::receive_packet(packet).ok();
-            });
-            regs.set_rx_queue_tail(tail);
-            any = true;
-        }
-
-        if cause.matches_any(&[ICR::TXQE::SET, ICR::TXDW::SET]) {
-            let mut tx = self.tx_ring.get().lock();
-            let head = regs.tx_queue_head();
-            tx.handle_tx(head);
-            any = true;
-        }
-
-        if !any {
-            log::info!("igbe: unhandled irq {:#x}", cause.get());
-        }
-
-        any
+        regs.disable_interrupts(cause);
+        self.softirq.signal(cause as u64);
+        true
    }
 }

@@ -161,15 +188,10 @@ impl NetworkDevice for Igbe {
    }

    fn transmit_buffer(&self, buffer: DmaBuffer<[u8]>) -> Result<(), Error> {
-        let mut tx = self.tx_ring.get().lock();
-
-        let Ok(head) = tx.tx_now(buffer) else {
-            return Err(Error::WouldBlock);
-        };
-
+        let queue = self.queue.get();
+        let tail = queue.try_push_xmit(buffer)?;
        let mut regs = self.regs.lock();
-        regs.set_tx_queue_tail(head);
-
+        regs.set_tx_queue_tail(tail as _);
        Ok(())
    }

@@ -7,14 +7,17 @@ use libk::{
 };
 use libk_mm::{address::PhysicalAddress, device::RawDeviceMemoryMapping};
 use tock_registers::{LocalRegisterCopy, RegisterLongName, fields::FieldValue, register_bitfields};
-use ygg_driver_net_core::ephy::{GBESR, MdioBus, PhyAccess};
+use ygg_driver_net_core::{
+    ephy::{GBESR, MdioBus, PhyAccess},
+    util::{GenericRxRing, GenericTxRing},
+};
 use ygg_driver_pci::PciBaseAddress;
 use yggdrasil_abi::net::{
    MacAddress,
    link::{Duplex, EthernetLinkState, EthernetSpeed},
 };

-use crate::{RxRing, TxRing};
+use crate::ring::{RxDescriptor, TxDescriptor};

 enum Inner {
    Memory(RawDeviceMemoryMapping),
@@ -79,12 +82,14 @@ register_bitfields! {
        TXDW    OFFSET(0)   NUMBITS(1)  [],
        TXQE    OFFSET(1)   NUMBITS(1)  [],
        LSC     OFFSET(2)   NUMBITS(1)  [],
+        RXDMT0  OFFSET(4)   NUMBITS(1)  [],
        RXT0    OFFSET(7)   NUMBITS(1)  [],
    ],
    pub IMS [
        TXDW    OFFSET(0)   NUMBITS(1)  [],
        TXQE    OFFSET(1)   NUMBITS(1)  [],
        LSC     OFFSET(2)   NUMBITS(1)  [],
+        RXDMT0  OFFSET(4)   NUMBITS(1)  [],
        RXT0    OFFSET(7)   NUMBITS(1)  [],
    ],
    pub RCTL [
@@ -459,36 +464,47 @@ impl Regs {
        }
    }

-    pub fn disable_interrupts(&mut self) {
-        self.inner.set::<IMC::Register>(0xFFFFFFFF);
-    }
-
-    pub fn clear_interrupts(&mut self, cause: u32) {
-        let _ = self.inner.get::<CPUVEC::Register>();
-        self.inner.set::<ICR::Register>(cause);
-    }
-
-    pub fn enable_interrupts(&mut self) {
-        self.inner.set::<IMS::Register>(0xFFFFFFFF);
-        // self.inner
-        //     .modify(IMS::LSC::SET + IMS::RXT0::SET + IMS::TXDW::SET + IMS::TXQE::SET);
-    }
+    // pub fn disable_interrupts(&mut self) {
+    //     self.inner.set::<IMC::Register>(0xFFFFFFFF);
+    // }

    pub fn interrupt_cause(&mut self) -> LocalRegisterCopy<u32, ICR::Register> {
        self.inner.extract()
    }

-    pub fn initialize_receiver(&mut self, rx_ring: &RxRing) {
-        let rx_queue_base = rx_ring.descriptors.bus_address().into_u64();
+    pub fn clear_interrupts(&mut self, icr: u32) {
+        let _ = self.inner.get::<CPUVEC::Register>();
+        self.inner.set::<ICR::Register>(icr);
+    }
+
+    pub fn enable_interrupts(&mut self, mask: u32) {
+        self.inner.set::<IMS::Register>(mask);
+    }
+
+    pub fn disable_interrupts(&mut self, mask: u32) {
+        self.inner.set::<IMC::Register>(mask);
+    }
+
+    // pub fn enable_interrupts(&mut self) {
+    //     self.inner.set::<IMS::Register>(0xFFFFFFFF);
+    //     // self.inner
+    //     //     .modify(IMS::LSC::SET + IMS::RXT0::SET + IMS::TXDW::SET + IMS::TXQE::SET);
+    // }
+
+    pub fn initialize_receiver(&mut self, rx_ring: &GenericRxRing<RxDescriptor>) {
+        let rx_queue_base = rx_ring.base().into_u64();
+        let rx_queue_capacity = rx_ring.capacity();
+
+        // let rx_queue_base = rx_ring.descriptors.bus_address().into_u64();
        self.inner.set::<RDBAL0::Register>(rx_queue_base as u32);
        self.inner
            .set::<RDBAH0::Register>((rx_queue_base >> 32) as u32);

        self.inner
-            .write(RDLEN0::LEN0.val((rx_ring.descriptors.len() / 8) as u32));
+            .write(RDLEN0::LEN0.val((rx_queue_capacity / 8) as u32));
        self.inner.set::<RDH0::Register>(0);
        self.inner
-            .set::<RDT0::Register>((rx_ring.descriptors.len() - 1) as u32);
+            .set::<RDT0::Register>((rx_queue_capacity - 1) as u32);

        self.inner.write(
            RCTL::EN::SET
@@ -499,14 +515,16 @@ impl Regs {
        );
    }

-    pub fn initialize_transmitter(&mut self, tx_ring: &TxRing) {
-        let tx_queue_base = tx_ring.descriptors.bus_address().into_u64();
+    pub fn initialize_transmitter(&mut self, tx_ring: &GenericTxRing<TxDescriptor>) {
+        let tx_queue_base = tx_ring.base().into_u64();
+        let tx_queue_capacity = tx_ring.capacity();
+
        self.inner.set::<TDBAL::Register>(tx_queue_base as u32);
        self.inner
            .set::<TDBAH::Register>((tx_queue_base >> 32) as u32);

        self.inner
-            .write(TDLEN::LEN.val((tx_ring.descriptors.len() / 8) as u32));
+            .write(TDLEN::LEN.val((tx_queue_capacity / 8) as u32));
        self.inner.set::<TDT::Register>(0);
        self.inner.set::<TDH::Register>(0);

@@ -1,31 +1,10 @@
-use core::mem::{self, MaybeUninit};
-
-use alloc::vec::Vec;
-use device_api::dma::DmaAllocator;
-use libk::{
-    dma::{BusAddress, DmaBuffer},
-    error::Error,
-};
-
-pub(crate) struct RxRing {
-    pub(crate) descriptors: DmaBuffer<[RxDescriptor]>,
-    buffers: Vec<DmaBuffer<[MaybeUninit<u8>]>>,
-    buffer_size: usize,
-    tail: u16,
-}
-
-pub(crate) struct TxRing {
-    pub(crate) descriptors: DmaBuffer<[TxDescriptor]>,
-    buffers: Vec<Option<DmaBuffer<[u8]>>>,
-    // Consumer end
-    tail: u16,
-    // Producer end
-    head: u16,
-}
+use libk::{dma::BusAddress, error::Error};
+use ygg_driver_net_core::util::{GenericRxDescriptor, GenericTxDescriptor};

+#[derive(Debug)]
 #[repr(C)]
 pub(crate) struct RxDescriptor {
-    address: BusAddress,
+    address: u64,
    length: u16,
    checksum: u16,
    status: u8,
@@ -33,9 +12,10 @@ pub(crate) struct RxDescriptor {
    special: u16,
 }

+#[derive(Debug)]
 #[repr(C)]
 pub(crate) struct TxDescriptor {
-    address: BusAddress,
+    address: u64,
    length: u16,
    cso: u8,
    cmd: u8,
@@ -45,117 +25,73 @@ pub(crate) struct TxDescriptor {
    special: u8,
 }

-impl RxRing {
-    pub fn with_capacity(
-        dma: &dyn DmaAllocator,
-        capacity: usize,
-        buffer_size: usize,
-    ) -> Result<Self, Error> {
-        let buffers = (0..capacity)
-            .map(|_| DmaBuffer::new_uninit_slice(dma, buffer_size))
-            .collect::<Result<Vec<_>, _>>()?;
-        let descriptors = DmaBuffer::new_slice_with(
-            dma,
-            |i| RxDescriptor::new(buffers[i].bus_address(), buffer_size as u16),
-            capacity,
-        )?;
+impl GenericTxDescriptor for TxDescriptor {
+    const EMPTY: Self = Self {
+        address: 0,
+        length: 0,
+        cso: 0,
+        cmd: 0,
+        sta: Self::STA_DD,
+        _0: 0,
+        css: 0,
+        special: 0,
+    };

-        Ok(Self {
-            descriptors,
-            buffers,
-            tail: 0,
-            buffer_size,
-        })
+    fn consume(&mut self) -> Option<Result<(), Error>> {
+        unreachable!()
    }

-    // TODO move to background task/softirq to reduce amount of code run by the irq handler
-    pub fn handle_rx<F: FnMut(DmaBuffer<[u8]>, usize)>(
+    fn setup_tx(
        &mut self,
-        dma: &dyn DmaAllocator,
-        head: u16,
-        mut handler: F,
-    ) -> u16 {
-        let capacity = self.descriptors.len();
-        while self.tail != head {
-            let index = self.tail as usize;
-            // Replace the buffer
-
-            let new_buffer = DmaBuffer::new_uninit_slice(dma, self.buffer_size).unwrap();
-            let new_buffer_address = new_buffer.bus_address();
-            let buffer = mem::replace(&mut self.buffers[index], new_buffer);
-            let buffer = unsafe { DmaBuffer::assume_init_slice(buffer) };
-
-            let descriptor = &mut self.descriptors[index];
-
-            if descriptor.errors & !1 != 0 {
-                log::warn!("igbe: drop erroneous packet {:#x}", descriptor.errors);
-            } else {
-                let len = descriptor.length as usize;
-                handler(buffer, len);
-            }
-
-            // Replace the descriptor
-            *descriptor = RxDescriptor::new(new_buffer_address, self.buffer_size as u16);
-
-            self.tail = (self.tail + 1) & (capacity as u16 - 1);
+        buffer_address: BusAddress,
+        size: usize,
+        index: usize,
+        capacity: usize,
+    ) -> Result<(), Error> {
+        if !(4..16288).contains(&size) {
+            return Err(Error::InvalidArgument);
        }
-
-        (self.tail + capacity as u16 - 1) & (capacity as u16 - 1)
-    }
-}
-
-impl TxRing {
-    pub fn with_capacity(dma: &dyn DmaAllocator, capacity: usize) -> Result<Self, Error> {
-        let buffers = (0..capacity).map(|_| None).collect::<Vec<_>>();
-        let descriptors = DmaBuffer::new_slice_with(dma, |_| TxDescriptor::empty(), capacity)?;
-        Ok(Self {
-            descriptors,
-            buffers,
-            head: 0,
-            tail: 0,
-        })
-    }
-
-    pub fn handle_tx(&mut self, head: u16) {
-        self.tail = head;
-    }
-
-    pub fn tx_now(&mut self, buffer: DmaBuffer<[u8]>) -> Result<u16, DmaBuffer<[u8]>> {
-        // Queue full
-        let capacity = self.descriptors.len();
-        if (self.head + 1) & (capacity as u16 - 1) == self.tail {
-            log::warn!("igbe: tx queue full");
-            return Err(buffer);
-        }
-        let index = self.head as usize;
-
-        let descriptor = &mut self.descriptors[index];
-        // Only generate interrupts for every 1/4th of the buffer
        let quarter = capacity / 4;
-        descriptor.setup_tx(
-            buffer.bus_address(),
-            buffer.len() as u16 - 4,
-            index % quarter == quarter - 1,
-        );
-        self.descriptors.cache_flush_element(index, true);
-
-        self.buffers[index] = Some(buffer);
-
-        self.head = (self.head + 1) & (capacity as u16 - 1);
-        Ok(self.head)
+        let ioc = index % quarter == quarter - 1;
+        let mut cmd = Self::CMD_EOP | Self::CMD_IFCS;
+        if ioc {
+            cmd |= Self::CMD_RS;
+        }
+        self.address = buffer_address.into_u64();
+        self.length = size as u16 - 4;
+        self.css = 0;
+        self.cso = 0;
+        self.sta = 0;
+        self.cmd = cmd;
+        self.special = 0;
+        Ok(())
    }
 }

-impl RxDescriptor {
-    pub fn new(address: BusAddress, length: u16) -> Self {
-        Self {
-            address,
-            length,
+impl GenericRxDescriptor for RxDescriptor {
+    fn consume(&mut self) -> Option<Result<usize, Error>> {
+        if self.status & Self::STA_DD == 0 {
+            None
+        } else if self.errors & !1 != 0 {
+            Some(Err(Error::InvalidArgument))
+        } else {
+            Some(Ok(self.length as _))
+        }
+    }
+
+    fn setup_rx(
+        buffer_address: BusAddress,
+        buffer_size: usize,
+        _last: bool,
+    ) -> Result<Self, Error> {
+        Ok(Self {
+            address: buffer_address.into_u64(),
+            length: buffer_size as _,
            checksum: 0,
            status: 0,
            errors: 0,
            special: 0,
-        }
+        })
    }
 }

@@ -170,31 +106,8 @@ impl TxDescriptor {
    // const CMD_IC: u8 = 1 << 2;
    // Report status
    const CMD_RS: u8 = 1 << 3;
-
-    pub const fn empty() -> Self {
-        Self {
-            address: BusAddress::ZERO,
-            length: 0,
-            cso: 0,
-            cmd: 0,
-            sta: Self::STA_DD,
-            _0: 0,
-            css: 0,
-            special: 0,
-        }
-    }
-
-    pub fn setup_tx(&mut self, address: BusAddress, length: u16, ioc: bool) {
-        let mut cmd = Self::CMD_EOP | Self::CMD_IFCS;
-        if ioc {
-            cmd |= Self::CMD_RS;
-        }
-        self.address = address;
-        self.length = length;
-        self.css = 0;
-        self.cso = 0;
-        self.sta = 0;
-        self.cmd = cmd;
-        self.special = 0;
-    }
+}
+
+impl RxDescriptor {
+    const STA_DD: u8 = 1 << 0;
 }
@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_net_loopback"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -29,12 +29,13 @@ use regs::{
    },
    mtl::{MTLOMR, MTLRXQiOMR, MTLTXQiOMR},
 };
-use ring::{RxDescriptor, RxRing, TxDescriptor, TxRing};
+use ring::{RxDescriptor, TxDescriptor};
 use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
 use ygg_driver_net_core::{
    RxPacket,
    ephy::{GBESR, PhyAccess},
    interface::{NetworkDevice, NetworkInterfaceType},
+    util::GenericQueue,
 };
 use yggdrasil_abi::net::{
    MacAddress,
@@ -48,9 +49,7 @@ pub mod ring;

 struct Inner {
    regs: IrqSafeSpinlock<DeviceMemoryIo<'static, Regs>>,
-
-    tx_ring: IrqSafeSpinlock<TxRing>,
-    rx_ring: IrqSafeSpinlock<RxRing>,
+    queue: GenericQueue<TxDescriptor, RxDescriptor>,
 }

 struct Stmmac {
@@ -105,12 +104,12 @@ impl Stmmac {

    pub fn start_xmit(&self, frame: DmaBuffer<[u8]>) -> Result<(), Error> {
        let inner = self.inner.get();
-        let regs = inner.regs.lock();
+        let index = inner.queue.try_push_xmit(frame)?;

-        let mut tx_ring = inner.tx_ring.lock();
-        let index = tx_ring.push_xmit(frame)?;
-        let ring_pos = tx_ring
-            .buffer_base()
+        let regs = inner.regs.lock();
+        let ring_pos = inner
+            .queue
+            .tx_buffer_base()
            .add(size_of::<TxDescriptor>() * index)
            .try_into_u32()
            .unwrap();
@@ -134,17 +133,17 @@ impl Stmmac {
            }

            if events & Self::SOFTIRQ_TX_STATUS != 0 {
-                inner.tx_ring.lock().consume().ok();
+                inner.queue.consume_tx().ok();
            }

            if events & Self::SOFTIRQ_RX_STATUS != 0 {
-                let mut rx_ring = inner.rx_ring.lock();
-                rx_ring
-                    .consume(dma.as_ref(), |packet| {
+                inner
+                    .queue
+                    .consume_rx(dma.as_ref(), None, |packet, _| {
                        let packet = RxPacket::new(packet, 0, iface);
                        ygg_driver_net_core::receive_packet(packet).ok();
                    })
-                    .ok();
+                    .expect("Rx failed");
            }
        }
    }
@@ -230,10 +229,10 @@ impl Device for Stmmac {
        );

        // Setup DMA Tx/Rx rings
-        let tx_ring = TxRing::with_capacity(dma.as_ref(), tx_ring_capacity)?;
-        let rx_ring = RxRing::with_capacity(dma.as_ref(), rx_ring_capacity)?;
-        let tx_ring_base = tx_ring.buffer_base().try_into_u32().unwrap();
-        let rx_ring_base = rx_ring.buffer_base().try_into_u32().unwrap();
+        let queue =
+            GenericQueue::with_capacity(dma.as_ref(), tx_ring_capacity, rx_ring_capacity, 4096)?;
+        let tx_ring_base = queue.tx_buffer_base().try_into_u32()?;
+        let rx_ring_base = queue.rx_buffer_base().try_into_u32()?;

        regs.DMA.DMAC0TXRLR.set(tx_ring_capacity as u32 - 1);
        regs.DMA.DMAC0TXDLAR.set(tx_ring_base);
@@ -338,9 +337,7 @@ impl Device for Stmmac {

        self.inner.init(Inner {
            regs: IrqSafeSpinlock::new(regs),
-
-            tx_ring: IrqSafeSpinlock::new(tx_ring),
-            rx_ring: IrqSafeSpinlock::new(rx_ring),
+            queue,
        });

        let iface =
@@ -1,26 +1,5 @@
-use core::mem::{self, MaybeUninit};
-
-use alloc::vec::Vec;
-use device_api::dma::DmaAllocator;
-use libk::{
-    dma::{BusAddress, DmaBuffer},
-    error::Error,
-};
-
-pub struct TxRing {
-    entries: DmaBuffer<[TxDescriptor]>,
-    buffers: Vec<Option<DmaBuffer<[u8]>>>,
-
-    wr: usize,
-    rd: usize,
-}
-
-pub struct RxRing {
-    entries: DmaBuffer<[RxDescriptor]>,
-    buffers: Vec<DmaBuffer<[MaybeUninit<u8>]>>,
-
-    rd: usize,
-}
+use libk::{dma::BusAddress, error::Error};
+use ygg_driver_net_core::util::{GenericRxDescriptor, GenericTxDescriptor};

 #[derive(Clone, Copy, Debug)]
 #[repr(C)]
@@ -40,215 +19,79 @@ pub struct RxDescriptor {
    rdes3: u32,
 }

-impl TxRing {
-    pub fn with_capacity(dma: &dyn DmaAllocator, capacity: usize) -> Result<Self, Error> {
-        let entries = DmaBuffer::new_slice(dma, TxDescriptor::empty(), capacity)?;
-        let buffers = (0..capacity).map(|_| None).collect();
-        Ok(Self {
-            entries,
-            buffers,
-
-            wr: 0,
-            rd: 0,
-        })
-    }
-
-    pub fn buffer_base(&self) -> BusAddress {
-        self.entries.bus_address()
-    }
-
-    pub fn capacity(&self) -> usize {
-        self.entries.len()
-    }
-
-    pub fn can_xmit(&self) -> bool {
-        self.wr.wrapping_add(1) != self.rd
-    }
-
-    pub fn outstanding_tx(&self) -> bool {
-        self.wr != self.rd
-    }
-
-    pub fn push_xmit(&mut self, frame: DmaBuffer<[u8]>) -> Result<usize, Error> {
-        if !self.can_xmit() {
-            return Err(Error::WouldBlock);
-        }
-
-        let address = frame.bus_address();
-        let frame_len = frame.len();
-
-        let capacity = self.entries.len();
-        let index = self.wr % capacity;
-        assert!(self.buffers[index].is_none());
-
-        frame.cache_flush_all(true);
-        self.entries[index].setup_tx(address, frame_len, true)?;
-        self.entries.cache_flush_element(index, true);
-
-        self.buffers[index] = Some(frame);
-        self.wr = self.wr.wrapping_add(1);
-
-        Ok(self.wr % self.capacity())
-    }
-
-    pub fn consume(&mut self) -> Result<usize, Error> {
-        let mut count = 0;
-
-        loop {
-            let index = self.rd % self.entries.len();
-            let entry = &self.entries[index];
-
-            if self.rd == self.wr {
-                break;
-            }
-
-            if let Some(status) = entry.tx_status() {
-                if status != 0 {
-                    log::warn!("tx_ring[{index}] error: {status:#x}");
-                }
-                let _ = self.buffers[index].take().unwrap();
-                self.rd = self.rd.wrapping_add(1);
-                count += 1;
-            } else {
-                break;
-            }
-        }
-
-        Ok(count)
-    }
-}
-
 impl TxDescriptor {
    const TDES3_OWN: u32 = 1 << 31;
    const TDES3_FD: u32 = 1 << 29;
    const TDES3_LD: u32 = 1 << 28;
    const TDES2_IOC: u32 = 1 << 31;
+}

-    pub const fn empty() -> Self {
-        Self {
-            tdes0: 0,
-            tdes1: 0,
-            tdes2: 0,
-            tdes3: 0,
-        }
-    }
+impl GenericTxDescriptor for TxDescriptor {
+    const EMPTY: Self = Self {
+        tdes0: 0,
+        tdes1: 0,
+        tdes2: 0,
+        tdes3: 0,
+    };

-    pub fn tx_status(&self) -> Option<u32> {
+    fn consume(&mut self) -> Option<Result<(), Error>> {
        if self.tdes3 & Self::TDES3_OWN == 0 {
-            Some(self.tdes3 & !(0xFFFF << 16))
+            // Some(self.tdes3 & !(0xFFFF << 16))
+            Some(Ok(()))
        } else {
            None
        }
    }

-    pub fn setup_tx(
+    fn setup_tx(
        &mut self,
-        frame: BusAddress,
-        frame_len: usize,
-        ioc: bool,
+        buffer_address: BusAddress,
+        size: usize,
+        _index: usize,
+        _capacity: usize,
    ) -> Result<(), Error> {
-        let tdes0 = frame.try_into_u32().map_err(|_| Error::InvalidArgument)?;
-        if frame_len & !0x3FFF != 0 {
+        if size & !0x3FFF != 0 {
            return Err(Error::InvalidArgument);
        }
-        let mut tdes2 = frame_len as u32;
-        if ioc {
-            tdes2 |= Self::TDES2_IOC;
-        }
-        let tdes3 = Self::TDES3_OWN | Self::TDES3_FD | Self::TDES3_LD;
-
-        self.tdes0 = tdes0;
+        // TODO ioc only on quarter buffer
+        self.tdes0 = buffer_address.try_into_u32()?;
        self.tdes1 = 0;
-        self.tdes2 = tdes2;
-        self.tdes3 = tdes3;
+        self.tdes2 = size as u32 | Self::TDES2_IOC;
+        self.tdes3 = Self::TDES3_OWN | Self::TDES3_LD | Self::TDES3_FD;
        Ok(())
    }
 }

-impl RxRing {
-    pub fn with_capacity(dma: &dyn DmaAllocator, capacity: usize) -> Result<Self, Error> {
-        let mut entries = DmaBuffer::new_slice(dma, RxDescriptor::empty(), capacity)?;
-        let buffers = (0..capacity)
-            .map(|_| DmaBuffer::new_uninit_slice(dma, 4096))
-            .collect::<Result<Vec<_>, _>>()?;
-        for i in 0..capacity {
-            entries[i].setup_rx(buffers[i].bus_address(), true)?;
-        }
-        Ok(Self {
-            buffers,
-            entries,
-
-            rd: 0,
-        })
-    }
-
-    pub fn buffer_base(&self) -> BusAddress {
-        self.entries.bus_address()
-    }
-
-    pub fn consume<F: Fn(DmaBuffer<[u8]>)>(
-        &mut self,
-        dma: &dyn DmaAllocator,
-        packet_handler: F,
-    ) -> Result<usize, Error> {
-        let mut count = 0;
-
-        loop {
-            let index = self.rd % self.entries.len();
-            let entry = &mut self.entries[index];
-
-            if entry.rx_completed().is_some() {
-                // Grab the current buffer (the one just written to by the DMA), replace it
-                // with the newly allocated one, and mark the descriptor as DMA-owned again
-                let new_buffer = DmaBuffer::new_uninit_slice(dma, 4096)?;
-                let new_buffer_address = new_buffer.bus_address();
-                let buffer = mem::replace(&mut self.buffers[index], new_buffer);
-                let buffer = unsafe { DmaBuffer::assume_init_slice(buffer) };
-                // TODO packet size hint
-                packet_handler(buffer);
-                entry.setup_rx(new_buffer_address, true)?;
-                self.rd = self.rd.wrapping_add(1);
-                count += 1;
-            } else {
-                break;
-            }
-        }
-
-        Ok(count)
-    }
-}
-
 impl RxDescriptor {
    const RDES3_OWN: u32 = 1 << 31;
    const RDES3_IOC: u32 = 1 << 30;
    const RDES3_BUF1V: u32 = 1 << 24;
+}

-    pub const fn empty() -> Self {
-        Self {
-            rdes0: 0,
-            rdes1: 0,
-            rdes2: 0,
-            rdes3: 0,
-        }
-    }
-
-    pub fn rx_completed(&self) -> Option<usize> {
+impl GenericRxDescriptor for RxDescriptor {
+    fn consume(&mut self) -> Option<Result<usize, Error>> {
        if self.rdes3 & Self::RDES3_OWN == 0 {
-            Some((self.rdes3 & 0x7FFF) as usize)
+            Some(Ok((self.rdes3 & 0x7FFF) as usize))
        } else {
            None
        }
    }

-    pub fn setup_rx(&mut self, buffer: BusAddress, ioc: bool) -> Result<(), Error> {
-        self.rdes0 = buffer.try_into_u32().map_err(|_| Error::InvalidArgument)?;
-        self.rdes1 = 0;
-        self.rdes2 = 0;
-        self.rdes3 = Self::RDES3_BUF1V;
-        if ioc {
-            self.rdes3 |= Self::RDES3_IOC;
-        }
-        self.rdes3 |= Self::RDES3_OWN;
-        Ok(())
+    fn setup_rx(
+        buffer_address: BusAddress,
+        _buffer_size: usize,
+        _last: bool,
+    ) -> Result<Self, Error> {
+        let rdes0 = buffer_address.try_into_u32()?;
+        let rdes1 = 0;
+        let rdes2 = 0;
+        // TODO ioc
+        let rdes3 = Self::RDES3_BUF1V | Self::RDES3_IOC | Self::RDES3_OWN;
+        Ok(Self {
+            rdes0,
+            rdes1,
+            rdes2,
+            rdes3,
+        })
    }
 }
@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_usb_xhci"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 [dependencies]
@@ -1,6 +1,5 @@
 #![no_std]
 #![allow(clippy::new_without_default)]
-#![feature(iter_array_chunks)]

 extern crate alloc;

@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_virtio_core"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -272,7 +272,7 @@ impl DescriptorTable {
        visitor: F,
    ) -> u16 {
        debug_assert_ne!(count, 0);
-        let mut current = self.first_free.unwrap_unchecked();
+        let mut current = unsafe { self.first_free.unwrap_unchecked() };
        let head = current;
        for i in 0..count {
            let descriptor = &mut self.descriptors[current as usize];
@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_virtio_gpu"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -1,7 +1,7 @@
 [package]
 name = "ygg_driver_virtio_net"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -263,7 +263,7 @@ impl<T: Transport + 'static> Device for VirtioNet<T> {
    unsafe fn init(self: Arc<Self>, _cx: DeviceInitContext) -> Result<(), Error> {
        let status = self.begin_init()?;

-        self.setup_queues()?;
+        unsafe { self.setup_queues() }?;

        self.finish_init(status);

@@ -1,7 +1,7 @@
 [package]
 name = "device-api"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
@@ -1,7 +1,7 @@
 [package]
 name = "device-api-macros"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
@@ -1,6 +1,6 @@
 use core::{
    fmt,
-    ops::{Div, Mul},
+    ops::{Div, Mul, Shr},
 };

 #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
@@ -48,6 +48,20 @@ impl From<u64> for Hertz {
    }
 }

+impl From<Hertz> for u64 {
+    fn from(value: Hertz) -> Self {
+        value.0
+    }
+}
+
+impl Shr<u32> for Hertz {
+    type Output = Hertz;
+
+    fn shr(self, rhs: u32) -> Self::Output {
+        Self(self.0 >> rhs)
+    }
+}
+
 impl Mul<u32> for Hertz {
    type Output = Hertz;

@@ -7,11 +7,13 @@ pub use freq::{Hertz, IntoHertz};

 mod freq;

+#[derive(Clone)]
 pub struct ClockHandle {
    pub parent: Arc<dyn ClockController>,
    pub clock: Option<u32>,
 }

+#[derive(Clone)]
 pub struct ResetHandle {
    pub parent: Arc<dyn ResetController>,
    pub reset: Option<u32>,
@@ -4,7 +4,8 @@ use core::{
    sync::atomic::{AtomicU16, AtomicU32, Ordering},
 };

-use alloc::sync::Arc;
+use alloc::{boxed::Box, sync::Arc};
+use async_trait::async_trait;
 use yggdrasil_abi::{error::Error, io::device::i2c::I2CMasterInfo, process::ProcessId};

 use crate::{
@@ -20,6 +21,17 @@ pub struct I2CDevice {
    user: AtomicU32,
 }

+pub enum I2CMessage<'a> {
+    Read(&'a mut [u8]),
+    Write(&'a [u8]),
+}
+
+pub struct I2CTransfer<'a> {
+    pub repeat_start: bool,
+    pub messages: &'a mut [I2CMessage<'a>],
+}
+
+#[async_trait]
 pub trait I2CController: Device {
    fn bus_number(&self) -> u32;
    fn child_number(&self) -> Option<u32>;
@@ -27,8 +39,13 @@ pub trait I2CController: Device {
    fn set_speed(&self, speed: Hertz) -> Result<Hertz, Error>;
    fn capabilities(&self) -> I2CMasterInfo;

-    fn i2c_write(&self, address: I2CAddress, buffer: &[u8]) -> Result<usize, Error>;
-    fn i2c_read(&self, address: I2CAddress, buffer: &mut [u8]) -> Result<usize, Error>;
+    async fn i2c_transfer(
+        &self,
+        address: I2CAddress,
+        transfer: &mut I2CTransfer,
+    ) -> Result<usize, Error>;
+    // async fn i2c_write(&self, address: I2CAddress, buffer: &[u8]) -> Result<usize, Error>;
+    // async fn i2c_read(&self, address: I2CAddress, buffer: &mut [u8]) -> Result<usize, Error>;
 }

 impl I2CAddress {
@@ -134,11 +151,11 @@ impl I2CDevice {

 impl Device for I2CDevice {
    unsafe fn init(self: Arc<Self>, cx: DeviceInitContext) -> Result<(), Error> {
-        self.device.clone().init(cx)
+        unsafe { self.device.clone().init(cx) }
    }

    unsafe fn init_irq(self: Arc<Self>) -> Result<(), Error> {
-        self.device.clone().init_irq()
+        unsafe { self.device.clone().init_irq() }
    }

    fn display_name(&self) -> &str {
@@ -34,10 +34,19 @@ pub enum IrqTrigger {
    Level,
 }

+#[derive(Default, Clone, Copy, Debug, PartialEq, Eq)]
+pub enum IrqPriority {
+    Low,
+    #[default]
+    Normal,
+    High,
+}
+
 #[derive(Default, Clone, Copy, Debug, PartialEq, Eq)]
 pub struct IrqOptions {
    pub level: IrqLevel,
    pub trigger: IrqTrigger,
+    pub priority: IrqPriority,
 }

 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
@@ -152,6 +161,18 @@ impl IrqHandle {
        self.intc.register_irq(self.irq, self.options, handler)
    }

+    pub fn register_with_priority(
+        &self,
+        priority: IrqPriority,
+        handler: Arc<dyn InterruptHandler>,
+    ) -> Result<(), Error> {
+        let options = IrqOptions {
+            priority,
+            ..self.options
+        };
+        self.intc.register_irq(self.irq, options, handler)
+    }
+
    pub fn enable(&self) -> Result<(), Error> {
        self.intc.enable_irq(self.irq)
    }
@@ -1,4 +1,3 @@
-#![feature(trait_alias)]
 #![no_std]
 #![allow(clippy::new_without_default)]

@@ -10,6 +9,7 @@ pub mod device;
 pub mod gpio;
 pub mod i2c;
 pub mod interrupt;
+pub mod pwm;
 pub mod serial;
 pub mod spi;
 pub mod timer;
@@ -0,0 +1,55 @@
+use alloc::sync::Arc;
+use yggdrasil_abi::error::Error;
+
+use crate::device::Device;
+
+pub enum PwmChannelMode {
+    OneShot,
+    Repeat,
+}
+
+#[derive(Debug)]
+pub struct PwmControllerInfo {
+    // If true, channel period can be configured individually,
+    // if false, channel 0 is used to set the period, and cannot be used to output PWM
+    pub per_channel_period: bool,
+    pub channel_count: usize,
+}
+
+pub struct PwmControllerDevice {
+    pub device: Arc<dyn PwmController>,
+}
+
+pub struct PwmChannelDevice {
+    pub device: Arc<dyn PwmController>,
+    pub channel: u32,
+}
+
+pub trait PwmController: Device {
+    fn controller_info(&self) -> Result<PwmControllerInfo, Error>;
+
+    fn channel_period(&self, channel: u32) -> Result<u64, Error>;
+    fn set_channel_period(&self, channel: u32, period: u64) -> Result<u64, Error>;
+    fn duty_cycle(&self, channel: u32) -> Result<u64, Error>;
+    fn set_duty_cycle(&self, channel: u32, t: u64) -> Result<(), Error>;
+
+    fn stop_channel(&self, channel: u32) -> Result<(), Error>;
+}
+
+impl From<Arc<dyn PwmController>> for PwmControllerDevice {
+    fn from(value: Arc<dyn PwmController>) -> Self {
+        Self { device: value }
+    }
+}
+
+impl Device for PwmControllerDevice {
+    fn display_name(&self) -> &str {
+        self.device.display_name()
+    }
+}
+
+impl Device for PwmChannelDevice {
+    fn display_name(&self) -> &str {
+        self.device.display_name()
+    }
+}
@@ -11,6 +11,13 @@ use crate::{DeviceTreePropertyRead, TProp, driver::DeviceTreeGpioPins};

 use super::{Node, lookup_phandle};

+pub(crate) struct InterruptIter<'dt> {
+    pub(crate) interrupts: TProp<'dt>,
+    pub(crate) interrupt_parent: Arc<Node>,
+    pub(crate) interrupt_cells: usize,
+    pub(crate) offset: usize,
+}
+
 pub(crate) struct ClockIter<'dt> {
    pub(crate) clocks: TProp<'dt>,
    pub(crate) offset: usize,
@@ -27,6 +34,19 @@ pub(crate) struct GpioIter<'o, 'dt> {
    pub(crate) offset: usize,
 }

+impl Iterator for InterruptIter<'_> {
+    type Item = IrqHandle;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        if self.offset >= self.interrupts.len() {
+            return None;
+        }
+        let irq = map_interrupt_at(&self.interrupt_parent, &self.interrupts, self.offset)?;
+        self.offset += self.interrupt_cells;
+        Some(irq)
+    }
+}
+
 impl Iterator for ClockIter<'_> {
    type Item = ClockHandle;

@@ -22,7 +22,9 @@ use yggdrasil_abi::error::Error;
 use crate::{
    DeviceTree, DeviceTreeNodeExt, DeviceTreePropertyRead, TNode, TProp,
    driver::{
-        DeviceTreeGpioPins, DeviceTreeSyscon, controller::GpioIter, traits::DeviceTreePinController,
+        DeviceTreeGpioPins, DeviceTreeSyscon,
+        controller::{GpioIter, InterruptIter},
+        traits::DeviceTreePinController,
    },
    tree,
 };
@@ -402,6 +404,19 @@ impl Node {
            .and_then(|i| self.reset(i))
    }

+    /// Returns an iterator over the node's interrupts
+    pub fn interrupts(&self) -> Option<impl Iterator<Item = IrqHandle>> {
+        let interrupts = self.property("interrupts")?;
+        let interrupt_parent = self.interrupt_controller()?;
+        let interrupt_cells = interrupt_parent.self_interrupt_cells()?;
+        Some(InterruptIter {
+            interrupts,
+            interrupt_parent,
+            interrupt_cells,
+            offset: 0,
+        })
+    }
+
    /// Returns an iterator over the node's input clocks
    pub fn clocks(&self) -> Option<impl Iterator<Item = ClockHandle>> {
        let clocks = self.property("clocks")?;
@@ -10,7 +10,7 @@
 //! * `pl011` - basic peripheral usage with `reg` and `interrupts`
 //! * `gic` in aarch64 - interrupt controller/mapper implementation
 #![cfg_attr(any(not(test), rust_analyzer), no_std)]
-#![feature(trait_alias, decl_macro)]
+#![feature(decl_macro)]
 #![allow(clippy::type_complexity)]
 #![warn(missing_docs)]

@@ -1,6 +1,6 @@
 [package]
 name = "module-build"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
@@ -1,7 +1,7 @@
 [package]
 name = "vmalloc"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"
 authors = ["Mark Poliakov <mark@alnyan.me>"]

 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
@@ -6,7 +6,6 @@

 #![deny(missing_docs)]
 #![no_std]
-#![feature(linked_list_cursors)]

 extern crate alloc;

@@ -1,7 +1,7 @@
 [package]
 name = "libk-mm"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 [dependencies]
 yggdrasil-abi.workspace = true
@@ -1,7 +1,7 @@
 [package]
 name = "libk-mm-interface"
 version = "0.1.0"
-edition = "2021"
+edition = "2024"

 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html

@@ -93,13 +93,15 @@ impl<N: DevicePageTableLevel, L: DevicePageTableLevel> DevicePageManager<N, L> {
                .ok_or(Error::OutOfMemory)?;
            let mapped_address = mapped_base + large_offset;

-            Ok(RawDeviceMemoryMapping::from_raw_parts(
-                large_aligned_base.into_u64(),
-                mapped_address,
-                mapped_base,
-                large_page_count,
-                L::Level::SIZE,
-            ))
+            Ok(unsafe {
+                RawDeviceMemoryMapping::from_raw_parts(
+                    large_aligned_base.into_u64(),
+                    mapped_address,
+                    mapped_base,
+                    large_page_count,
+                    L::Level::SIZE,
+                )
+            })
        } else {
            // Allocate from small page pool
            let mapped_base = self
@@ -108,13 +110,15 @@ impl<N: DevicePageTableLevel, L: DevicePageTableLevel> DevicePageManager<N, L> {
                .ok_or(Error::OutOfMemory)?;
            let mapped_address = mapped_base + small_offset;

-            Ok(RawDeviceMemoryMapping::from_raw_parts(
-                small_aligned_base.into_u64(),
-                mapped_address,
-                mapped_base,
-                small_page_count,
-                N::Level::SIZE,
-            ))
+            Ok(unsafe {
+                RawDeviceMemoryMapping::from_raw_parts(
+                    small_aligned_base.into_u64(),
+                    mapped_address,
+                    mapped_base,
+                    small_page_count,
+                    N::Level::SIZE,
+                )
+            })
        }
    }

@@ -125,17 +129,19 @@ impl<N: DevicePageTableLevel, L: DevicePageTableLevel> DevicePageManager<N, L> {
        &mut self,
        mapping: &RawDeviceMemoryMapping<A>,
    ) {
-        if mapping.page_size == N::Level::SIZE {
-            self.normal
-                .remove_mapping(mapping.base_address, mapping.page_count);
-        } else if mapping.page_size == L::Level::SIZE {
-            self.large
-                .remove_mapping(mapping.base_address, mapping.page_count);
-        } else {
-            unreachable!(
-                "Invalid device memory mapping with page size {:#x}",
-                mapping.page_size
-            )
+        unsafe {
+            if mapping.page_size == N::Level::SIZE {
+                self.normal
+                    .remove_mapping(mapping.base_address, mapping.page_count);
+            } else if mapping.page_size == L::Level::SIZE {
+                self.large
+                    .remove_mapping(mapping.base_address, mapping.page_count);
+            } else {
+                unreachable!(
+                    "Invalid device memory mapping with page size {:#x}",
+                    mapping.page_size
+                )
+            }
        }
    }
 }
@@ -1,5 +1,5 @@
 #![no_std]
-#![feature(step_trait, const_trait_impl)]
+#![feature(step_trait)]

 use core::ops::{Deref, DerefMut};

@@ -33,7 +33,7 @@ impl<'a, T: Sized, K: KernelTableManager> PhysicalRefMut<'a, T, K> {
    /// contains T. The caller must also take care of access synchronization and make sure no
    /// aliasing occurs.
    pub unsafe fn map(physical: PhysicalAddress) -> PhysicalRefMut<'a, T, K> {
-        let value = virtualize_raw::<_, K>(physical);
+        let value = unsafe { virtualize_raw::<_, K>(physical) };
        PhysicalRefMut {
            value,
            _pd: PhantomData,
@@ -48,7 +48,7 @@ impl<'a, T: Sized, K: KernelTableManager> PhysicalRefMut<'a, T, K> {
    /// contains [T; len]. The caller must also take care of access synchronization and make
    /// sure no aliasing occurs.
    pub unsafe fn map_slice(physical: PhysicalAddress, len: usize) -> PhysicalRefMut<'a, [T], K> {
-        let value = virtualize_slice_raw::<_, K>(physical, len);
+        let value = unsafe { virtualize_slice_raw::<_, K>(physical, len) };
        PhysicalRefMut {
            value,
            _pd: PhantomData,
@@ -66,7 +66,9 @@ impl<T: ?Sized, K: KernelTableManager> PhysicalRefMut<'_, T, K> {

 impl<T: ?Sized, K: KernelTableManager> AsPhysicalAddress for PhysicalRefMut<'_, T, K> {
    unsafe fn as_physical_address(&self) -> PhysicalAddress {
-        PhysicalAddress::raw_from_virtualized::<K>(PhysicalRefMut::<T, K>::as_address(self))
+        unsafe {
+            PhysicalAddress::raw_from_virtualized::<K>(PhysicalRefMut::<T, K>::as_address(self))
+        }
    }
 }

@@ -106,7 +108,7 @@ impl<'a, T: Sized, K: KernelTableManager> PhysicalRef<'a, T, K> {
    /// The caller must ensure the correct origin of the physical address as well that it actually
    /// contains T.
    pub unsafe fn map(physical: PhysicalAddress) -> PhysicalRef<'a, T, K> {
-        let value = virtualize_raw::<_, K>(physical);
+        let value = unsafe { virtualize_raw::<_, K>(physical) };
        PhysicalRef {
            value,
            _pd: PhantomData,
@@ -121,7 +123,7 @@ impl<'a, T: Sized, K: KernelTableManager> PhysicalRef<'a, T, K> {
    /// The caller must ensure the correct origin of the physical address as well that it actually
    /// contains [T; len].
    pub unsafe fn map_slice(physical: PhysicalAddress, len: usize) -> PhysicalRef<'a, [T], K> {
-        let value = virtualize_slice_raw::<_, K>(physical, len);
+        let value = unsafe { virtualize_slice_raw::<_, K>(physical, len) };
        PhysicalRef {
            value,
            _pd: PhantomData,
@@ -139,7 +141,7 @@ impl<T: ?Sized, K: KernelTableManager> PhysicalRef<'_, T, K> {

 impl<T: ?Sized, K: KernelTableManager> AsPhysicalAddress for PhysicalRef<'_, T, K> {
    unsafe fn as_physical_address(&self) -> PhysicalAddress {
-        PhysicalAddress::raw_from_virtualized::<K>(PhysicalRef::<T, K>::as_address(self))
+        unsafe { PhysicalAddress::raw_from_virtualized::<K>(PhysicalRef::<T, K>::as_address(self)) }
    }
 }

@@ -162,7 +164,7 @@ unsafe fn virtualize_raw<'a, T: Sized, K: KernelTableManager>(
 ) -> &'a mut T {
    // TODO check align
    let address = physical.raw_virtualize::<K>();
-    &mut *(address as *mut T)
+    unsafe { &mut *(address as *mut T) }
 }

 unsafe fn virtualize_slice_raw<'a, T: Sized, K: KernelTableManager>(
@@ -171,5 +173,5 @@ unsafe fn virtualize_slice_raw<'a, T: Sized, K: KernelTableManager>(
 ) -> &'a mut [T] {
    // TODO check align
    let address = physical.raw_virtualize::<K>();
-    core::slice::from_raw_parts_mut(address as *mut T, len)
+    unsafe { core::slice::from_raw_parts_mut(address as *mut T, len) }
 }
@@ -100,7 +100,7 @@ pub trait EntryLevelDrop {
    /// Caller must ensure the unmapped range is not in use by some other thread and will not be
    /// referred to from this point.
    unsafe fn drop_all<TA: TableAllocator>(&mut self) {
-        self.drop_range::<TA>(Self::FULL_RANGE)
+        unsafe { self.drop_range::<TA>(Self::FULL_RANGE) }
    }
 }

@@ -50,7 +50,7 @@ impl DeviceMemoryMapping {
        size: usize,
        attrs: DeviceMemoryAttributes,
    ) -> Result<Self, Error> {
-        let inner = RawDeviceMemoryMapping::map(base.into_u64(), size, attrs)?;
+        let inner = unsafe { RawDeviceMemoryMapping::map(base.into_u64(), size, attrs)? };
        let address = inner.address;
        Ok(Self {
            inner: Arc::new(inner),
@@ -78,7 +78,7 @@ impl<'a, T: Sized> DeviceMemoryIo<'a, T> {
            todo!();
        }
        // TODO check align
-        let value = &*(inner.address as *const T);
+        let value = unsafe { &*(inner.address as *const T) };
        Ok(DeviceMemoryIo { inner, value })
    }

@@ -94,8 +94,8 @@ impl<'a, T: Sized> DeviceMemoryIo<'a, T> {
        attrs: DeviceMemoryAttributes,
    ) -> Result<DeviceMemoryIo<'a, [T]>, Error> {
        let layout = Layout::array::<T>(count).unwrap();
-        let inner = RawDeviceMemoryMapping::map(base.into_u64(), layout.size(), attrs)?;
-        let value = core::slice::from_raw_parts(inner.address as *mut T, count);
+        let inner = unsafe { RawDeviceMemoryMapping::map(base.into_u64(), layout.size(), attrs)? };
+        let value = unsafe { core::slice::from_raw_parts(inner.address as *mut T, count) };

        Ok(DeviceMemoryIo {
            inner: Arc::new(inner),
@@ -113,8 +113,8 @@ impl<'a, T: Sized> DeviceMemoryIo<'a, T> {
        base: PhysicalAddress,
        attrs: DeviceMemoryAttributes,
    ) -> Result<DeviceMemoryIo<'a, T>, Error> {
-        let inner = RawDeviceMemoryMapping::map(base.into_u64(), size_of::<T>(), attrs)?;
-        let value = &*(inner.address as *const T);
+        let inner = unsafe { RawDeviceMemoryMapping::map(base.into_u64(), size_of::<T>(), attrs)? };
+        let value = unsafe { &*(inner.address as *const T) };

        Ok(DeviceMemoryIo {
            inner: Arc::new(inner),
@@ -139,7 +139,7 @@ impl<'a, T: ?Sized> DeviceMemoryIo<'a, T> {

        DeviceMemoryIo {
            inner: self.inner.clone(),
-            value: &*value,
+            value: unsafe { &*value },
        }
    }
 }
@@ -175,8 +175,8 @@ impl<'a, T: Sized> DeviceMemoryIoMut<'a, T> {
        attrs: DeviceMemoryAttributes,
    ) -> Result<DeviceMemoryIoMut<'a, [T]>, Error> {
        let layout = Layout::array::<T>(len).unwrap();
-        let inner = RawDeviceMemoryMapping::map(base.into_u64(), layout.size(), attrs)?;
-        let value = core::slice::from_raw_parts_mut(inner.address as *mut T, len);
+        let inner = unsafe { RawDeviceMemoryMapping::map(base.into_u64(), layout.size(), attrs)? };
+        let value = unsafe { core::slice::from_raw_parts_mut(inner.address as *mut T, len) };

        Ok(DeviceMemoryIoMut { inner, value })
    }
@@ -59,7 +59,7 @@ unsafe impl GlobalAlloc for KernelAllocator {

    unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
        let ptr = NonNull::new(ptr).unwrap();
-        self.inner.lock().free(ptr, layout);
+        unsafe { self.inner.lock().free(ptr, layout) };
    }
 }

@@ -1,10 +1,4 @@
-#![feature(
-    slice_ptr_get,
-    step_trait,
-    const_trait_impl,
-    maybe_uninit_as_bytes,
-    negative_impls
-)]
+#![feature(slice_ptr_get, maybe_uninit_as_bytes, negative_impls)]
 #![no_std]

 extern crate alloc;
@@ -46,7 +40,7 @@ impl TableAllocator for TableAllocatorImpl {
    }

    unsafe fn free_page_table(address: PhysicalAddress) {
-        phys::free_page(address)
+        unsafe { phys::free_page(address) }
    }
 }

@@ -138,7 +132,7 @@ impl<T> PageBox<T, GlobalPhysicalAllocator> {
    /// Unsafe: converts a raw physical address back into a [PageBox]. Only intended to be used
    /// for allocations previously converted to [PhysicalAddress] via [PageBox::into_physical_raw].
    pub unsafe fn from_physical_raw(address: PhysicalAddress) -> PageBox<T> {
-        PageBox::from_physical_raw_in(address)
+        unsafe { PageBox::from_physical_raw_in(address) }
    }

    pub fn from_slice(slice: &[T]) -> Result<PageBox<[T]>, Error>
@@ -335,7 +329,7 @@ impl<T, A: PhysicalMemoryAllocator<Address = PhysicalAddress>> PageBox<MaybeUnin
        // 1. MaybeUninit<T> is transparent
        // 2. self.value still points to the same memory and is not deallocated
        let page_count = self.page_count;
-        let value = MaybeUninit::assume_init_mut(&mut *self.value);
+        let value = unsafe { MaybeUninit::assume_init_mut(&mut *self.value) };

        // Prevent deallocation of the PageBox with MaybeUninit
        core::mem::forget(self);
@@ -363,7 +357,7 @@ impl<T, A: PhysicalMemoryAllocator<Address = PhysicalAddress>> PageBox<[MaybeUni
        // 1. MaybeUninit<T> is transparent
        // 2. self.value still points to the same memory and is not deallocated
        let page_count = self.page_count;
-        let value = (&mut *self.value).assume_init_mut();
+        let value = unsafe { (&mut *self.value).assume_init_mut() };

        core::mem::forget(self);

@@ -380,7 +374,7 @@ impl<T, A: PhysicalMemoryAllocator<Address = PhysicalAddress>> PageBox<[MaybeUni
    ///
    /// See [MaybeUninit::slice_assume_init_ref]
    pub unsafe fn assume_init_slice_ref(&self) -> &[T] {
-        (&*self.value).assume_init_ref()
+        unsafe { (&*self.value).assume_init_ref() }
    }

    /// Returns a mutable reference to the slice data with [MaybeUninit] removed.
@@ -389,7 +383,7 @@ impl<T, A: PhysicalMemoryAllocator<Address = PhysicalAddress>> PageBox<[MaybeUni
    ///
    /// See [MaybeUninit::slice_assume_init_mut]
    pub unsafe fn assume_init_slice_mut(&mut self) -> &mut [T] {
-        (&mut *self.value).assume_init_mut()
+        unsafe { (&mut *self.value).assume_init_mut() }
    }

    /// Fills a slice of MaybeUninit<T> with zeroes.
@@ -400,7 +394,7 @@ impl<T, A: PhysicalMemoryAllocator<Address = PhysicalAddress>> PageBox<[MaybeUni
    /// trivial types.
    pub unsafe fn zero(p: &mut Self) {
        let ptr = p.as_mut_ptr() as *mut u8;
-        let slice = core::slice::from_raw_parts_mut(ptr, p.page_count * L3_PAGE_SIZE);
+        let slice = unsafe { core::slice::from_raw_parts_mut(ptr, p.page_count * L3_PAGE_SIZE) };
        slice.fill(0);
    }
 }
@@ -49,10 +49,12 @@ impl PhysicalMemoryManager {
        page_count: usize,
    ) -> PhysicalMemoryManager {
        let bitmap_len = page_count.div_ceil(BITMAP_WORD_SIZE);
-        let mut bitmap = PhysicalRefMut::<'static, _, KernelTableManagerImpl>::map_slice(
-            bitmap_phys_base,
-            bitmap_len,
-        );
+        let mut bitmap = unsafe {
+            PhysicalRefMut::<'static, _, KernelTableManagerImpl>::map_slice(
+                bitmap_phys_base,
+                bitmap_len,
+            )
+        };

        bitmap.fill(BitmapWord::MAX);

@@ -132,7 +134,10 @@ impl PhysicalMemoryManager {

    /// Allocates a contiguous range of physical pages, marking it as used with `usage`
    pub fn alloc_contiguous_pages(&mut self, count: usize) -> Result<PhysicalAddress, Error> {
-        'l0: for i in self.last_free_bit..self.page_count {
+        if count >= self.page_count {
+            return Err(Error::OutOfMemory);
+        }
+        'l0: for i in self.last_free_bit..self.page_count - count {
            for j in 0..count {
                if self.is_alloc(i + j) {
                    continue 'l0;
@@ -164,8 +169,13 @@ impl PhysicalMemoryManager {
    /// `addr` must be a page-aligned physical address previously allocated by this implementation.
    pub unsafe fn free_page(&mut self, page: PhysicalAddress) {
        let page = page.try_into_usize().unwrap();
-        assert!(page >= self.offset);
+        if page < self.offset {
+            panic!("Physical page below managed area: {page:#x}");
+        }
        let index = (page - self.offset) / L3_PAGE_SIZE;
+        if index >= self.page_count {
+            panic!("Physical page above managed area: {page:#x}");
+        }

        STATS.used_pages.fetch_sub(1, Ordering::Relaxed);

--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
alnyan	236820fad4	WIP: Fix TLS issues on riscv64	2026-03-28 01:58:09 +02:00
alnyan	69cc9a2eaa	WIP: migrate to 1.94.0 toolchain, broken riscv64	2026-03-27 17:10:20 +02:00
alnyan	7f256cf3a6	i2c: improve i2c architecture, add sifive i2c driver	2026-03-25 19:07:59 +02:00
alnyan	f416414b93	char: add pwm subsystem, add sifive pwm driver	2026-03-23 14:02:02 +02:00
alnyan	0386e3916d	maint: fix irq priority addition for aarch64/x86_64	2026-03-20 16:01:26 +02:00
alnyan	31176fb5aa	riscv: initial support for hifive unmatched	2026-03-20 15:24:55 +02:00
alnyan	1411f1eed0	maint: update rustc to 1.95.0-nightly	2026-03-19 10:51:42 +02:00
alnyan	4c5309fa15	rsh: add rcp, remote copy program	2026-02-08 14:57:12 +02:00
alnyan	1012abceec	cross: add unix i2c/spi stubs	2026-02-07 16:11:15 +02:00
alnyan	a6a6dba155	net/stmmac: use GenericQueue	2026-02-07 15:47:40 +02:00
alnyan	7f46da9ebd	net: unify netdev tx/rx queue interface	2026-02-07 14:13:09 +02:00
alnyan	1a87bc3666	sifive: support for cadence gemgxl ethernet	2026-02-05 17:10:14 +02:00
alnyan	4f648142c8	sifive: initial support for hifive unleashed a00	2026-02-04 17:34:37 +02:00