549 lines
16 KiB
Rust
549 lines
16 KiB
Rust
//! x86-64 architecture implementation
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use core::{mem::size_of, ops::DerefMut, sync::atomic::Ordering};
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use abi::error::Error;
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use acpi_lib::{mcfg::Mcfg, AcpiTables, InterruptModel};
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use alloc::boxed::Box;
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use device_api::{
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interrupt::{ExternalInterruptController, MessageInterruptController},
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timer::MonotonicTimestampProviderDevice,
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Device,
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};
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use git_version::git_version;
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use kernel_fs::devfs;
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use libk_mm::{
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address::{FromRaw, IntoRaw, PhysicalAddress},
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device::{DeviceMemoryAttributes, RawDeviceMemoryMapping},
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phys::PhysicalMemoryRegion,
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table::EntryLevelExt,
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};
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use libk_util::{sync::SpinFence, OneTimeInit};
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use yboot_proto::{v1::AvailableMemoryRegion, LoadProtocolV1};
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use ygg_driver_pci::PciBusManager;
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mod acpi;
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mod apic;
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mod boot;
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pub mod context;
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pub mod cpu;
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mod cpuid;
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mod exception;
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mod gdt;
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mod intrinsics;
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pub mod mem;
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mod peripherals;
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mod registers;
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mod smp;
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mod syscall;
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use crate::{
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arch::x86_64::{
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intrinsics::{IoPort, IoPortAccess},
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mem::{
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map_heap_block,
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table::{PageTable, L2},
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HEAP_MAPPING_OFFSET,
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},
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},
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debug::{self, LogLevel},
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device::{
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self,
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display::{console, fb_console::FramebufferConsole, linear_fb::LinearFramebuffer},
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},
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fs::{Initrd, INITRD_DATA},
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mem::{
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heap,
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phys::{self, reserved::reserve_region},
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table::EntryLevel,
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},
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};
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use self::{
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acpi::{AcpiAllocator, AcpiHandlerImpl},
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apic::{ioapic::IoApic, local::LocalApic},
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boot::BootData,
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cpu::Cpu,
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cpuid::{ProcessorFeatures, PROCESSOR_FEATURES},
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mem::{
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init_fixed_tables,
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table::{PageAttributes, PageEntry, L1, L3},
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EarlyMapping, MEMORY_LIMIT, RAM_MAPPING_L1, RAM_MAPPING_OFFSET,
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},
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peripherals::{i8253::I8253, ps2::PS2Controller, serial::ComPort},
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smp::CPU_COUNT,
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};
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use super::{CpuAccess, CpuMessage, Platform};
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/// x86-64-specific interrupt number
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#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
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pub enum IrqNumber {
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/// Legacy (ISA) interrupt
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Isa(u8),
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/// Global System Interrupt
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Gsi(u8),
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}
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/// x86-64 architecture implementation
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pub struct X86_64 {
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boot_data: OneTimeInit<BootData>,
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acpi: OneTimeInit<AcpiTables<AcpiHandlerImpl>>,
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// Display
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framebuffer: OneTimeInit<LinearFramebuffer>,
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fbconsole: OneTimeInit<FramebufferConsole>,
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ioapic: OneTimeInit<IoApic>,
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timer: OneTimeInit<I8253>,
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}
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static SHUTDOWN_FENCE: SpinFence = SpinFence::new();
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/// Global x86-64 architecture value
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pub static PLATFORM: X86_64 = X86_64 {
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boot_data: OneTimeInit::new(),
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acpi: OneTimeInit::new(),
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framebuffer: OneTimeInit::new(),
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fbconsole: OneTimeInit::new(),
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ioapic: OneTimeInit::new(),
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timer: OneTimeInit::new(),
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};
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impl Platform for X86_64 {
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const KERNEL_VIRT_OFFSET: usize = 0xFFFFFF8000000000;
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type IrqNumber = IrqNumber;
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type L3 = mem::table::L3;
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unsafe fn start_application_processors(&self) {
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if let Some(acpi) = self.acpi.try_get() {
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let Some(pinfo) = acpi
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.platform_info_in(AcpiAllocator)
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.ok()
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.and_then(|p| p.processor_info)
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else {
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return;
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};
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smp::start_ap_cores(&pinfo);
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}
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}
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fn cpu_count() -> usize {
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CPU_COUNT.load(Ordering::Acquire)
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}
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#[inline]
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unsafe fn map_device_memory(
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&self,
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base: PhysicalAddress,
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size: usize,
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attrs: DeviceMemoryAttributes,
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) -> Result<RawDeviceMemoryMapping, Error> {
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mem::map_device_memory(base, size, attrs)
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}
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#[inline]
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unsafe fn unmap_device_memory(&self, map: &RawDeviceMemoryMapping) {
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mem::unmap_device_memory(map)
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}
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fn map_physical_memory<I: Iterator<Item = PhysicalMemoryRegion> + Clone>(
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&self,
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it: I,
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_memory_start: PhysicalAddress,
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memory_end: PhysicalAddress,
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) -> Result<(), Error> {
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let end_l1i = (IntoRaw::<usize>::into_raw(memory_end) + (1 << 30) - 1) >> 30;
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if end_l1i > 512 {
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todo!(
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"Cannot handle {}GiB of RAM",
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end_l1i * L1::SIZE / (1024 * 1024 * 1024)
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);
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}
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MEMORY_LIMIT.init(memory_end.into_raw());
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// Check if 1GiB pages are supported
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if PROCESSOR_FEATURES
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.get()
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.contains(ProcessorFeatures::PDPE1GB)
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{
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// Just map gigabytes of RAM
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for l1i in 0..end_l1i {
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// TODO NX
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unsafe {
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RAM_MAPPING_L1[l1i] = PageEntry::<L1>::block(
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PhysicalAddress::from_raw(l1i << 30),
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PageAttributes::WRITABLE,
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);
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}
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}
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} else {
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// Allocate the intermediate tables first
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let l2_tables_start = phys::find_contiguous_region(it, end_l1i)
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.expect("Could not allocate the memory for RAM mapping L2 tables");
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unsafe {
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reserve_region(
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"ram-l2-tables",
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PhysicalMemoryRegion {
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base: l2_tables_start,
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size: end_l1i * 0x1000,
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},
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);
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}
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// Fill in the tables
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for l1i in 0..end_l1i {
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let l2_phys_addr = l2_tables_start.add(l1i * 0x1000);
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// TODO (minor) the slice is uninitialized, maybe find some way to deal with that
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// case nicely
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// Safety: ok, the mapping is done to the memory obtained from
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// find_contiguous_region()
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let mut l2_data =
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unsafe { EarlyMapping::<[PageEntry<L2>; 512]>::map(l2_phys_addr)? };
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// Safety: ok, the slice comes from EarlyMapping of a page-aligned region
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let l2 = unsafe { PageTable::from_raw_slice_mut(l2_data.deref_mut()) };
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for l2i in 0..512 {
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// TODO NX
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l2[l2i] = PageEntry::<L2>::block(
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PhysicalAddress::from_raw((l1i << 30) | (l2i << 21)),
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PageAttributes::WRITABLE,
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);
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}
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// Point the L1 entry to the L2 table
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unsafe {
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RAM_MAPPING_L1[l1i] =
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PageEntry::<L1>::table(l2_phys_addr, PageAttributes::WRITABLE)
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};
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intrinsics::flush_cpu_cache();
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// The EarlyMapping is then dropped
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}
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}
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Ok(())
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}
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#[inline]
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fn virtualize(address: u64) -> usize {
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let address = address as usize;
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if address < *mem::MEMORY_LIMIT.get() {
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address + RAM_MAPPING_OFFSET
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} else {
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panic!("Invalid physical address: {:#x}", address);
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}
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}
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#[inline]
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fn physicalize(address: usize) -> u64 {
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if address < RAM_MAPPING_OFFSET || address - RAM_MAPPING_OFFSET >= *mem::MEMORY_LIMIT.get()
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{
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panic!("Not a virtualized physical address: {:#x}", address);
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}
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(address - RAM_MAPPING_OFFSET) as _
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}
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fn external_interrupt_controller(
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&'static self,
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) -> &'static dyn ExternalInterruptController<IrqNumber = Self::IrqNumber> {
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self.ioapic.get()
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}
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fn message_interrupt_controller(&'static self) -> &'static dyn MessageInterruptController {
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Cpu::local().local_apic()
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}
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fn monotonic_timer(&'static self) -> &'static dyn MonotonicTimestampProviderDevice {
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self.timer.get()
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}
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}
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impl X86_64 {
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unsafe fn handle_ipi(&self, _msg: CpuMessage) {
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warnln!("Received an IPI");
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todo!();
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}
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fn set_boot_data(&self, data: BootData) {
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match data {
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BootData::YBoot(data) => {
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// Reserve the memory map
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unsafe {
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reserve_region(
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"mmap",
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PhysicalMemoryRegion {
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base: PhysicalAddress::from_raw(data.memory_map.address),
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size: data.memory_map.len as usize * size_of::<AvailableMemoryRegion>(),
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},
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);
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}
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// Reserve initrd, if not NULL
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if data.initrd_address != 0 && data.initrd_size != 0 {
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let aligned_start = data.initrd_address & !0xFFF;
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let aligned_end = (data.initrd_address + data.initrd_size + 0xFFF) & !0xFFF;
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unsafe {
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reserve_region(
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"initrd",
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PhysicalMemoryRegion {
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base: PhysicalAddress::from_raw(aligned_start),
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size: (aligned_end - aligned_start) as usize,
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},
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);
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}
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}
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}
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}
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self.boot_data.init(data);
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}
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unsafe fn init_physical_memory_from_yboot(data: &LoadProtocolV1) -> Result<(), Error> {
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let mmap = EarlyMapping::<AvailableMemoryRegion>::map_slice(
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PhysicalAddress::from_raw(data.memory_map.address),
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data.memory_map.len as usize,
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)?;
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phys::init_from_iter(mmap.as_ref().iter().map(|reg| PhysicalMemoryRegion {
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base: PhysicalAddress::from_raw(reg.start_address),
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size: reg.page_count as usize * 0x1000,
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}))
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}
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unsafe fn init_memory_management(&self) -> Result<(), Error> {
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const HEAP_PAGES: usize = 16;
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init_fixed_tables();
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// Reserve lower 4MiB just in case
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reserve_region(
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"lowmem",
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PhysicalMemoryRegion {
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base: PhysicalAddress::ZERO,
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size: 4 * 1024 * 1024,
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},
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);
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match self.boot_data.get() {
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&BootData::YBoot(data) => Self::init_physical_memory_from_yboot(data)?,
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}
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// Setup heap
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for i in 0..HEAP_PAGES {
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// Allocate in 2MiB chunks
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let l2_page = phys::alloc_2m_page()?;
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map_heap_block(i, l2_page);
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}
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heap::init_heap(HEAP_MAPPING_OFFSET, HEAP_PAGES * L2::SIZE);
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Ok(())
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}
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unsafe fn init_platform(&'static self, cpu_id: usize) -> Result<(), Error> {
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Cpu::init_local(LocalApic::new(), cpu_id as _);
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if cpu_id == 0 {
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// Register the PCI drivers
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// TODO make this implicit init
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ygg_driver_pci::register_class_driver(
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"NVMe Host Controller",
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0x01,
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Some(0x08),
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Some(0x02),
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ygg_driver_nvme::probe,
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);
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ygg_driver_pci::register_class_driver(
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"AHCI SATA Controller",
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0x01,
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Some(0x06),
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Some(0x01),
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ygg_driver_ahci::probe,
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);
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ygg_driver_pci::register_vendor_driver(
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"Virtio PCI Network Device",
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0x1AF4,
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0x1000,
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ygg_driver_virtio_net::probe,
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);
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match self.boot_data.get() {
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&BootData::YBoot(data) => {
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let start = PhysicalAddress::from_raw(data.initrd_address);
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Self::init_initrd(start, start.add(data.initrd_size as usize));
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}
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}
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self.init_acpi_from_boot_data()?;
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Self::disable_8259();
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self.timer.init(I8253::new());
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let com1_3 = Box::leak(Box::new(ComPort::new(0x3F8, 0x3E8, IrqNumber::Isa(4))));
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debug::add_sink(com1_3.port_a(), LogLevel::Debug);
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self.init_framebuffer()?;
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debug::init();
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infoln!(
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"Yggdrasil v{} ({})",
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env!("CARGO_PKG_VERSION"),
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git_version!()
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);
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let ps2 = Box::leak(Box::new(PS2Controller::new(
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IrqNumber::Isa(1),
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IrqNumber::Isa(12),
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0x64,
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0x60,
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)));
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ps2.init()?;
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if let Some(acpi) = self.acpi.try_get() {
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self.init_platform_from_acpi(acpi)?;
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}
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self.timer.get().init_irq()?;
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// ps2.connect(self.tty.get());
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ps2.init_irq()?;
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device::register_device(self.ioapic.get());
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device::register_device(ps2);
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PciBusManager::setup_bus_devices()?;
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}
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Ok(())
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}
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unsafe fn init_acpi_from_boot_data(&self) -> Result<(), Error> {
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match self.boot_data.get() {
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&BootData::YBoot(data) => self.init_acpi_from_rsdp(data.rsdp_address as usize),
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}
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}
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unsafe fn init_acpi_from_rsdp(&self, rsdp: usize) -> Result<(), Error> {
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let acpi_tables = AcpiTables::from_rsdp(AcpiHandlerImpl, rsdp).map_err(|err| {
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errorln!("Could not initialize ACPI tables: {:?}", err);
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Error::InvalidArgument
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})?;
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self.acpi.init(acpi_tables);
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Ok(())
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}
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unsafe fn init_platform_from_acpi(
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&self,
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acpi: &'static AcpiTables<AcpiHandlerImpl>,
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) -> Result<(), Error> {
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let platform_info = acpi.platform_info_in(AcpiAllocator).map_err(|err| {
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errorln!("Could not get ACPI platform info: {:?}", err);
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Error::InvalidArgument
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})?;
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let InterruptModel::Apic(apic_info) = platform_info.interrupt_model else {
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panic!("The processor does not support APIC");
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};
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self.ioapic.init(IoApic::from_acpi(&apic_info)?);
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// acpi::init_acpi(acpi).unwrap();
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if let Ok(mcfg) = acpi.find_table::<Mcfg>() {
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for entry in mcfg.entries() {
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PciBusManager::add_segment_from_mcfg(entry)?;
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}
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}
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Ok(())
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}
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unsafe fn init_framebuffer(&'static self) -> Result<(), Error> {
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match self.boot_data.get() {
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&BootData::YBoot(data) => {
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let info = &data.opt_framebuffer;
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self.framebuffer.init(LinearFramebuffer::from_physical_bits(
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PhysicalAddress::from_raw(info.res_address),
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info.res_size as usize,
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info.res_stride as usize,
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info.res_width,
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info.res_height,
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)?);
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}
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}
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self.fbconsole.init(FramebufferConsole::from_framebuffer(
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self.framebuffer.get(),
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None,
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)?);
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debug::add_sink(self.fbconsole.get(), LogLevel::Info);
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// self.tty.init(CombinedTerminal::new(self.fbconsole.get()));
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devfs::add_named_block_device(self.framebuffer.get(), "fb0")?;
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// devfs::add_char_device(self.tty.get(), CharDeviceType::TtyRegular)?;
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console::add_console_autoflush(self.fbconsole.get());
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Ok(())
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}
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fn init_initrd(initrd_start: PhysicalAddress, initrd_end: PhysicalAddress) {
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if initrd_start.is_zero() || initrd_end <= initrd_start {
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infoln!("No initrd loaded");
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return;
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}
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let start_aligned = initrd_start.page_align_down::<L3>();
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let end_aligned = initrd_start.page_align_up::<L3>();
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let data = unsafe {
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core::slice::from_raw_parts(
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start_aligned.virtualize_raw() as *const u8,
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initrd_end - initrd_start,
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)
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};
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let initrd = Initrd {
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phys_page_start: start_aligned,
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phys_page_len: end_aligned - start_aligned,
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data,
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};
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INITRD_DATA.init(initrd);
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}
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unsafe fn disable_8259() {
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infoln!("Disabling i8259 PIC");
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// TODO should I make a module for 8259 if I don't even use it?
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let pic_master_cmd = IoPort::<u8>::new(0x20);
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let pic_master_data = IoPort::<u8>::new(0x21);
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let pic_slave_cmd = IoPort::<u8>::new(0xA0);
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let pic_slave_data = IoPort::<u8>::new(0xA1);
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// Remap PIC IRQ vectors to 32..
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pic_master_cmd.write(0x11);
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pic_slave_cmd.write(0x11);
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pic_master_data.write(32);
|
|
pic_slave_data.write(32 + 8);
|
|
|
|
pic_slave_data.write(0xFF);
|
|
pic_master_data.write(0xFF);
|
|
|
|
pic_master_cmd.write(0x20);
|
|
pic_slave_cmd.write(0x20);
|
|
}
|
|
}
|