Mark
32 lines
1.4 KiB
Markdown
32 lines
1.4 KiB
Markdown
Local APIC
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==========
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LAPIC Base MSR
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--------------
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`IA32_LAPIC_BASE = 0x1B` model-specific register stores information about Local APIC
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status and its base address.
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Notable LAPIC registers
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-----------------------
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| Base offset | Name | Description |
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|------------:|---------------------|-------------------------------------------|
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| 0x20 | IA32_LAPIC_REG_ID | Local APIC ID register |
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| 0x80 | IA32_LAPIC_REG_TPR | Task Priority Register |
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| 0xB0 | IA32_LAPIC_REG_EOI | End of interrupt register |
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| 0xF0 | IA32_LAPIC_REG_SVR | Spurious Interrupt Vector Register |
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| 0x300 | IA32_LAPIC_REG_ICR0 | Interrupt Control Register, 31 .. 0 |
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| 0x310 | IA32_LAPIC_REG_ICR1 | Interrupt Control Register, 63 .. 32 |
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|-------------|---------------------|-------------------------------------------|
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Local APIC configuration sequence
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---------------------------------
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1. Mask all the interrupts in i8259
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2. Remap all of them properly so spurious interrupts don't generate exceptions
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3. Setup `LINTx` registers for LAPIC-originated (internal) interrupts
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4. Set the IRQ number spurious interrupts should be mapped to and soft-enable the
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LAPIC by writing `IA32_LAPIC_REG_SVR`
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5. Set the `IA32_LAPIC_REG_TPR` so that lower-priority interrupts don't get postponed
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