aarch64: Rework parse_typed_reg interface
parse_typed_reg returned a register number and passed the register type back using a pointer parameter. It seems simpler to return the register entry instead, since that has both pieces of information in one place. The patch also replaces the boolean in_reg_list parameter with a mask of flags. This hopefully makes calls easier to read (more self-documenting than "true" or "false"), but more importantly, it allows a later patch to add a second flag.
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@ -1006,19 +1006,19 @@ parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
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/* Parse a register of the type TYPE.
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Return PARSE_FAIL if the string pointed by *CCP is not a valid register
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Return null if the string pointed to by *CCP is not a valid register
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name or the parsed register is not of TYPE.
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Otherwise return the register number, and optionally fill in the actual
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type of the register in *RTYPE when multiple alternatives were given, and
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return the register shape and element index information in *TYPEINFO.
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Otherwise return the register, and optionally return the register
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shape and element index information in *TYPEINFO.
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IN_REG_LIST should be set with TRUE if the caller is parsing a register
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list. */
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FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list. */
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static int
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parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
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struct vector_type_el *typeinfo, bool in_reg_list)
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#define PTR_IN_REGLIST (1U << 0)
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static const reg_entry *
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parse_typed_reg (char **ccp, aarch64_reg_type type,
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struct vector_type_el *typeinfo, unsigned int flags)
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{
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char *str = *ccp;
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const reg_entry *reg = parse_reg (&str);
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@ -1036,14 +1036,14 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
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if (typeinfo)
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*typeinfo = atype;
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set_default_error ();
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return PARSE_FAIL;
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return NULL;
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}
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if (! aarch64_check_reg_type (reg, type))
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{
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DEBUG_TRACE ("reg type check failed");
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set_default_error ();
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return PARSE_FAIL;
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return NULL;
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}
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type = reg->type;
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@ -1053,12 +1053,12 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
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if (*str == '.')
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{
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if (!parse_vector_type_for_operand (type, &parsetype, &str))
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return PARSE_FAIL;
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return NULL;
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}
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else
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{
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if (!parse_predication_for_operand (&parsetype, &str))
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return PARSE_FAIL;
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return NULL;
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}
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/* Register if of the form Vn.[bhsdq]. */
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@ -1092,13 +1092,13 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
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if (!is_typed_vecreg)
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{
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first_error (_("this type of register can't be indexed"));
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return PARSE_FAIL;
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return NULL;
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}
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if (in_reg_list)
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if (flags & PTR_IN_REGLIST)
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{
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first_error (_("index not allowed inside register list"));
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return PARSE_FAIL;
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return NULL;
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}
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atype.defined |= NTA_HASINDEX;
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@ -1108,19 +1108,19 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
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if (exp.X_op != O_constant)
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{
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first_error (_("constant expression required"));
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return PARSE_FAIL;
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return NULL;
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}
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if (! skip_past_char (&str, ']'))
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return PARSE_FAIL;
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return NULL;
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atype.index = exp.X_add_number;
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}
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else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
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else if (!(flags & PTR_IN_REGLIST) && (atype.defined & NTA_HASINDEX) != 0)
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{
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/* Indexed vector register expected. */
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first_error (_("indexed vector register expected"));
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return PARSE_FAIL;
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return NULL;
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}
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/* A vector reg Vn should be typed or indexed. */
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@ -1132,44 +1132,25 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
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if (typeinfo)
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*typeinfo = atype;
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if (rtype)
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*rtype = type;
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*ccp = str;
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return reg->number;
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return reg;
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}
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/* Parse register.
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Return the register number on success; return PARSE_FAIL otherwise.
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If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
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the register (e.g. NEON double or quad reg when either has been requested).
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Return the register on success; return null otherwise.
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If this is a NEON vector register with additional type information, fill
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in the struct pointed to by VECTYPE (if non-NULL).
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This parser does not handle register list. */
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This parser does not handle register lists. */
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static int
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static const reg_entry *
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aarch64_reg_parse (char **ccp, aarch64_reg_type type,
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aarch64_reg_type *rtype, struct vector_type_el *vectype)
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struct vector_type_el *vectype)
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{
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struct vector_type_el atype;
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char *str = *ccp;
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int reg = parse_typed_reg (&str, type, rtype, &atype,
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/*in_reg_list= */ false);
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if (reg == PARSE_FAIL)
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return PARSE_FAIL;
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if (vectype)
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*vectype = atype;
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*ccp = str;
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return reg;
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return parse_typed_reg (ccp, type, vectype, 0);
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}
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static inline bool
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@ -1239,14 +1220,15 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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str++; /* skip over '-' */
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val_range = val;
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}
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val = parse_typed_reg (&str, type, NULL, &typeinfo,
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/*in_reg_list= */ true);
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if (val == PARSE_FAIL)
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const reg_entry *reg = parse_typed_reg (&str, type, &typeinfo,
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PTR_IN_REGLIST);
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if (!reg)
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{
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set_first_syntax_error (_("invalid vector register in list"));
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error = true;
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continue;
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}
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val = reg->number;
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/* reject [bhsd]n */
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if (type == REG_TYPE_VN && typeinfo.defined == 0)
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{
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@ -2271,18 +2253,18 @@ const pseudo_typeS md_pseudo_table[] = {
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static bool
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reg_name_p (char *str, aarch64_reg_type reg_type)
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{
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int reg;
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const reg_entry *reg;
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/* Prevent the diagnostics state from being spoiled. */
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if (error_p ())
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return false;
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reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
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reg = aarch64_reg_parse (&str, reg_type, NULL);
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/* Clear the parsing error that may be set by the reg parser. */
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clear_error ();
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if (reg == PARSE_FAIL)
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if (!reg)
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return false;
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skip_whitespace (str);
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@ -4957,8 +4939,8 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
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} while (0)
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#define po_reg_or_fail(regtype) do { \
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val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
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if (val == PARSE_FAIL) \
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reg = aarch64_reg_parse (&str, regtype, NULL); \
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if (!reg) \
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{ \
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set_default_error (); \
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goto failure; \
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@ -6344,7 +6326,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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int64_t val;
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const reg_entry *reg;
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int comma_skipped_p = 0;
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aarch64_reg_type rtype;
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struct vector_type_el vectype;
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aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier;
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aarch64_opnd_info *info = &inst.base.operands[i];
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@ -6443,16 +6424,17 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_Vd:
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case AARCH64_OPND_SVE_Vm:
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case AARCH64_OPND_SVE_Vn:
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val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
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if (val == PARSE_FAIL)
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reg = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, NULL);
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if (!reg)
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{
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first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
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goto failure;
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}
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gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
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gas_assert (reg->type >= REG_TYPE_FP_B
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&& reg->type <= REG_TYPE_FP_Q);
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info->reg.regno = val;
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info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
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info->reg.regno = reg->number;
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info->qualifier = AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B);
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break;
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case AARCH64_OPND_SVE_Pd:
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@ -6483,8 +6465,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Vm:
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reg_type = REG_TYPE_VN;
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vector_reg:
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val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
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if (val == PARSE_FAIL)
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reg = aarch64_reg_parse (&str, reg_type, &vectype);
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if (!reg)
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{
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first_error (_(get_reg_expected_msg (reg_type)));
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goto failure;
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@ -6492,7 +6474,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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if (vectype.defined & NTA_HASINDEX)
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goto failure;
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info->reg.regno = val;
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info->reg.regno = reg->number;
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if ((reg_type == REG_TYPE_PN || reg_type == REG_TYPE_ZN)
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&& vectype.type == NT_invtype)
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/* Unqualified Pn and Zn registers are allowed in certain
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@ -6509,8 +6491,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_VdD1:
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case AARCH64_OPND_VnD1:
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val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
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if (val == PARSE_FAIL)
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reg = aarch64_reg_parse (&str, REG_TYPE_VN, &vectype);
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if (!reg)
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{
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set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
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goto failure;
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@ -6521,7 +6503,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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(_("the top half of a 128-bit FP/SIMD register is expected"));
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goto failure;
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}
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info->reg.regno = val;
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info->reg.regno = reg->number;
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/* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
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here; it is correct for the purpose of encoding/decoding since
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only the register number is explicitly encoded in the related
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@ -6545,8 +6527,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SM3_IMM2:
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reg_type = REG_TYPE_VN;
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vector_reg_index:
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val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
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if (val == PARSE_FAIL)
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reg = aarch64_reg_parse (&str, reg_type, &vectype);
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if (!reg)
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{
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first_error (_(get_reg_expected_msg (reg_type)));
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goto failure;
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@ -6554,7 +6536,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
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goto failure;
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info->reglane.regno = val;
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info->reglane.regno = reg->number;
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info->reglane.index = vectype.index;
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info->qualifier = vectype_to_qualifier (&vectype);
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if (info->qualifier == AARCH64_OPND_QLF_NIL)
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@ -6576,13 +6558,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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&& get_opcode_dependent_value (opcode) == 1
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&& *str != '{')
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{
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val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
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if (val == PARSE_FAIL)
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reg = aarch64_reg_parse (&str, reg_type, &vectype);
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if (!reg)
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{
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first_error (_(get_reg_expected_msg (reg_type)));
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goto failure;
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}
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info->reglist.first_regno = val;
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info->reglist.first_regno = reg->number;
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info->reglist.num_regs = 1;
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}
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else
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