Support Intel MSRLIST

gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated.
2022-11-01 10:50:27 +08:00
parent 941f083324
commit 2188d6ea4f
15 changed files with 4284 additions and 4162 deletions
@@ -1,5 +1,7 @@
 -*- text -*-

+* Add support for Intel MSRLIST instructions.
+
 * Add support for Intel WRMSRNS instructions.

 * Add support for Intel CMPccXADD instructions.
@@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] =
  SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
  SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false),
  SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false),
+  SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false),
 };

 #undef SUBARCH
@@ -199,6 +199,7 @@ accept various extension mnemonics.  For example,
@code{avx_vnni_int8},
@code{cmpccxadd},
@code{wrmsrns},
+@code{msrlist},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1493,7 +1494,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
@item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
-@item @samp{.cmpccxadd} @tab @samp{.wrmsrns}
+@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@@ -482,6 +482,7 @@ if [gas_32_check] then {
    run_list_test "cmpccxadd-inval"
    run_dump_test "wrmsrns"
    run_dump_test "wrmsrns-intel"
+    run_list_test "msrlist-inval"
    run_list_test "sg"
    run_dump_test "clzero"
    run_dump_test "invlpgb"
@@ -1159,6 +1160,8 @@ if [gas_64_check] then {
    run_dump_test "x86-64-cmpccxadd-intel"
    run_dump_test "x86-64-wrmsrns"
    run_dump_test "x86-64-wrmsrns-intel"
+    run_dump_test "x86-64-msrlist"
+    run_dump_test "x86-64-msrlist-intel"
    run_dump_test "x86-64-clzero"
    run_dump_test "x86-64-mwaitx-bdver4"
    run_list_test "x86-64-mwaitx-reg"
@@ -0,0 +1,3 @@
+.* Assembler messages:
+.*:6: Error: `rdmsrlist' is only supported in 64-bit mode
+.*:7: Error: `wrmsrlist' is only supported in 64-bit mode
@@ -0,0 +1,7 @@
+# Check Illegal MSRLIST instructions
+
+	.allow_index_reg
+	.text
+_start:
+	rdmsrlist		 #MSRLIST
+	wrmsrlist		 #MSRLIST
@@ -0,0 +1,5 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 MSRLIST insns (Intel disassembly)
+#source: x86-64-msrlist.s
+#dump: x86-64-msrlist.d
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw
+#name: x86_64 MSRLIST insns
+#source: x86-64-msrlist.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
+\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist
+\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist
@@ -0,0 +1,10 @@
+# Check 64bit MSRLIST instructions
+
+	.text
+_start:
+	rdmsrlist		 #MSRLIST
+	wrmsrlist		 #MSRLIST
+
+.intel_syntax noprefix
+	rdmsrlist		 #MSRLIST
+	wrmsrlist		 #MSRLIST
@@ -1264,6 +1264,8 @@ enum
  X86_64_E9,
  X86_64_EA,
  X86_64_0F01_REG_0,
+  X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
+  X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
  X86_64_0F01_REG_1,
  X86_64_0F01_REG_1_RM_5_PREFIX_2,
  X86_64_0F01_REG_1_RM_6_PREFIX_2,
@@ -2960,6 +2962,9 @@ static const struct dis386 prefix_table[][4] = {
  /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
  {
    { "wrmsrns",        { Skip_MODRM }, 0 },
+    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
+    { Bad_Opcode },
+    { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
  },

  /* PREFIX_0F01_REG_1_RM_4 */
@@ -4286,6 +4291,18 @@ static const struct dis386 x86_64_table[][2] = {
    { "sgdt", { M }, 0 },
  },

+  /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
+  {
+    { Bad_Opcode },
+    { "wrmsrlist",	{ Skip_MODRM }, 0 },
+  },
+
+  /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
+  {
+    { Bad_Opcode },
+    { "rdmsrlist",	{ Skip_MODRM }, 0 },
+  },
+
  /* X86_64_0F01_REG_1 */
  {
    { "sidt{Q|Q}", { M }, 0 },
@@ -255,6 +255,8 @@ static initializer cpu_flag_init[] =
    "CpuCMPCCXADD" },
  { "CPU_WRMSRNS_FLAGS",
    "CpuWRMSRNS" },
+  { "CPU_MSRLIST_FLAGS",
+    "CpuMSRLIST" },
  { "CPU_IAMCU_FLAGS",
    "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
  { "CPU_ADX_FLAGS",
@@ -459,6 +461,8 @@ static initializer cpu_flag_init[] =
    "CpuCMPCCXADD" },
  { "CPU_ANY_WRMSRNS_FLAGS",
    "CpuWRMSRNS" },
+  { "CPU_ANY_MSRLIST_FLAGS",
+    "CpuMSRLIST" },
 };

 static initializer operand_type_init[] =
@@ -663,6 +667,7 @@ static bitfield cpu_flags[] =
  BITFIELD (CpuAVX_VNNI_INT8),
  BITFIELD (CpuCMPCCXADD),
  BITFIELD (CpuWRMSRNS),
+  BITFIELD (CpuMSRLIST),
  BITFIELD (CpuMWAITX),
  BITFIELD (CpuCLZERO),
  BITFIELD (CpuOSPKE),
@@ -219,6 +219,8 @@ enum
  CpuCMPCCXADD,
  /* Intel WRMSRNS Instructions support required */
  CpuWRMSRNS,
+  /* Intel MSRLIST Instructions support required.  */
+  CpuMSRLIST,
  /* mwaitx instruction required */
  CpuMWAITX,
  /* Clzero instruction required */
@@ -405,6 +407,7 @@ typedef union i386_cpu_flags
      unsigned int cpuavx_vnni_int8:1;
      unsigned int cpucmpccxadd:1;
      unsigned int cpuwrmsrns:1;
+      unsigned int cpumsrlist:1;
      unsigned int cpumwaitx:1;
      unsigned int cpuclzero:1;
      unsigned int cpuospke:1;
@@ -3301,3 +3301,10 @@ cmp<cc>xadd, 0x66e<cc:opc>, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVV
 wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}

 // WRMSRNS instruction end.
+
+// MSRLIST instructions.
+
+rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+
+// MSRLIST instructions end.