aarch64: Tweak parsing of integer & FP registers
Integer registers were parsed indirectly through aarch64_reg_parse_32_64 (and thus aarch64_addr_reg_parse) rather than directly through parse_reg. This was because we need the qualifier associated with the register, and the logic to calculate that was buried in aarch64_addr_reg_parse. The code that parses FP registers had the same need, but it open-coded the calculation of the qualifier. This patch tries to handle both cases in the same way. It is needed by a later patch that tries to improve the register-related diagnostics.
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@ -801,6 +801,38 @@ parse_reg (char **ccp)
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return reg;
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}
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/* Return the operand qualifier associated with all uses of REG, or
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AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either
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that qualifiers don't apply to REG or that qualifiers are added
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using suffixes. */
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static aarch64_opnd_qualifier_t
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inherent_reg_qualifier (const reg_entry *reg)
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{
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switch (reg->type)
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{
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case REG_TYPE_R_32:
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case REG_TYPE_SP_32:
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case REG_TYPE_Z_32:
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return AARCH64_OPND_QLF_W;
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case REG_TYPE_R_64:
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case REG_TYPE_SP_64:
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case REG_TYPE_Z_64:
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return AARCH64_OPND_QLF_X;
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case REG_TYPE_FP_B:
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case REG_TYPE_FP_H:
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case REG_TYPE_FP_S:
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case REG_TYPE_FP_D:
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case REG_TYPE_FP_Q:
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return AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B);
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default:
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return AARCH64_OPND_QLF_NIL;
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}
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}
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/* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
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return FALSE. */
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static bool
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@ -828,18 +860,6 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
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switch (reg->type)
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{
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case REG_TYPE_R_32:
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case REG_TYPE_SP_32:
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case REG_TYPE_Z_32:
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*qualifier = AARCH64_OPND_QLF_W;
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break;
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case REG_TYPE_R_64:
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case REG_TYPE_SP_64:
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case REG_TYPE_Z_64:
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*qualifier = AARCH64_OPND_QLF_X;
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break;
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case REG_TYPE_ZN:
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if ((reg_type_masks[reg_type] & (1 << REG_TYPE_ZN)) == 0
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|| str[0] != '.')
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@ -859,7 +879,10 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
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break;
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default:
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return NULL;
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if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
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return NULL;
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*qualifier = inherent_reg_qualifier (reg);
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break;
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}
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*ccp = str;
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@ -4744,15 +4767,15 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
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} \
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} while (0)
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#define po_int_reg_or_fail(reg_type) do { \
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reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
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#define po_int_fp_reg_or_fail(reg_type) do { \
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reg = parse_reg (&str); \
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if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
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{ \
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set_default_error (); \
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goto failure; \
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} \
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info->reg.regno = reg->number; \
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info->qualifier = qualifier; \
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info->qualifier = inherent_reg_qualifier (reg); \
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} while (0)
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#define po_imm_nc_or_fail() do { \
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@ -6163,7 +6186,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Rt_SYS:
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case AARCH64_OPND_PAIRREG:
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case AARCH64_OPND_SVE_Rm:
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po_int_reg_or_fail (REG_TYPE_R_Z);
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po_int_fp_reg_or_fail (REG_TYPE_R_Z);
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/* In LS64 load/store instructions Rt register number must be even
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and <=22. */
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@ -6186,7 +6209,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_Rt_SP:
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case AARCH64_OPND_SVE_Rn_SP:
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case AARCH64_OPND_Rm_SP:
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po_int_reg_or_fail (REG_TYPE_R_SP);
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po_int_fp_reg_or_fail (REG_TYPE_R_SP);
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break;
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case AARCH64_OPND_Rm_EXT:
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@ -6221,17 +6244,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_Vd:
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case AARCH64_OPND_SVE_Vm:
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case AARCH64_OPND_SVE_Vn:
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reg = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, NULL);
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if (!reg)
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{
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first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
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goto failure;
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}
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gas_assert (reg->type >= REG_TYPE_FP_B
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&& reg->type <= REG_TYPE_FP_Q);
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info->reg.regno = reg->number;
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info->qualifier = AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B);
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po_int_fp_reg_or_fail (REG_TYPE_BHSDQ);
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break;
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case AARCH64_OPND_SVE_Pd:
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