RISC-V: Fix disassembling Zfinx with -M numeric

This commit fixes floating point operand register names from ABI ones
to dynamically set ones.

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
	Zfinx extension and -M numeric disassembler option.
	* testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
	names to disassemble Zfinx instructions.

gas/testsuite/gas/riscv/zfinx-dis-numeric.d

@@ -0,0 +1,10 @@
+#as: -march=rv64ima_zfinx
+#source: zfinx-dis-numeric.s
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+a0c5a553[ 	]+feq.s[ 	]+x10,x11,x12

gas/testsuite/gas/riscv/zfinx-dis-numeric.s

@@ -0,0 +1,2 @@
+target:
+	feq.s	a0, a1, a2

opcodes/riscv-dis.c

@@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
       /* If arch has ZFINX flags, use gpr for disassemble.  */
       if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
-	riscv_fpr_names = riscv_gpr_names_abi;
+	riscv_fpr_names = riscv_gpr_names;
 
       for (; op->name; op++)
 	{