Support Intel AVX-VNNI-INT16
gas/ChangeLog: * NEWS: Support Intel AVX-VNNI-INT16. * config/tc-i386.c: Add avx_vnni_int16. * doc/c-i386.texi: Document avx_vnni_int16. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/avx-vnni-int16.d: New test. * testsuite/gas/i386/avx-vnni-int16.s: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38D2_W_0): New. (PREFIX_VEX_0F38D3_W_0): Ditto. (VEX_W_0F38D2_P_0): Ditto. (VEX_W_0F38D2_P_1): Ditto. (VEX_W_0F38D2_P_2): Ditto. (VEX_W_0F38D3_P_0): Ditto. (VEX_W_0F38D3_P_1): Ditto. (VEX_W_0F38D3_P_2): Ditto. (prefix_table): Add PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. (vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3. (vex_w_table): Ditto. * i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16. (cpu_flag): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: (CpuAVX_VNNI_INT16): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions. * i386-tbl.h: Regenerated.
This commit is contained in:
konglin1
Haochen Jiang
@@ -1,5 +1,7 @@
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-*- text -*-
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* Add support for Intel AVX-VNNI-INT16 instructions.
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Changes in 2.41:
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* Add support for Intel FRED instructions.
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@@ -1151,6 +1151,7 @@ static const arch_entry cpu_arch[] =
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SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false),
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SUBARCH (fred, FRED, ANY_FRED, false),
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SUBARCH (lkgs, LKGS, ANY_LKGS, false),
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SUBARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, false),
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};
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#undef SUBARCH
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+3
-2
@@ -207,6 +207,7 @@ accept various extension mnemonics. For example,
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@code{rao_int},
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@code{fred},
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@code{lkgs},
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@code{avx_vnni_int16},
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@code{amx_int8},
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@code{amx_bf16},
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@code{amx_fp16},
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@@ -1635,8 +1636,8 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
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@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
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@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
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@item @samp{.avx_ne_convert} @tab @samp{.rao_int}
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@item @samp{.fred} @tab @samp{.lkgs}
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@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
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@item @samp{.avx_vnni_int16}
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@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
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@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
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@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
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@@ -0,0 +1,129 @@
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#objdump: -dw -Mintel
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#name: i386 AVX-VNNI-INT16 insns (Intel disassembly)
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#source: avx-vnni-int16.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 56 d2 b4 f4 00 00 00 10\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 56 d2 31\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 b4 f4 00 00 00 10\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 31\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 56 d3 b4 f4 00 00 00 10\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 31\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
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\s*[a-f0-9]+:\s*c4 e2 52 d3 b4 f4 00 00 00 10\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 52 d3 31\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 55 d2 b4 f4 00 00 00 10\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 55 d2 31\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
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\s*[a-f0-9]+:\s*c4 e2 51 d2 b4 f4 00 00 00 10\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 51 d2 31\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 55 d3 b4 f4 00 00 00 10\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 55 d3 31\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
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\s*[a-f0-9]+:\s*c4 e2 51 d3 b4 f4 00 00 00 10\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 51 d3 31\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 54 d2 b4 f4 00 00 00 10\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 54 d2 31\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
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\s*[a-f0-9]+:\s*c4 e2 50 d2 b4 f4 00 00 00 10\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 50 d2 31\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 54 d3 b4 f4 00 00 00 10\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 54 d3 31\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
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\s*[a-f0-9]+:\s*c4 e2 50 d3 b4 f4 00 00 00 10\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 50 d3 31\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 56 d2 b4 f4 00 00 00 10\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 56 d2 31\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 b4 f4 00 00 00 10\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 31\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 56 d3 b4 f4 00 00 00 10\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 31\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
|
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\s*[a-f0-9]+:\s*c4 e2 52 d3 b4 f4 00 00 00 10\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 52 d3 31\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[ecx\]
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\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
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\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
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\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd ymm6,ymm5,ymm4
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\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd xmm6,xmm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 55 d2 b4 f4 00 00 00 10\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 55 d2 31\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[ecx\]
|
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\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
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\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
|
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\s*[a-f0-9]+:\s*c4 e2 51 d2 b4 f4 00 00 00 10\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 e2 51 d2 31\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[ecx\]
|
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\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
|
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\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b4 f4 00 00 00 10\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 31\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[ecx\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b4 f4 00 00 00 10\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 31\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[ecx\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b4 f4 00 00 00 10\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 31\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[ecx\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b4 f4 00 00 00 10\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 31\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[ecx\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b4 f4 00 00 00 10\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 31\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[ecx\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[ecx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b4 f4 00 00 00 10\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 31\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[ecx\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[ecx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
@@ -0,0 +1,129 @@
|
||||
#objdump: -dw
|
||||
#name: i386 AVX-VNNI-INT16 insns
|
||||
#source: avx-vnni-int16.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b4 f4 00 00 00 10\s+vpdpwsud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 31\s+vpdpwsud \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b4 f4 00 00 00 10\s+vpdpwsud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 31\s+vpdpwsud \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b4 f4 00 00 00 10\s+vpdpwsuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 31\s+vpdpwsuds \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b4 f4 00 00 00 10\s+vpdpwsuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 31\s+vpdpwsuds \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b4 f4 00 00 00 10\s+vpdpwusd 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 31\s+vpdpwusd \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b4 f4 00 00 00 10\s+vpdpwusd 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 31\s+vpdpwusd \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b4 f4 00 00 00 10\s+vpdpwusds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 31\s+vpdpwusds \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b4 f4 00 00 00 10\s+vpdpwusds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 31\s+vpdpwusds \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b4 f4 00 00 00 10\s+vpdpwuud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 31\s+vpdpwuud \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b4 f4 00 00 00 10\s+vpdpwuud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 31\s+vpdpwuud \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b4 f4 00 00 00 10\s+vpdpwuuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 31\s+vpdpwuuds \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b4 f4 00 00 00 10\s+vpdpwuuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 31\s+vpdpwuuds \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b4 f4 00 00 00 10\s+vpdpwsud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 31\s+vpdpwsud \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b4 f4 00 00 00 10\s+vpdpwsud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 31\s+vpdpwsud \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b4 f4 00 00 00 10\s+vpdpwsuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 31\s+vpdpwsuds \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b4 f4 00 00 00 10\s+vpdpwsuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 31\s+vpdpwsuds \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b4 f4 00 00 00 10\s+vpdpwusd 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 31\s+vpdpwusd \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b4 f4 00 00 00 10\s+vpdpwusd 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 31\s+vpdpwusd \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b4 f4 00 00 00 10\s+vpdpwusds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 31\s+vpdpwusds \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b4 f4 00 00 00 10\s+vpdpwusds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 31\s+vpdpwusds \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b4 f4 00 00 00 10\s+vpdpwuud 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 31\s+vpdpwuud \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b4 f4 00 00 00 10\s+vpdpwuud 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 31\s+vpdpwuud \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud -0x800\(%edx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b4 f4 00 00 00 10\s+vpdpwuuds 0x10000000\(%esp,%esi,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 31\s+vpdpwuuds \(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds 0xfe0\(%ecx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds -0x1000\(%edx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b4 f4 00 00 00 10\s+vpdpwuuds 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 31\s+vpdpwuuds \(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds 0x7f0\(%ecx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds -0x800\(%edx\),%xmm5,%xmm6
|
||||
@@ -0,0 +1,126 @@
|
||||
# Check 32bit AVX-VNNI-INT16 instructions
|
||||
|
||||
.text
|
||||
_start:
|
||||
vpdpwsud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwsuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusd %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusd %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusd 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusd (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusd 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusd -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusd 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusd (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusd 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusd -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuud 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuud (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuud 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuud -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuud 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuud (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuud 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuud -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds 0x10000000(%esp, %esi, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds (%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds 4064(%ecx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuuds -4096(%edx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuuds 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds (%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds 2032(%ecx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuuds -2048(%edx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpdpwsud ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwsud xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwsuds ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwsuds xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusd ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwusd xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusds ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwusds xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuud ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwuud xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuuds ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwuuds xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [ecx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [edx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [ecx] #AVX-VNNI-INT16
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [ecx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [edx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
@@ -496,6 +496,8 @@ if [gas_32_check] then {
|
||||
run_dump_test "raoint"
|
||||
run_dump_test "raoint-intel"
|
||||
run_list_test "amx-complex-inval"
|
||||
run_dump_test "avx-vnni-int16"
|
||||
run_dump_test "avx-vnni-int16-intel"
|
||||
run_list_test "sg"
|
||||
run_dump_test "clzero"
|
||||
run_dump_test "invlpgb"
|
||||
|
||||
@@ -0,0 +1,129 @@
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX-VNNI-INT16 insns (Intel disassembly)
|
||||
#source: x86-64-avx-vnni-int16.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d2 b4 f5 00 00 00 10\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d2 31\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d2 b4 f5 00 00 00 10\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d2 31\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d3 b4 f5 00 00 00 10\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d3 31\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d3 b4 f5 00 00 00 10\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d3 31\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d2 b4 f5 00 00 00 10\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d2 31\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d2 b4 f5 00 00 00 10\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d2 31\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d3 b4 f5 00 00 00 10\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d3 31\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d3 b4 f5 00 00 00 10\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d3 31\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d2 b4 f5 00 00 00 10\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d2 31\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d2 b4 f5 00 00 00 10\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d2 31\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d3 b4 f5 00 00 00 10\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d3 31\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d3 b4 f5 00 00 00 10\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d3 31\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d2 b4 f5 00 00 00 10\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d2 31\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d2 b4 f5 00 00 00 10\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d2 31\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d3 b4 f5 00 00 00 10\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d3 31\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d3 b4 f5 00 00 00 10\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d3 31\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d2 b4 f5 00 00 00 10\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d2 31\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d2 b4 f5 00 00 00 10\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d2 31\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d3 b4 f5 00 00 00 10\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d3 31\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d3 b4 f5 00 00 00 10\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d3 31\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d2 b4 f5 00 00 00 10\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d2 31\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d2 b4 f5 00 00 00 10\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d2 31\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds ymm6,ymm5,ymm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds xmm6,xmm5,xmm4
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d3 b4 f5 00 00 00 10\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d3 31\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[rcx\+0xfe0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d3 b4 f5 00 00 00 10\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d3 31\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[r9\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[rcx\+0x7f0\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
|
||||
@@ -0,0 +1,129 @@
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX-VNNI-INT16 insns
|
||||
#source: x86-64-avx-vnni-int16.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d2 b4 f5 00 00 00 10\s+vpdpwsud 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d2 31\s+vpdpwsud \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d2 b4 f5 00 00 00 10\s+vpdpwsud 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d2 31\s+vpdpwsud \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d3 b4 f5 00 00 00 10\s+vpdpwsuds 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d3 31\s+vpdpwsuds \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d3 b4 f5 00 00 00 10\s+vpdpwsuds 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d3 31\s+vpdpwsuds \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d2 b4 f5 00 00 00 10\s+vpdpwusd 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d2 31\s+vpdpwusd \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d2 b4 f5 00 00 00 10\s+vpdpwusd 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d2 31\s+vpdpwusd \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d3 b4 f5 00 00 00 10\s+vpdpwusds 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d3 31\s+vpdpwusds \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d3 b4 f5 00 00 00 10\s+vpdpwusds 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d3 31\s+vpdpwusds \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d2 b4 f5 00 00 00 10\s+vpdpwuud 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d2 31\s+vpdpwuud \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d2 b4 f5 00 00 00 10\s+vpdpwuud 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d2 31\s+vpdpwuud \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d3 b4 f5 00 00 00 10\s+vpdpwuuds 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d3 31\s+vpdpwuuds \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d3 b4 f5 00 00 00 10\s+vpdpwuuds 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d3 31\s+vpdpwuuds \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 f4\s+vpdpwsud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 f4\s+vpdpwsud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d2 b4 f5 00 00 00 10\s+vpdpwsud 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d2 31\s+vpdpwsud \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b1 e0 0f 00 00\s+vpdpwsud 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d2 b2 00 f0 ff ff\s+vpdpwsud -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d2 b4 f5 00 00 00 10\s+vpdpwsud 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d2 31\s+vpdpwsud \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b1 f0 07 00 00\s+vpdpwsud 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d2 b2 00 f8 ff ff\s+vpdpwsud -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 f4\s+vpdpwsuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 f4\s+vpdpwsuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 56 d3 b4 f5 00 00 00 10\s+vpdpwsuds 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 56 d3 31\s+vpdpwsuds \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b1 e0 0f 00 00\s+vpdpwsuds 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 56 d3 b2 00 f0 ff ff\s+vpdpwsuds -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 52 d3 b4 f5 00 00 00 10\s+vpdpwsuds 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 52 d3 31\s+vpdpwsuds \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b1 f0 07 00 00\s+vpdpwsuds 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 52 d3 b2 00 f8 ff ff\s+vpdpwsuds -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 f4\s+vpdpwusd %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 f4\s+vpdpwusd %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d2 b4 f5 00 00 00 10\s+vpdpwusd 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d2 31\s+vpdpwusd \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b1 e0 0f 00 00\s+vpdpwusd 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d2 b2 00 f0 ff ff\s+vpdpwusd -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d2 b4 f5 00 00 00 10\s+vpdpwusd 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d2 31\s+vpdpwusd \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b1 f0 07 00 00\s+vpdpwusd 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d2 b2 00 f8 ff ff\s+vpdpwusd -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 f4\s+vpdpwusds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 f4\s+vpdpwusds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 55 d3 b4 f5 00 00 00 10\s+vpdpwusds 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 55 d3 31\s+vpdpwusds \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b1 e0 0f 00 00\s+vpdpwusds 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 55 d3 b2 00 f0 ff ff\s+vpdpwusds -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 51 d3 b4 f5 00 00 00 10\s+vpdpwusds 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 51 d3 31\s+vpdpwusds \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b1 f0 07 00 00\s+vpdpwusds 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 51 d3 b2 00 f8 ff ff\s+vpdpwusds -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 f4\s+vpdpwuud %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 f4\s+vpdpwuud %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d2 b4 f5 00 00 00 10\s+vpdpwuud 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d2 31\s+vpdpwuud \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b1 e0 0f 00 00\s+vpdpwuud 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d2 b2 00 f0 ff ff\s+vpdpwuud -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d2 b4 f5 00 00 00 10\s+vpdpwuud 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d2 31\s+vpdpwuud \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b1 f0 07 00 00\s+vpdpwuud 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d2 b2 00 f8 ff ff\s+vpdpwuud -0x800\(%rdx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 f4\s+vpdpwuuds %ymm4,%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 f4\s+vpdpwuuds %xmm4,%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 54 d3 b4 f5 00 00 00 10\s+vpdpwuuds 0x10000000\(%rbp,%r14,8\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 54 d3 31\s+vpdpwuuds \(%r9\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b1 e0 0f 00 00\s+vpdpwuuds 0xfe0\(%rcx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 54 d3 b2 00 f0 ff ff\s+vpdpwuuds -0x1000\(%rdx\),%ymm5,%ymm6
|
||||
\s*[a-f0-9]+:\s*c4 a2 50 d3 b4 f5 00 00 00 10\s+vpdpwuuds 0x10000000\(%rbp,%r14,8\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 50 d3 31\s+vpdpwuuds \(%r9\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b1 f0 07 00 00\s+vpdpwuuds 0x7f0\(%rcx\),%xmm5,%xmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 50 d3 b2 00 f8 ff ff\s+vpdpwuuds -0x800\(%rdx\),%xmm5,%xmm6
|
||||
@@ -0,0 +1,126 @@
|
||||
# Check 64bit AVX-VNNI-INT16 instructions
|
||||
|
||||
.text
|
||||
_start:
|
||||
vpdpwsud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsud 0x10000000(%rbp, %r14, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsud (%r9), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsud 4064(%rcx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsud -4096(%rdx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsud 0x10000000(%rbp, %r14, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsud (%r9), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsud 2032(%rcx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsud -2048(%rdx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwsuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds 0x10000000(%rbp, %r14, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds (%r9), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds 4064(%rcx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsuds -4096(%rdx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsuds 0x10000000(%rbp, %r14, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds (%r9), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwsuds 2032(%rcx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsuds -2048(%rdx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusd %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusd %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusd 0x10000000(%rbp, %r14, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusd (%r9), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusd 4064(%rcx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusd -4096(%rdx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusd 0x10000000(%rbp, %r14, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusd (%r9), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusd 2032(%rcx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusd -2048(%rdx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusds 0x10000000(%rbp, %r14, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusds (%r9), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwusds 4064(%rcx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusds -4096(%rdx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusds 0x10000000(%rbp, %r14, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusds (%r9), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwusds 2032(%rcx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusds -2048(%rdx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuud %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuud %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuud 0x10000000(%rbp, %r14, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuud (%r9), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuud 4064(%rcx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuud -4096(%rdx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuud 0x10000000(%rbp, %r14, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuud (%r9), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuud 2032(%rcx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuud -2048(%rdx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuuds %ymm4, %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds %xmm4, %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds 0x10000000(%rbp, %r14, 8), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds (%r9), %ymm5, %ymm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds 4064(%rcx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuuds -4096(%rdx), %ymm5, %ymm6 #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuuds 0x10000000(%rbp, %r14, 8), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds (%r9), %xmm5, %xmm6 #AVX-VNNI-INT16
|
||||
vpdpwuuds 2032(%rcx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuuds -2048(%rdx), %xmm5, %xmm6 #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpdpwsud ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwsud xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsud ymm6, ymm5, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsud xmm6, xmm5, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwsuds ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwsuds xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwsuds ymm6, ymm5, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwsuds xmm6, xmm5, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusd ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwusd xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusd ymm6, ymm5, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusd xmm6, xmm5, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwusds ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwusds xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwusds ymm6, ymm5, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwusds xmm6, xmm5, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuud ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwuud xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuud ymm6, ymm5, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuud xmm6, xmm5, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
vpdpwuuds ymm6, ymm5, ymm4 #AVX-VNNI-INT16
|
||||
vpdpwuuds xmm6, xmm5, xmm4 #AVX-VNNI-INT16
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [rcx+4064] #AVX-VNNI-INT16 Disp32(e00f0000)
|
||||
vpdpwuuds ymm6, ymm5, YMMWORD PTR [rdx-4096] #AVX-VNNI-INT16 Disp32(00f0ffff)
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [rbp+r14*8+0x10000000] #AVX-VNNI-INT16
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [r9] #AVX-VNNI-INT16
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [rcx+2032] #AVX-VNNI-INT16 Disp32(f0070000)
|
||||
vpdpwuuds xmm6, xmm5, XMMWORD PTR [rdx-2048] #AVX-VNNI-INT16 Disp32(00f8ffff)
|
||||
@@ -439,6 +439,8 @@ run_dump_test "x86-64-fred"
|
||||
run_dump_test "x86-64-lkgs"
|
||||
run_dump_test "x86-64-lkgs-intel"
|
||||
run_list_test "x86-64-lkgs-inval"
|
||||
run_dump_test "x86-64-avx-vnni-int16"
|
||||
run_dump_test "x86-64-avx-vnni-int16-intel"
|
||||
run_dump_test "x86-64-clzero"
|
||||
run_dump_test "x86-64-mwaitx-bdver4"
|
||||
run_list_test "x86-64-mwaitx-reg"
|
||||
|
||||
+28
-2
@@ -1060,6 +1060,8 @@ enum
|
||||
PREFIX_VEX_0F3872,
|
||||
PREFIX_VEX_0F38B0_W_0,
|
||||
PREFIX_VEX_0F38B1_W_0,
|
||||
PREFIX_VEX_0F38D2_W_0,
|
||||
PREFIX_VEX_0F38D3_W_0,
|
||||
PREFIX_VEX_0F38F5_L_0,
|
||||
PREFIX_VEX_0F38F6_L_0,
|
||||
PREFIX_VEX_0F38F7_L_0,
|
||||
@@ -1470,6 +1472,8 @@ enum
|
||||
VEX_W_0F38B4,
|
||||
VEX_W_0F38B5,
|
||||
VEX_W_0F38CF,
|
||||
VEX_W_0F38D2,
|
||||
VEX_W_0F38D3,
|
||||
VEX_W_0F3A00_L_1,
|
||||
VEX_W_0F3A01_L_1,
|
||||
VEX_W_0F3A02,
|
||||
@@ -3908,6 +3912,20 @@ static const struct dis386 prefix_table[][4] = {
|
||||
{ "vbcstnesh2ps", { XM, Mw }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F38D2_W_0 */
|
||||
{
|
||||
{ "vpdpwuud", { XM, Vex, EXx }, 0 },
|
||||
{ "vpdpwsud", { XM, Vex, EXx }, 0 },
|
||||
{ "vpdpwusd", { XM, Vex, EXx }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F38D3_W_0 */
|
||||
{
|
||||
{ "vpdpwuuds", { XM, Vex, EXx }, 0 },
|
||||
{ "vpdpwsuds", { XM, Vex, EXx }, 0 },
|
||||
{ "vpdpwusds", { XM, Vex, EXx }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_VEX_0F38F5_L_0 */
|
||||
{
|
||||
{ "bzhiS", { Gdq, Edq, VexGdq }, 0 },
|
||||
@@ -6368,8 +6386,8 @@ static const struct dis386 vex_table[][256] = {
|
||||
/* d0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (VEX_W_0F38D2) },
|
||||
{ VEX_W_TABLE (VEX_W_0F38D3) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
@@ -7598,6 +7616,14 @@ static const struct dis386 vex_w_table[][2] = {
|
||||
/* VEX_W_0F38CF */
|
||||
{ "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F38D2 */
|
||||
{ PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F38D3 */
|
||||
{ PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
|
||||
},
|
||||
{
|
||||
/* VEX_W_0F3A00_L_1 */
|
||||
{ Bad_Opcode },
|
||||
|
||||
@@ -162,6 +162,8 @@ static const dependency isa_dependencies[] =
|
||||
"AVX2" },
|
||||
{ "AVX_VNNI_INT8",
|
||||
"AVX2" },
|
||||
{ "AVX_VNNI_INT16",
|
||||
"AVX2" },
|
||||
{ "AVX_NE_CONVERT",
|
||||
"AVX2" },
|
||||
{ "FRED",
|
||||
@@ -359,6 +361,7 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (PREFETCHI),
|
||||
BITFIELD (AVX_IFMA),
|
||||
BITFIELD (AVX_VNNI_INT8),
|
||||
BITFIELD (AVX_VNNI_INT16),
|
||||
BITFIELD (CMPCCXADD),
|
||||
BITFIELD (WRMSRNS),
|
||||
BITFIELD (MSRLIST),
|
||||
|
||||
+555
-293
File diff suppressed because it is too large
Load Diff
+1342
-1336
File diff suppressed because it is too large
Load Diff
@@ -219,6 +219,8 @@ enum
|
||||
CpuAVX_IFMA,
|
||||
/* Intel AVX VNNI-INT8 Instructions support required. */
|
||||
CpuAVX_VNNI_INT8,
|
||||
/* Intel AVX VNNI-INT16 Instructions support required. */
|
||||
CpuAVX_VNNI_INT16,
|
||||
/* Intel CMPccXADD instructions support required. */
|
||||
CpuCMPCCXADD,
|
||||
/* Intel WRMSRNS Instructions support required */
|
||||
@@ -423,6 +425,7 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpuprefetchi:1;
|
||||
unsigned int cpuavx_ifma:1;
|
||||
unsigned int cpuavx_vnni_int8:1;
|
||||
unsigned int cpuavx_vnni_int16:1;
|
||||
unsigned int cpucmpccxadd:1;
|
||||
unsigned int cpuwrmsrns:1;
|
||||
unsigned int cpumsrlist:1;
|
||||
|
||||
@@ -2910,6 +2910,17 @@ vpdpbsuds, 0xf351, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperand
|
||||
|
||||
// AVX-VNNI-INT8 instructions end.
|
||||
|
||||
// AVX-VNNI-INT16 instructions.
|
||||
|
||||
vpdpwuud, 0xd2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpdpwuuds, 0xd3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpdpwusd, 0x66d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpdpwusds, 0x66d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpdpwsud, 0xf3d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
vpdpwsuds, 0xf3d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
|
||||
// AVX-VNNI-INT16 instructions end.
|
||||
|
||||
// AVX512_BITALG instructions
|
||||
|
||||
vpopcnt<bw>, 0x6654, AVX512_BITALG, Modrm|Masking|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
|
||||
|
||||
+7936
-3991
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user