Support Intel AVX-VNNI-INT16

gas/ChangeLog:

	* NEWS: Support Intel AVX-VNNI-INT16.
	* config/tc-i386.c: Add avx_vnni_int16.
	* doc/c-i386.texi: Document avx_vnni_int16.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.s: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38D2_W_0): New.
	(PREFIX_VEX_0F38D3_W_0): Ditto.
	(VEX_W_0F38D2_P_0): Ditto.
	(VEX_W_0F38D2_P_1): Ditto.
	(VEX_W_0F38D2_P_2): Ditto.
	(VEX_W_0F38D3_P_0): Ditto.
	(VEX_W_0F38D3_P_1): Ditto.
	(VEX_W_0F38D3_P_2): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38D2_W_0 and
	PREFIX_VEX_0F38D3_W_0.
	(vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3.
	(vex_w_table): Ditto.
	* i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16.
	(cpu_flag): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h: (CpuAVX_VNNI_INT16): New.
	* i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions.
	* i386-tbl.h: Regenerated.

opcodes/i386-dis.c

@@ -1060,6 +1060,8 @@ enum
   PREFIX_VEX_0F3872,
   PREFIX_VEX_0F38B0_W_0,
   PREFIX_VEX_0F38B1_W_0,
+  PREFIX_VEX_0F38D2_W_0,
+  PREFIX_VEX_0F38D3_W_0,
   PREFIX_VEX_0F38F5_L_0,
   PREFIX_VEX_0F38F6_L_0,
   PREFIX_VEX_0F38F7_L_0,
@@ -1470,6 +1472,8 @@ enum
   VEX_W_0F38B4,
   VEX_W_0F38B5,
   VEX_W_0F38CF,
+  VEX_W_0F38D2,
+  VEX_W_0F38D3,
   VEX_W_0F3A00_L_1,
   VEX_W_0F3A01_L_1,
   VEX_W_0F3A02,
@@ -3908,6 +3912,20 @@ static const struct dis386 prefix_table[][4] = {
     { "vbcstnesh2ps", { XM, Mw }, 0 },
   },
  
+  /* PREFIX_VEX_0F38D2_W_0 */
+  {
+    { "vpdpwuud",	{ XM, Vex, EXx }, 0 },
+    { "vpdpwsud",	{ XM, Vex, EXx }, 0 },
+    { "vpdpwusd",	{ XM, Vex, EXx }, 0 },
+  },
+
+  /* PREFIX_VEX_0F38D3_W_0 */
+  {
+    { "vpdpwuuds",	{ XM, Vex, EXx }, 0 },
+    { "vpdpwsuds",	{ XM, Vex, EXx }, 0 },
+    { "vpdpwusds",	{ XM, Vex, EXx }, 0 },
+  },
+
   /* PREFIX_VEX_0F38F5_L_0 */
   {
     { "bzhiS",		{ Gdq, Edq, VexGdq }, 0 },
@@ -6368,8 +6386,8 @@ static const struct dis386 vex_table[][256] = {
     /* d0 */
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F38D2) },
+    { VEX_W_TABLE (VEX_W_0F38D3) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -7598,6 +7616,14 @@ static const struct dis386 vex_w_table[][2] = {
     /* VEX_W_0F38CF */
     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
   },
+  {
+    /* VEX_W_0F38D2 */
+    { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
+  },
+  {
+    /* VEX_W_0F38D3 */
+    { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
+  },
   {
     /* VEX_W_0F3A00_L_1 */
     { Bad_Opcode },

opcodes/i386-gen.c

@@ -162,6 +162,8 @@ static const dependency isa_dependencies[] =
     "AVX2" },
   { "AVX_VNNI_INT8",
     "AVX2" },
+  { "AVX_VNNI_INT16",
+    "AVX2" },
   { "AVX_NE_CONVERT",
     "AVX2" },
   { "FRED",
@@ -359,6 +361,7 @@ static bitfield cpu_flags[] =
   BITFIELD (PREFETCHI),
   BITFIELD (AVX_IFMA),
   BITFIELD (AVX_VNNI_INT8),
+  BITFIELD (AVX_VNNI_INT16),
   BITFIELD (CMPCCXADD),
   BITFIELD (WRMSRNS),
   BITFIELD (MSRLIST),

opcodes/i386-opc.h

@@ -219,6 +219,8 @@ enum
   CpuAVX_IFMA,
   /* Intel AVX VNNI-INT8 Instructions support required.  */
   CpuAVX_VNNI_INT8,
+  /* Intel AVX VNNI-INT16 Instructions support required.  */
+  CpuAVX_VNNI_INT16,
   /* Intel CMPccXADD instructions support required.  */
   CpuCMPCCXADD,
   /* Intel WRMSRNS Instructions support required */
@@ -423,6 +425,7 @@ typedef union i386_cpu_flags
       unsigned int cpuprefetchi:1;
       unsigned int cpuavx_ifma:1;
       unsigned int cpuavx_vnni_int8:1;
+      unsigned int cpuavx_vnni_int16:1;
       unsigned int cpucmpccxadd:1;
       unsigned int cpuwrmsrns:1;
       unsigned int cpumsrlist:1;

opcodes/i386-opc.tbl

@@ -2910,6 +2910,17 @@ vpdpbsuds, 0xf351, AVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperand
 
 // AVX-VNNI-INT8 instructions end.
 
+// AVX-VNNI-INT16 instructions.
+
+vpdpwuud, 0xd2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpwuuds, 0xd3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpwusd, 0x66d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpwusds, 0x66d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpwsud, 0xf3d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vpdpwsuds, 0xf3d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+
+// AVX-VNNI-INT16 instructions end.
+
 // AVX512_BITALG instructions
 
 vpopcnt<bw>, 0x6654, AVX512_BITALG, Modrm|Masking|Space0F38|<bw:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }