AArch64: Add MTE register set support for GDB and gdbserver
AArch64 MTE support in the Linux kernel exposes a new register through ptrace. This patch adds the required code to support it. include/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * elf/common.h (NT_ARM_TAGGED_ADDR_CTRL): Define. gdb/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * aarch64-linux-nat.c (fetch_mteregs_from_thread): New function. (store_mteregs_to_thread): New function. (aarch64_linux_nat_target::fetch_registers): Update to call fetch_mteregs_from_thread. (aarch64_linux_nat_target::store_registers): Update to call store_mteregs_to_thread. * aarch64-tdep.c (aarch64_mte_register_names): New struct. (aarch64_cannot_store_register): Handle MTE registers. (aarch64_gdbarch_init): Initialize and setup MTE registers. * aarch64-tdep.h (gdbarch_tdep) <mte_reg_base>: New field. <has_mte>: New method. * arch/aarch64-linux.h (AARCH64_LINUX_SIZEOF_MTE): Define. gdbserver/ChangeLog: 2021-03-24 Luis Machado <luis.machado@linaro.org> * linux-aarch64-low.cc (aarch64_fill_mteregset): New function. (aarch64_store_mteregset): New function. (aarch64_regsets): Add MTE register set entry. (aarch64_sve_regsets): Add MTE register set entry.
This commit is contained in:
Luis Machado
parent
c1bd443b4d
commit
5e984dbf35
@ -1,3 +1,18 @@
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2021-03-24 Luis Machado <luis.machado@linaro.org>
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* aarch64-linux-nat.c (fetch_mteregs_from_thread): New function.
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(store_mteregs_to_thread): New function.
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(aarch64_linux_nat_target::fetch_registers): Update to call
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fetch_mteregs_from_thread.
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(aarch64_linux_nat_target::store_registers): Update to call
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store_mteregs_to_thread.
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* aarch64-tdep.c (aarch64_mte_register_names): New struct.
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(aarch64_cannot_store_register): Handle MTE registers.
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(aarch64_gdbarch_init): Initialize and setup MTE registers.
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* aarch64-tdep.h (gdbarch_tdep) <mte_reg_base>: New field.
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<has_mte>: New method.
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* arch/aarch64-linux.h (AARCH64_LINUX_SIZEOF_MTE): Define.
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2021-03-24 Luis Machado <luis.machado@linaro.org>
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* aarch64-linux-nat.c
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@ -461,6 +461,58 @@ fetch_pauth_masks_from_thread (struct regcache *regcache)
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&pauth_regset[1]);
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}
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/* Fill GDB's register array with the MTE register values from
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the current thread. */
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static void
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fetch_mteregs_from_thread (struct regcache *regcache)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
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int regno = tdep->mte_reg_base;
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gdb_assert (regno != -1);
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uint64_t tag_ctl = 0;
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struct iovec iovec;
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iovec.iov_base = &tag_ctl;
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iovec.iov_len = sizeof (tag_ctl);
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int tid = get_ptrace_pid (regcache->ptid ());
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if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
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perror_with_name (_("unable to fetch MTE registers."));
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regcache->raw_supply (regno, &tag_ctl);
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}
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/* Store to the current thread the valid MTE register set in the GDB's
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register array. */
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static void
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store_mteregs_to_thread (struct regcache *regcache)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
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int regno = tdep->mte_reg_base;
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gdb_assert (regno != -1);
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uint64_t tag_ctl = 0;
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if (REG_VALID != regcache->get_register_status (regno))
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return;
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regcache->raw_collect (regno, (char *) &tag_ctl);
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struct iovec iovec;
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iovec.iov_base = &tag_ctl;
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iovec.iov_len = sizeof (tag_ctl);
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int tid = get_ptrace_pid (regcache->ptid ());
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if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
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perror_with_name (_("unable to store MTE registers."));
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}
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/* Implement the "fetch_registers" target_ops method. */
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void
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@ -479,6 +531,9 @@ aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
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if (tdep->has_pauth ())
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fetch_pauth_masks_from_thread (regcache);
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if (tdep->has_mte ())
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fetch_mteregs_from_thread (regcache);
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}
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else if (regno < AARCH64_V0_REGNUM)
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fetch_gregs_from_thread (regcache);
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@ -493,6 +548,11 @@ aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
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|| regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
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fetch_pauth_masks_from_thread (regcache);
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}
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/* Fetch individual MTE registers. */
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if (tdep->has_mte ()
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&& (regno == tdep->mte_reg_base))
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fetch_mteregs_from_thread (regcache);
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}
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/* Implement the "store_registers" target_ops method. */
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@ -510,6 +570,9 @@ aarch64_linux_nat_target::store_registers (struct regcache *regcache,
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store_sveregs_to_thread (regcache);
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else
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store_fpregs_to_thread (regcache);
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if (tdep->has_mte ())
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store_mteregs_to_thread (regcache);
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}
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else if (regno < AARCH64_V0_REGNUM)
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store_gregs_to_thread (regcache);
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@ -517,6 +580,11 @@ aarch64_linux_nat_target::store_registers (struct regcache *regcache,
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store_sveregs_to_thread (regcache);
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else
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store_fpregs_to_thread (regcache);
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/* Store MTE registers. */
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if (tdep->has_mte ()
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&& (regno == tdep->mte_reg_base))
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store_mteregs_to_thread (regcache);
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}
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/* Fill register REGNO (if it is a general-purpose register) in
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@ -172,6 +172,12 @@ static const char *const aarch64_pauth_register_names[] =
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"pauth_cmask"
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};
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static const char *const aarch64_mte_register_names[] =
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{
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/* Tag Control Register. */
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"tag_ctl"
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};
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/* AArch64 prologue cache structure. */
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struct aarch64_prologue_cache
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{
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@ -3346,6 +3352,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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bool valid_p = true;
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int i, num_regs = 0, num_pseudo_regs = 0;
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int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
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int first_mte_regnum = -1;
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/* Use the vector length passed via the target info. Here -1 is used for no
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SVE, and 0 is unset. If unset then use the vector length from the existing
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@ -3383,6 +3390,8 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
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feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
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feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
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const struct tdesc_feature *feature_mte
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= tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.mte");
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if (feature_core == nullptr)
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return nullptr;
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@ -3453,6 +3462,20 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
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}
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/* Add the MTE registers. */
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if (feature_mte != NULL)
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{
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first_mte_regnum = num_regs;
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/* Validate the descriptor provides the mandatory MTE registers and
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allocate their numbers. */
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for (i = 0; i < ARRAY_SIZE (aarch64_mte_register_names); i++)
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valid_p &= tdesc_numbered_register (feature_mte, tdesc_data.get (),
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first_mte_regnum + i,
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aarch64_mte_register_names[i]);
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num_regs += i;
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}
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if (!valid_p)
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return nullptr;
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@ -3470,6 +3493,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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tdep->pauth_reg_base = first_pauth_regnum;
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tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
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: pauth_ra_state_offset + num_regs;
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tdep->mte_reg_base = first_mte_regnum;
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set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
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set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
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@ -100,6 +100,15 @@ struct gdbarch_tdep
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{
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return pauth_reg_base != -1;
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}
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/* First MTE register. This is -1 if no MTE registers are available. */
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int mte_reg_base;
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/* Returns true if the target supports MTE. */
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bool has_mte () const
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{
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return mte_reg_base != -1;
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}
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};
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const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p,
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@ -25,4 +25,7 @@
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#define HWCAP2_MTE (1 << 18)
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#endif
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/* The MTE regset consists of a single 64-bit register. */
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#define AARCH64_LINUX_SIZEOF_MTE 8
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#endif /* ARCH_AARCH64_LINUX_H */
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@ -1,3 +1,10 @@
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2021-03-24 Luis Machado <luis.machado@linaro.org>
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* linux-aarch64-low.cc (aarch64_fill_mteregset): New function.
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(aarch64_store_mteregset): New function.
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(aarch64_regsets): Add MTE register set entry.
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(aarch64_sve_regsets): Add MTE register set entry.
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2021-03-24 Luis Machado <luis.machado@linaro.org>
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* linux-aarch64-ipa.cc (get_ipa_tdesc): Update call to
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@ -261,6 +261,29 @@ aarch64_store_pauthregset (struct regcache *regcache, const void *buf)
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&pauth_regset[1]);
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}
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/* Fill BUF with the MTE registers from the regcache. */
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static void
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aarch64_fill_mteregset (struct regcache *regcache, void *buf)
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{
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uint64_t *mte_regset = (uint64_t *) buf;
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int mte_base = find_regno (regcache->tdesc, "tag_ctl");
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collect_register (regcache, mte_base, mte_regset);
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}
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/* Store the MTE registers to regcache. */
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static void
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aarch64_store_mteregset (struct regcache *regcache, const void *buf)
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{
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uint64_t *mte_regset = (uint64_t *) buf;
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int mte_base = find_regno (regcache->tdesc, "tag_ctl");
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/* Tag Control register */
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supply_register (regcache, mte_base, mte_regset);
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}
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bool
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aarch64_target::low_supports_breakpoints ()
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{
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@ -706,6 +729,9 @@ static struct regset_info aarch64_regsets[] =
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
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AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
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NULL, aarch64_store_pauthregset },
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
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AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
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aarch64_store_mteregset },
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NULL_REGSET
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};
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@ -735,6 +761,9 @@ static struct regset_info aarch64_sve_regsets[] =
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
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AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
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NULL, aarch64_store_pauthregset },
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
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AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
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aarch64_store_mteregset },
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NULL_REGSET
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};
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@ -672,6 +672,9 @@
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/* note name must be "LINUX". */
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#define NT_ARM_PAC_MASK 0x406 /* AArch pointer authentication code masks */
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/* note name must be "LINUX". */
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#define NT_ARM_TAGGED_ADDR_CTRL 0x409 /* AArch64 tagged address control
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(prctl()) */
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/* note name must be "LINUX". */
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#define NT_ARC_V2 0x600 /* ARC HS accumulator/extra registers. */
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/* note name must be "LINUX". */
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#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
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