sim/bpf: desCGENization of the BPF simulator
The BPF port in binutils has been rewritten (commit
d218e7fedc) in order to not be longer
based on CGEN. Please see that commit log for more information.
This patch updates the BPF simulator accordingly. The new
implementation is much simpler and it is based on the new BPF opcodes.
Tested with target bpf-unknown-none with both 64-bit little-endian
host and 32-bit little-endian host.
Note that I have not tested in a big-endian host yet. I will do so
once this lands upstream so I can use the GCC compiler farm.
This commit is contained in:
Jose E. Marchesi
+129
-220
@@ -146,76 +146,71 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
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@SIM_ENABLE_ARCH_bfin_TRUE@am__append_10 = bfin/run
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@SIM_ENABLE_ARCH_bpf_TRUE@am__append_11 = bpf/libsim.a
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@SIM_ENABLE_ARCH_bpf_TRUE@am__append_12 = bpf/run
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@SIM_ENABLE_ARCH_bpf_TRUE@am__append_13 = \
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@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-le.h \
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@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-be.h
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@SIM_ENABLE_ARCH_bpf_TRUE@am__append_14 = $(bpf_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/libsim.a
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/run
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = cr16/simops.h
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = cr16/gencode
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_19 = $(cr16_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/libsim.a
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/run
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = cris/rvdummy
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = \
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_13 = cr16/libsim.a
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/run
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/simops.h
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/gencode
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = $(cr16_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_18 = cris/libsim.a
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/run
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/rvdummy
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = \
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@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \
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@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = $(cris_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/libsim.a
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/run
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = d10v/simops.h
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = $(d10v_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_30 = erc32/libsim.a
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = erc32/run erc32/sis
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = sim-%D-install-exec-local
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 = sim-erc32-uninstall-local
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@SIM_ENABLE_ARCH_examples_TRUE@am__append_34 = example-synacor/libsim.a
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@SIM_ENABLE_ARCH_examples_TRUE@am__append_35 = example-synacor/run
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_36 = frv/libsim.a
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/run
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/eng.h
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = $(frv_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_ft32_TRUE@am__append_40 = ft32/libsim.a
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@SIM_ENABLE_ARCH_ft32_TRUE@am__append_41 = ft32/run
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@SIM_ENABLE_ARCH_h8300_TRUE@am__append_42 = h8300/libsim.a
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@SIM_ENABLE_ARCH_h8300_TRUE@am__append_43 = h8300/run
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_44 = iq2000/libsim.a
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 = iq2000/run
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/eng.h
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = $(iq2000_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_48 = lm32/libsim.a
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_49 = lm32/run
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_50 = lm32/eng.h
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = $(lm32_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_52 = m32c/libsim.a
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_53 = m32c/run
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_54 = m32c/opc2c
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 = \
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@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = $(cris_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_23 = d10v/libsim.a
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_24 = d10v/run
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/simops.h
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/gencode
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = $(d10v_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_28 = erc32/libsim.a
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_29 = erc32/run erc32/sis
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_30 = sim-%D-install-exec-local
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@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = sim-erc32-uninstall-local
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@SIM_ENABLE_ARCH_examples_TRUE@am__append_32 = example-synacor/libsim.a
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@SIM_ENABLE_ARCH_examples_TRUE@am__append_33 = example-synacor/run
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_34 = frv/libsim.a
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_35 = frv/run
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_36 = frv/eng.h
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@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = $(frv_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_ft32_TRUE@am__append_38 = ft32/libsim.a
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@SIM_ENABLE_ARCH_ft32_TRUE@am__append_39 = ft32/run
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@SIM_ENABLE_ARCH_h8300_TRUE@am__append_40 = h8300/libsim.a
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@SIM_ENABLE_ARCH_h8300_TRUE@am__append_41 = h8300/run
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_42 = iq2000/libsim.a
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_43 = iq2000/run
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_44 = iq2000/eng.h
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@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 = $(iq2000_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_46 = lm32/libsim.a
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_47 = lm32/run
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_48 = lm32/eng.h
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@SIM_ENABLE_ARCH_lm32_TRUE@am__append_49 = $(lm32_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_50 = m32c/libsim.a
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_51 = m32c/run
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_52 = m32c/opc2c
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@SIM_ENABLE_ARCH_m32c_TRUE@am__append_53 = \
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@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
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@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
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@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_56 = m32r/libsim.a
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_57 = m32r/run
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_58 = \
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_54 = m32r/libsim.a
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_55 = m32r/run
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_56 = \
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@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
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@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
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@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 = $(m32r_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_60 = m68hc11/libsim.a
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_61 = m68hc11/run
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_62 = m68hc11/gencode
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 = $(m68hc11_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_mcore_TRUE@am__append_64 = mcore/libsim.a
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@SIM_ENABLE_ARCH_mcore_TRUE@am__append_65 = mcore/run
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@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_66 = microblaze/libsim.a
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@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_67 = microblaze/run
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_68 = \
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@SIM_ENABLE_ARCH_m32r_TRUE@am__append_57 = $(m32r_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_58 = m68hc11/libsim.a
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_59 = m68hc11/run
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_60 = m68hc11/gencode
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@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_61 = $(m68hc11_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_mcore_TRUE@am__append_62 = mcore/libsim.a
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@SIM_ENABLE_ARCH_mcore_TRUE@am__append_63 = mcore/run
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@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_64 = microblaze/libsim.a
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@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_65 = microblaze/run
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_66 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.o \
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@@ -224,7 +219,7 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_69 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_67 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics.o \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o \
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@@ -238,35 +233,35 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_70 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_68 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_OBJ) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_71 = mips/libsim.a
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_72 = mips/run
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_73 = mips/itable.h \
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_69 = mips/libsim.a
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_70 = mips/run
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_71 = mips/itable.h \
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@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_74 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_72 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_75 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_73 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_76 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_74 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
|
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = $(mips_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/multi-include.h mips/multi-run.c
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@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_79 = mn10300/libsim.a
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_80 = mn10300/run
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_81 = \
|
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 = $(mips_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/multi-include.h mips/multi-run.c
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_77 = mn10300/libsim.a
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_78 = mn10300/run
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_79 = \
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
|
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@@ -275,36 +270,36 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
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@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
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@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
|
||||
|
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@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 = $(mn10300_BUILD_OUTPUTS)
|
||||
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_83 = moxie/libsim.a
|
||||
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_84 = moxie/run
|
||||
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_85 = msp430/libsim.a
|
||||
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_86 = msp430/run
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_87 = or1k/libsim.a
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_88 = or1k/run
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_89 = or1k/eng.h
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 = $(or1k_BUILD_OUTPUTS)
|
||||
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_91 = common/libcommon.a
|
||||
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_92 = ppc/run
|
||||
@SIM_ENABLE_ARCH_pru_TRUE@am__append_93 = pru/libsim.a
|
||||
@SIM_ENABLE_ARCH_pru_TRUE@am__append_94 = pru/run
|
||||
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_95 = riscv/libsim.a
|
||||
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_96 = riscv/run
|
||||
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_97 = rl78/libsim.a
|
||||
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_98 = rl78/run
|
||||
@SIM_ENABLE_ARCH_rx_TRUE@am__append_99 = rx/libsim.a
|
||||
@SIM_ENABLE_ARCH_rx_TRUE@am__append_100 = rx/run
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_101 = sh/libsim.a
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 = sh/run
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 = \
|
||||
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_80 = $(mn10300_BUILD_OUTPUTS)
|
||||
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_81 = moxie/libsim.a
|
||||
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_82 = moxie/run
|
||||
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_83 = msp430/libsim.a
|
||||
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_84 = msp430/run
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_85 = or1k/libsim.a
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_86 = or1k/run
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_87 = or1k/eng.h
|
||||
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_88 = $(or1k_BUILD_OUTPUTS)
|
||||
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_89 = common/libcommon.a
|
||||
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_90 = ppc/run
|
||||
@SIM_ENABLE_ARCH_pru_TRUE@am__append_91 = pru/libsim.a
|
||||
@SIM_ENABLE_ARCH_pru_TRUE@am__append_92 = pru/run
|
||||
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_93 = riscv/libsim.a
|
||||
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_94 = riscv/run
|
||||
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_95 = rl78/libsim.a
|
||||
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_96 = rl78/run
|
||||
@SIM_ENABLE_ARCH_rx_TRUE@am__append_97 = rx/libsim.a
|
||||
@SIM_ENABLE_ARCH_rx_TRUE@am__append_98 = rx/run
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_99 = sh/libsim.a
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_100 = sh/run
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_101 = \
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
|
||||
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = sh/gencode
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = $(sh_BUILD_OUTPUTS)
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_106 = v850/libsim.a
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 = v850/run
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 = \
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 = sh/gencode
|
||||
@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 = $(sh_BUILD_OUTPUTS)
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_104 = v850/libsim.a
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_105 = v850/run
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_106 = \
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
|
||||
@@ -313,7 +308,7 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
|
||||
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 = $(v850_BUILD_OUTPUTS)
|
||||
@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 = $(v850_BUILD_OUTPUTS)
|
||||
subdir = .
|
||||
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
|
||||
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
|
||||
@@ -437,18 +432,12 @@ bfin_libsim_a_AR = $(AR) $(ARFLAGS)
|
||||
bfin_libsim_a_OBJECTS = $(am_bfin_libsim_a_OBJECTS) \
|
||||
$(nodist_bfin_libsim_a_OBJECTS)
|
||||
bpf_libsim_a_AR = $(AR) $(ARFLAGS)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = $(patsubst \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = bpf/bpf-sim.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-run.o bpf/cgen-scache.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-trace.o bpf/cgen-utils.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/arch.o bpf/cpu.o bpf/decode-le.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o bpf/sem-le.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o bpf/mloop-le.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o bpf/bpf.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o bpf/sim-if.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@am_bpf_libsim_a_OBJECTS = $(am__objects_1)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_OBJECTS = \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.$(OBJEXT)
|
||||
@@ -727,8 +716,8 @@ am__DEPENDENCIES_1 =
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_68) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_69) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_66) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_67) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \
|
||||
@@ -1780,36 +1769,35 @@ pkginclude_HEADERS = $(am__append_1)
|
||||
EXTRA_LIBRARIES = igen/libigen.a
|
||||
noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \
|
||||
$(am__append_7) $(am__append_9) $(am__append_11) \
|
||||
$(am__append_15) $(am__append_20) $(am__append_25) \
|
||||
$(am__append_30) $(am__append_34) $(am__append_36) \
|
||||
$(am__append_40) $(am__append_42) $(am__append_44) \
|
||||
$(am__append_48) $(am__append_52) $(am__append_56) \
|
||||
$(am__append_60) $(am__append_64) $(am__append_66) \
|
||||
$(am__append_71) $(am__append_79) $(am__append_83) \
|
||||
$(am__append_85) $(am__append_87) $(am__append_93) \
|
||||
$(am__append_95) $(am__append_97) $(am__append_99) \
|
||||
$(am__append_101) $(am__append_106)
|
||||
BUILT_SOURCES = $(am__append_13) $(am__append_17) $(am__append_23) \
|
||||
$(am__append_27) $(am__append_38) $(am__append_46) \
|
||||
$(am__append_50) $(am__append_58) $(am__append_73) \
|
||||
$(am__append_81) $(am__append_89) $(am__append_103) \
|
||||
$(am__append_108)
|
||||
$(am__append_13) $(am__append_18) $(am__append_23) \
|
||||
$(am__append_28) $(am__append_32) $(am__append_34) \
|
||||
$(am__append_38) $(am__append_40) $(am__append_42) \
|
||||
$(am__append_46) $(am__append_50) $(am__append_54) \
|
||||
$(am__append_58) $(am__append_62) $(am__append_64) \
|
||||
$(am__append_69) $(am__append_77) $(am__append_81) \
|
||||
$(am__append_83) $(am__append_85) $(am__append_91) \
|
||||
$(am__append_93) $(am__append_95) $(am__append_97) \
|
||||
$(am__append_99) $(am__append_104)
|
||||
BUILT_SOURCES = $(am__append_15) $(am__append_21) $(am__append_25) \
|
||||
$(am__append_36) $(am__append_44) $(am__append_48) \
|
||||
$(am__append_56) $(am__append_71) $(am__append_79) \
|
||||
$(am__append_87) $(am__append_101) $(am__append_106)
|
||||
CLEANFILES = common/version.c common/version.c-stamp \
|
||||
testsuite/common/bits-gen testsuite/common/bits32m0.c \
|
||||
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
|
||||
testsuite/common/bits64m63.c
|
||||
DISTCLEANFILES = $(am__append_78)
|
||||
DISTCLEANFILES = $(am__append_76)
|
||||
MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \
|
||||
$(SIM_ENABLED_ARCHES:%=%/hw-config.h) \
|
||||
$(SIM_ENABLED_ARCHES:%=%/stamp-hw) \
|
||||
$(SIM_ENABLED_ARCHES:%=%/modules.c) \
|
||||
$(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \
|
||||
site-sim-config.exp testrun.log testrun.sum $(am__append_14) \
|
||||
$(am__append_19) $(am__append_24) $(am__append_29) \
|
||||
$(am__append_39) $(am__append_47) $(am__append_51) \
|
||||
$(am__append_55) $(am__append_59) $(am__append_63) \
|
||||
$(am__append_77) $(am__append_82) $(am__append_90) \
|
||||
$(am__append_105) $(am__append_109)
|
||||
site-sim-config.exp testrun.log testrun.sum $(am__append_17) \
|
||||
$(am__append_22) $(am__append_27) $(am__append_37) \
|
||||
$(am__append_45) $(am__append_49) $(am__append_53) \
|
||||
$(am__append_57) $(am__append_61) $(am__append_75) \
|
||||
$(am__append_80) $(am__append_88) $(am__append_103) \
|
||||
$(am__append_107)
|
||||
AM_CFLAGS = \
|
||||
$(WERROR_CFLAGS) \
|
||||
$(WARN_CFLAGS) \
|
||||
@@ -1824,10 +1812,10 @@ AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \
|
||||
$(SIM_INLINE) -I$(srcdir)/common
|
||||
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD)
|
||||
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
|
||||
SIM_ALL_RECURSIVE_DEPS = $(am__append_91)
|
||||
SIM_ALL_RECURSIVE_DEPS = $(am__append_89)
|
||||
SIM_INSTALL_DATA_LOCAL_DEPS =
|
||||
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_32)
|
||||
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_33)
|
||||
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_30)
|
||||
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_31)
|
||||
SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
|
||||
SIM_COMPILE = \
|
||||
$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \
|
||||
@@ -2120,13 +2108,6 @@ testsuite_common_CPPFLAGS = \
|
||||
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wp \
|
||||
@SIM_ENABLE_ARCH_bfin_TRUE@ eth_phy
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf = -DWITH_TARGET_WORD_BITSIZE=64
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_mloop_le.o = -DWANT_ISA_EBPFLE
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_mloop_be.o = -DWANT_ISA_EBPFBE
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_decode_le.o = -DWANT_ISA_EBPFLE
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_decode_be.o = -DWANT_ISA_EBPFBE
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_sem_le.o = -DWANT_ISA_EBPFLE
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_sem_be.o = -DWANT_ISA_EBPFBE
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_SOURCES = \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.c
|
||||
|
||||
@@ -2134,27 +2115,10 @@ testsuite_common_CPPFLAGS = \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(common_libcommon_a_SOURCES)
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-sim.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-run.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-scache.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-trace.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-utils.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/arch.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cpu.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-le.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-le.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-if.o \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES =
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
|
||||
@@ -2162,12 +2126,6 @@ testsuite_common_CPPFLAGS = \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/libsim.a \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(SIM_COMMON_LIBS)
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_BUILD_OUTPUTS = \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.c \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-le \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.c \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-be
|
||||
|
||||
@SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_SOURCES = \
|
||||
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/modules.c
|
||||
|
||||
@@ -2658,8 +2616,8 @@ testsuite_common_CPPFLAGS = \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
|
||||
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_68) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_69) $(am__append_70)
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_66) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_67) $(am__append_68)
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c
|
||||
|
||||
@@ -2731,8 +2689,8 @@ testsuite_common_CPPFLAGS = \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_76)
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73) \
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74)
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
|
||||
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
|
||||
@@ -5015,55 +4973,6 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: common/%.c ; $(SIM_COMPILE)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@-@am__include@ bpf/$(DEPDIR)/*.Po
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/modules.c: | $(bpf_BUILD_OUTPUTS)
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/mloop-le.c bpf/eng-le.h: bpf/stamp-mloop-le ; @true
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/stamp-mloop-le: $(srccom)/genmloop.sh bpf/mloop.in
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ -mono -scache -prefix bpfbf_ebpfle -cpu bpfbf \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ -infile $(srcdir)/bpf/mloop.in \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ -outfile-prefix bpf/ -outfile-suffix -le
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/eng-le.hin bpf/eng-le.h
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/mloop-le.cin bpf/mloop-le.c
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)touch $@
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/mloop-be.c bpf/eng-be.h: bpf/stamp-mloop-be ; @true
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/stamp-mloop-be: $(srccom)/genmloop.sh bpf/mloop.in
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ -mono -scache -prefix bpfbf_ebpfbe -cpu bpfbf \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ -infile $(srcdir)/bpf/mloop.in \
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ -outfile-prefix bpf/ -outfile-suffix -be
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/eng-be.hin bpf/eng-be.h
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/mloop-be.cin bpf/mloop-be.c
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)touch $@
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen: bpf/cgen-arch bpf/cgen-cpu bpf/cgen-defs-le bpf/cgen-defs-be bpf/cgen-decode-le bpf/cgen-decode-be
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-arch:
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)mach=bpf cpu=bpfbf FLAGS="with-scache"; $(CGEN_GEN_ARCH)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/arch.h bpf/arch.c bpf/cpuall.h: @CGEN_MAINT@ bpf/cgen-arch
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-cpu:
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle,ebpfbe cpu=bpfbf mach=bpf FLAGS="with-multiple-isa with-scache"; $(CGEN_GEN_CPU)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)rm -f $(srcdir)/bpf/model.c
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cpu.h bpf/cpu.c bpf/model.c: @CGEN_MAINT@ bpf/cgen-cpu
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-le:
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le"; $(CGEN_GEN_DEFS)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-le.h: @CGEN_MAINT@ bpf/cgen-defs-le
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-be:
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be"; $(CGEN_GEN_DEFS)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-be.h: @CGEN_MAINT@ bpf/cgen-defs-be
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-le:
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-le.c bpf/decode-le.c bpf/decode-le.h: @CGEN_MAINT@ bpf/cgen-decode-vle
|
||||
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-be:
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
|
||||
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-be.c bpf/decode-be.c bpf/decode-be.h: @CGEN_MAINT@ bpf/cgen-decode-be
|
||||
@SIM_ENABLE_ARCH_cr16_TRUE@$(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD): cr16/hw-config.h
|
||||
|
||||
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.o: cr16/modules.c
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
/* Simulator support for bpf.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "bfd.h"
|
||||
|
||||
const SIM_MACH * const bpf_sim_machs[] =
|
||||
{
|
||||
#ifdef HAVE_CPU_BPFBF
|
||||
& bpf_mach,
|
||||
#endif
|
||||
0
|
||||
};
|
||||
|
||||
@@ -1,50 +0,0 @@
|
||||
/* Simulator header for bpf.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef BPF_ARCH_H
|
||||
#define BPF_ARCH_H
|
||||
|
||||
#define TARGET_BIG_ENDIAN 1
|
||||
|
||||
#define WI DI
|
||||
#define UWI UDI
|
||||
#define AI UDI
|
||||
|
||||
#define IAI UDI
|
||||
|
||||
/* Enum declaration for model types. */
|
||||
typedef enum model_type {
|
||||
MODEL_BPF_DEF, MODEL_MAX
|
||||
} MODEL_TYPE;
|
||||
|
||||
#define MAX_MODELS ((int) MODEL_MAX)
|
||||
|
||||
/* Enum declaration for unit types. */
|
||||
typedef enum unit_type {
|
||||
UNIT_NONE, UNIT_BPF_DEF_U_EXEC, UNIT_MAX
|
||||
} UNIT_TYPE;
|
||||
|
||||
#define MAX_UNITS (1)
|
||||
|
||||
#endif /* BPF_ARCH_H */
|
||||
@@ -1,181 +0,0 @@
|
||||
/* Emulation of eBPF helpers.
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* BPF programs rely on the existence of several helper functions,
|
||||
which are provided by the kernel. This simulator provides an
|
||||
implementation of the helpers, which can be customized by the
|
||||
user. */
|
||||
|
||||
/* This must come before any other includes. */
|
||||
#include "defs.h"
|
||||
|
||||
#define WANT_CPU_BPFBF
|
||||
#define WANT_CPU bpfbf
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "cgen-mem.h"
|
||||
#include "cgen-ops.h"
|
||||
#include "cpu.h"
|
||||
|
||||
#include "bpf-helpers.h"
|
||||
|
||||
/* bpf_trace_printk is a printk-like facility for debugging.
|
||||
|
||||
In the kernel, it appends a line to the Linux's tracing debugging
|
||||
interface.
|
||||
|
||||
In this simulator, it uses the simulator's tracing interface
|
||||
instead.
|
||||
|
||||
The format tags recognized by this helper are:
|
||||
%d, %i, %u, %x, %ld, %li, %lu, %lx, %lld, %lli, %llu, %llx,
|
||||
%p, %s
|
||||
|
||||
A maximum of three tags are supported.
|
||||
|
||||
This helper returns the number of bytes written, or a negative
|
||||
value in case of failure. */
|
||||
|
||||
int
|
||||
bpf_trace_printk (SIM_CPU *current_cpu)
|
||||
{
|
||||
va_list ap;
|
||||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||||
|
||||
DI fmt_address;
|
||||
uint32_t size, tags_processed;
|
||||
size_t i, bytes_written = 0;
|
||||
|
||||
/* The first argument is the format string, which is passed as a
|
||||
pointer in %r1. */
|
||||
fmt_address = GET_H_GPR (1);
|
||||
|
||||
/* The second argument is the length of the format string, as an
|
||||
unsigned 32-bit number in %r2. */
|
||||
size = GET_H_GPR (2);
|
||||
|
||||
/* Read the format string from the memory pointed by %r2, printing
|
||||
out the stuff as we go. There is a maximum of three format tags
|
||||
supported, which are read from %r3, %r4 and %r5 respectively. */
|
||||
for (i = 0, tags_processed = 0; i < size;)
|
||||
{
|
||||
UDI value;
|
||||
QI c = GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
|
||||
fmt_address + i);
|
||||
|
||||
switch (c)
|
||||
{
|
||||
case '%':
|
||||
/* Check we are not exceeding the limit of three format
|
||||
tags. */
|
||||
if (tags_processed > 2)
|
||||
return -1; /* XXX look for kernel error code. */
|
||||
|
||||
/* Depending on the kind of tag, extract the value from the
|
||||
proper argument. */
|
||||
if (i++ >= size)
|
||||
return -1; /* XXX look for kernel error code. */
|
||||
|
||||
value = GET_H_GPR (3 + tags_processed);
|
||||
|
||||
switch ((GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
|
||||
fmt_address + i)))
|
||||
{
|
||||
case 'd':
|
||||
trace_printf (sd, current_cpu, "%d", (int) value);
|
||||
break;
|
||||
case 'i':
|
||||
trace_printf (sd, current_cpu, "%i", (int) value);
|
||||
break;
|
||||
case 'u':
|
||||
trace_printf (sd, current_cpu, "%u", (unsigned int) value);
|
||||
break;
|
||||
case 'x':
|
||||
trace_printf (sd, current_cpu, "%x", (unsigned int) value);
|
||||
break;
|
||||
case 'l':
|
||||
{
|
||||
if (i++ >= size)
|
||||
return -1;
|
||||
switch (GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
|
||||
fmt_address + i))
|
||||
{
|
||||
case 'd':
|
||||
trace_printf (sd, current_cpu, "%ld", (long) value);
|
||||
break;
|
||||
case 'i':
|
||||
trace_printf (sd, current_cpu, "%li", (long) value);
|
||||
break;
|
||||
case 'u':
|
||||
trace_printf (sd, current_cpu, "%lu", (unsigned long) value);
|
||||
break;
|
||||
case 'x':
|
||||
trace_printf (sd, current_cpu, "%lx", (unsigned long) value);
|
||||
break;
|
||||
case 'l':
|
||||
{
|
||||
if (i++ >= size)
|
||||
return -1;
|
||||
switch (GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
|
||||
fmt_address + i)) {
|
||||
case 'd':
|
||||
trace_printf (sd, current_cpu, "%lld", (long long) value);
|
||||
break;
|
||||
case 'i':
|
||||
trace_printf (sd, current_cpu, "%lli", (long long) value);
|
||||
break;
|
||||
case 'u':
|
||||
trace_printf (sd, current_cpu, "%llu", (unsigned long long) value);
|
||||
break;
|
||||
case 'x':
|
||||
trace_printf (sd, current_cpu, "%llx", (unsigned long long) value);
|
||||
break;
|
||||
default:
|
||||
assert (0);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
assert (0);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
/* XXX completeme */
|
||||
assert (0);
|
||||
break;
|
||||
}
|
||||
|
||||
tags_processed++;
|
||||
i++;
|
||||
break;
|
||||
case '\0':
|
||||
i = size;
|
||||
break;
|
||||
default:
|
||||
trace_printf (sd, current_cpu, "%c", c);
|
||||
bytes_written++;
|
||||
i++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return bytes_written;
|
||||
}
|
||||
@@ -1,194 +0,0 @@
|
||||
/* BPF helpers database.
|
||||
Copyright (C) 2019-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulator.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* This file contains the definition of the helpers that are available
|
||||
to BPF programs.
|
||||
|
||||
The primary source for information on kernel helpers is the
|
||||
linux/include/uapi/linux/bpf.h file in the Linux source tree.
|
||||
Please keep this database in sync.
|
||||
|
||||
The first column is the first kernel version featuring the helper
|
||||
function. This should be an enumerate from bpf_kernel_version,
|
||||
defined in bpf-opts.h. Note that the backend assumes that helpers
|
||||
never get deprecated in the kernel. If that eventually happens,
|
||||
then we will need to use a bitmask here instead of an enumerate.
|
||||
|
||||
The second column is the constant-name for the helper.
|
||||
The third column is the program-name of the helper.
|
||||
|
||||
The fourth column is a list of names describing the types of the
|
||||
values returned and accepted by the helper, in one of these forms:
|
||||
|
||||
TYPES (type1, type2, ..., 0)
|
||||
VTYPES (type1, type2, ..., 0)
|
||||
|
||||
VTYPES should be used should the helper accept a variable number of
|
||||
arguments, TYPES otherwise. The valid type names are:
|
||||
|
||||
`vt' for void.
|
||||
`it' for signed int.
|
||||
`ut' for unsigned int.
|
||||
`pt' for void*.
|
||||
`cpt' for const void*.
|
||||
`st' for short int.
|
||||
`ust' for unsigned short int.
|
||||
`cst' for const char *.
|
||||
`ullt' for unsigned long long.
|
||||
`llt' for long long.
|
||||
`u32t' for uint32.
|
||||
`u64t' for uint64.
|
||||
|
||||
In types descriptions, the firt entry corresponds to the value
|
||||
returned by the helper. Subsequent names correspond to the helper
|
||||
arguments. Finally, a 0 should close the list.
|
||||
|
||||
VERY IMPORTANT: the helper entries should be listed in the same
|
||||
order than in the definition of __BPF_FUNC_MAPPER in
|
||||
linux/include/uapi/linux/bpf.h! */
|
||||
|
||||
DEF_HELPER (LINUX_V4_0, MAP_LOOKUP_ELEM, map_lookup_elem, TYPES (pt, pt, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_0, MAP_UPDATE_ELEM, map_update_elem, TYPES (it, pt, pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_0, MAP_DELETE_ELEM, map_delete_elem, TYPES (it, pt, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_1, PROBE_READ, probe_read, TYPES (it, pt, ut, cpt, 0))
|
||||
DEF_HELPER (LINUX_V4_1, KTIME_GET_NS, ktime_get_ns, TYPES (ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_1, TRACE_PRINTK, trace_printk, VTYPES (it, cst, it, 0))
|
||||
DEF_HELPER (LINUX_V4_1, GET_PRANDOM_U32, get_prandom_u32, TYPES (ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_1, GET_SMP_PROCESSOR_ID, get_smp_processor_id, TYPES (ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_1, SKB_STORE_BYTES, skb_store_bytes, TYPES (it, pt, it, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_1, L3_CSUM_REPLACE, l3_csum_replace, TYPES (it, pt, it, it ,it ,it, 0))
|
||||
DEF_HELPER (LINUX_V4_1, L4_CSUM_REPLACE, l4_csum_replace, TYPES (it, pt, it, it, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_2, TAIL_CALL, tail_call, TYPES (vt, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_2, CLONE_REDIRECT, clone_redirect, TYPES (it, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_2, GET_CURRENT_PID_TGID, get_current_pid_tgid, TYPES (ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_2, GET_CURRENT_UID_GID, get_current_uid_gid, TYPES (ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_2, GET_CURRENT_COMM, get_current_comm, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_3, GET_CGROUP_CLASSID, get_cgroup_classid, TYPES (it, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_3, SKB_VLAN_PUSH, skb_vlan_push, TYPES (it, pt, st, ust, 0))
|
||||
DEF_HELPER (LINUX_V4_3, SKB_VLAN_POP, skb_vlan_pop, TYPES (it, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_3, SKB_GET_TUNNEL_KEY, skb_get_tunnel_key, TYPES (it, pt, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_3, SKB_SET_TUNNEL_KEY, skb_set_tunnel_key, TYPES (it, pt, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_3, PERF_EVENT_READ, perf_event_read, TYPES (ullt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_4, REDIRECT, redirect, TYPES (it, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_4, GET_ROUTE_REALM, get_route_realm, TYPES (ut, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_4, PERF_EVENT_OUTPUT, perf_event_output, \
|
||||
TYPES (it, pt, pt, ullt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_5, SKB_LOAD_BYTES, skb_load_bytes, TYPES (it, pt, it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_6, GET_STACKID, get_stackid, TYPES (it, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_6, CSUM_DIFF, csum_diff, TYPES (it, pt, it, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_6, SKB_GET_TUNNEL_OPT, skb_get_tunnel_opt, TYPES (it, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_6, SKB_SET_TUNNEL_OPT, skb_set_tunnel_opt, TYPES (it, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_8, SKB_CHANGE_PROTO, skb_change_proto, TYPES (it, pt, st, u64t, 0))
|
||||
DEF_HELPER (LINUX_V4_8, SKB_CHANGE_TYPE, skb_change_type, TYPES (it, pt, u32t, 0))
|
||||
DEF_HELPER (LINUX_V4_8, SKB_UNDER_CGROUP, skb_under_cgroup, TYPES (it, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_8, GET_HASH_RECALC, get_hash_recalc, TYPES (ut, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_8, GET_CURRENT_TASK, get_current_task, TYPES (ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_8, PROBE_WRITE_USER, probe_write_user, TYPES (it, pt, cpt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_9, CURRENT_TASK_UNDER_CGROUP, current_task_under_cgroup, \
|
||||
TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_9, SKB_CHANGE_TAIL, skb_change_tail, TYPES (it, pt, ut, u64t, 0))
|
||||
DEF_HELPER (LINUX_V4_9, SKB_PULL_DATA, skb_pull_data, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_9, CSUM_UPDATE, csum_update, TYPES (llt, pt, u32t, 0))
|
||||
DEF_HELPER (LINUX_V4_9, SET_HASH_INVALID, set_hash_invalid, TYPES (vt, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_10, GET_NUMA_NODE_ID, get_numa_node_id, TYPES (it, 0))
|
||||
DEF_HELPER (LINUX_V4_10, SKB_CHANGE_HEAD, skb_change_head, TYPES (it, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_10, XDP_ADJUST_HEAD, xdp_adjust_head, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_11, PROBE_READ_STR, probe_read_str, TYPES (it, pt, u32t, cpt, 0))
|
||||
DEF_HELPER (LINUX_V4_12, GET_SOCKET_COOKIE, get_socket_cookie, TYPES (it, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_12, GET_SOCKET_UID, get_socket_uid, TYPES (ut, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_13, SET_HASH, set_hash, TYPES (ut, pt, u32t, 0))
|
||||
DEF_HELPER (LINUX_V4_13, SETSOCKOPT, setsockopt, TYPES (it, pt, it, it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_13, SKB_ADJUST_ROOM, skb_adjust_room, TYPES (it, pt, st, u32t, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_14, REDIRECT_MAP, redirect_map, TYPES (it, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_14, SK_REDIRECT_MAP, sk_redirect_map, TYPES (it, pt, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_14, SOCK_MAP_UPDATE, sock_map_update, TYPES (it, pt, pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_15, XDP_ADJUST_META, xdp_adjust_meta, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_15, PERF_EVENT_READ_VALUE, perf_event_read_value,
|
||||
TYPES (it, pt, ullt, pt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_15, PERF_PROG_READ_VALUE, perf_prog_read_value,
|
||||
TYPES (it, pt, pt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_15, GETSOCKOPT, getsockopt, TYPES (it, pt, it, it, pt, it, 0))
|
||||
|
||||
DEF_HELPER (LINUX_V4_16, OVERRIDE_RETURN, override_return, TYPES (it, pt, ult, 0))
|
||||
DEF_HELPER (LINUX_V4_16, SOCK_OPS_CB_FLAGS_SET, sock_ops_cb_flags_set, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_17, MSG_REDIRECT_MAP, msg_redirect_map, TYPES (it, pt, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_17, MSG_APPLY_BYTES, msg_apply_bytes, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_17, MSG_CORK_BYTES, msg_cork_bytes, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_17, MSG_PULL_DATA, msg_pull_data, TYPES (it, pt, it, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_17, BIND, bind, TYPES (it, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_18, XDP_ADJUST_TAIL, xdp_adjust_tail, TYPES (it, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_18, SKB_GET_XFRM_STATE,
|
||||
skb_get_xfrm_state, TYPES (it, pt, it, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_18, GET_STACK, get_stack, TYPES (it, pt, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V4_18, SKB_LOAD_BYTES_RELATIVE, skb_load_bytes_relative,
|
||||
TYPES (it, pt, it, pt, it, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_18, FIB_LOOKUP, fib_lookup, TYPES (it, pt, pt, it, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_18, SOCK_HASH_UPDATE, sock_hash_update, TYPES (it, pt, pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_18, MSG_REDIRECT_HASH, msg_redirect_hash, TYPES (it, pt, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_18, SK_REDIRECT_HASH, sk_redirect_hash, TYPES (it, pt, pt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_18, LWT_PUSH_ENCAP, lwt_push_encap, TYPES (it, pt, ut, pt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_18, LWT_SEG6_STORE_BYTES, lwt_seg6_store_bytes,
|
||||
TYPES (it, pt, ut, pt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_18, LWT_SEG6_ADJUST_SRH, lwt_seg6_adjust_srh, TYPES (it, pt, ut, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_18, LWT_SEG6_ACTION, lwt_seg6_action, TYPES (it, pt, ut, pt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_18, RC_REPEAT, rc_repeat, TYPES (it, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_18, RC_KEYDOWN, rc_keydown, TYPES (it, pt, ut, ullt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_18, SKB_CGROUP_ID, skb_cgroup_id, TYPES (ullt, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_18, GET_CURRENT_CGROUP_ID, get_current_cgroup_id, TYPES (ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_19, GET_LOCAL_STORAGE, get_local_storage, TYPES (pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_19, SK_SELECT_REUSEPORT, sk_select_reuseport,
|
||||
TYPES (it, pt, pt, pt, ut, 0))
|
||||
DEF_HELPER (LINUX_V4_19, SKB_ANCESTOR_CGROUP_ID, skb_ancestor_cgroup_id,
|
||||
TYPES (ullt, pt, it, 0))
|
||||
DEF_HELPER (LINUX_V4_20, SK_LOOKUP_TCP, sk_lookup_tcp, TYPES (pt, pt, pt, it, ullt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_20, SK_LOOKUP_UDP, sk_lookup_udp, TYPES (pt, pt, pt, it, ullt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_20, SK_RELEASE, sk_release, TYPES (it, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_20, MAP_PUSH_ELEM, map_push_elem, TYPES (it, pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V4_20, MAP_POP_ELEM, map_pop_elem, TYPES (it, pt, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_20, MAP_PEEK_ELEM, map_peek_elem, TYPES (it, pt, pt, 0))
|
||||
DEF_HELPER (LINUX_V4_20, MSG_PUSH_DATA, msg_push_data, TYPES (it, pt, it, it, it, 0))
|
||||
DEF_HELPER (LINUX_V5_0, MSG_POP_DATA, msg_pop_data, TYPES (it, pt, it, it, it, 0))
|
||||
DEF_HELPER (LINUX_V5_0, RC_POINTER_REL, rc_pointer_rel, TYPES (it, pt, it, it, 0))
|
||||
DEF_HELPER (LINUX_V5_1, SPIN_LOCK, spin_lock, TYPES (vt, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_1, SPIN_UNLOCK, spin_unlock, TYPES (vt, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_1, SK_FULLSOCK, sk_fullsock, TYPES (pt, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_1, TCP_SOCK, tcp_sock, TYPES (pt, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_1, SKB_ECN_SET_CE, skb_ecn_set_ce, TYPES (it, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_1, GET_LISTENER_SOCK, get_listener_sock, TYPES (pt, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_2, SKC_LOOKUP_TCP, skc_lookup_tcp,
|
||||
TYPES (pt, pt, pt, u32t, u64t, u64t, 0))
|
||||
DEF_HELPER (LINUX_V5_2, TCP_CHECK_SYNCOOKIE, tcp_check_syncookie,
|
||||
TYPES (it, pt, pt, u32t, pt, u32t, 0))
|
||||
DEF_HELPER (LINUX_V5_2, SYSCTL_GET_NAME, sysctl_get_name, TYPES (it, pt, pt, ullt, u64t, 0))
|
||||
DEF_HELPER (LINUX_V5_2, SYSCTL_GET_CURRENT_VALUE, sysctl_get_current_value,
|
||||
TYPES (it, pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V5_2, SYSCTL_GET_NEW_VALUE, sysctl_get_new_value,
|
||||
TYPES (it, pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V5_2, SYSCTL_SET_NEW_VALUE, sysctl_set_new_value,
|
||||
TYPES (it, pt, pt, ullt, 0))
|
||||
DEF_HELPER (LINUX_V5_2, STRTOL, strtol, TYPES (it, cst, ullt, u64t, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_2, STRTOUL, strtoul, TYPES (it, pt, ullt, u64t, pt, 0))
|
||||
DEF_HELPER (LINUX_V5_2, SK_STORAGE_GET, sk_storage_get, TYPES (pt, pt, pt, pt, u64t, 0))
|
||||
DEF_HELPER (LINUX_V5_2, SK_STORAGE_DELETE, sk_storage_delete, TYPES (it, pt, pt, 0))
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
mode:c
|
||||
End:
|
||||
*/
|
||||
@@ -1,33 +0,0 @@
|
||||
/* Emulation of eBPF helpers. Interface.
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef BPF_HELPERS_H
|
||||
#define BPF_HELPERS_H
|
||||
|
||||
enum bpf_kernel_helper
|
||||
{
|
||||
#define DEF_HELPER(kver, name, fn, types) name,
|
||||
#include "bpf-helpers.def"
|
||||
#undef DEF_HELPER
|
||||
};
|
||||
|
||||
int bpf_trace_printk (SIM_CPU *current_cpu);
|
||||
|
||||
VOID bpfbf_breakpoint (SIM_CPU *current_cpu);
|
||||
|
||||
#endif /* ! BPF_HELPERS_H */
|
||||
+1455
File diff suppressed because it is too large
Load Diff
+11
-9
@@ -1,5 +1,7 @@
|
||||
/* eBPF simulator support code header
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
/* BPF simulator support code header
|
||||
Copyright (C) 2023 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Oracle Inc.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
@@ -19,13 +21,13 @@
|
||||
#ifndef BPF_SIM_H
|
||||
#define BPF_SIM_H
|
||||
|
||||
void bpfbf_insn_before (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
|
||||
void bpfbf_insn_after (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
|
||||
/* The following struct determines the state of the simulator. */
|
||||
|
||||
DI bpfbf_endbe (SIM_CPU *, DI, UINT);
|
||||
DI bpfbf_endle (SIM_CPU *, DI, UINT);
|
||||
DI bpfbf_skb_data_offset (SIM_CPU *);
|
||||
VOID bpfbf_call (SIM_CPU *, INT, UINT);
|
||||
VOID bpfbf_exit (SIM_CPU *);
|
||||
struct bpf_sim_state
|
||||
{
|
||||
|
||||
};
|
||||
|
||||
#define BPF_SIM_STATE(sd) ((struct bpf_sim_state *) STATE_ARCH_DATA (sd))
|
||||
|
||||
#endif /* ! BPF_SIM_H */
|
||||
|
||||
-329
@@ -1,329 +0,0 @@
|
||||
/* eBPF simulator support code
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* This must come before any other includes. */
|
||||
#include "defs.h"
|
||||
|
||||
#define WANT_CPU_BPFBF
|
||||
#define WANT_CPU bpfbf
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "sim-fpu.h"
|
||||
#include "sim-signal.h"
|
||||
#include "cgen-mem.h"
|
||||
#include "cgen-ops.h"
|
||||
#include "cpuall.h"
|
||||
#include "decode.h"
|
||||
|
||||
#include "decode-be.h"
|
||||
#include "decode-le.h"
|
||||
|
||||
#include "defs-le.h" /* For SCACHE */
|
||||
#include "bpf-helpers.h"
|
||||
|
||||
uint64_t skb_data_offset;
|
||||
|
||||
IDESC *bpf_idesc_le;
|
||||
IDESC *bpf_idesc_be;
|
||||
|
||||
|
||||
int
|
||||
bpfbf_fetch_register (SIM_CPU *current_cpu,
|
||||
int rn,
|
||||
void *buf,
|
||||
int len)
|
||||
{
|
||||
if (rn == 11)
|
||||
SETTDI (buf, CPU_PC_GET (current_cpu));
|
||||
else if (0 <= rn && rn < 10)
|
||||
SETTDI (buf, GET_H_GPR (rn));
|
||||
else
|
||||
return 0;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
int
|
||||
bpfbf_store_register (SIM_CPU *current_cpu,
|
||||
int rn,
|
||||
const void *buf,
|
||||
int len)
|
||||
{
|
||||
if (rn == 11)
|
||||
CPU_PC_SET (current_cpu, GETTDI (buf));
|
||||
else if (0 <= rn && rn < 10)
|
||||
SET_H_GPR (rn, GETTDI (buf));
|
||||
else
|
||||
return 0;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
void
|
||||
bpfbf_model_insn_before (SIM_CPU *current_cpu, int first_p)
|
||||
{
|
||||
/* XXX */
|
||||
}
|
||||
|
||||
void
|
||||
bpfbf_model_insn_after (SIM_CPU *current_cpu, int first_p, int cycles)
|
||||
{
|
||||
/* XXX */
|
||||
}
|
||||
|
||||
|
||||
/***** Instruction helpers. *****/
|
||||
|
||||
/* The semantic routines for most instructions are expressed in RTL in
|
||||
the cpu/bpf.cpu file, and automatically translated to C in the
|
||||
sem-*.c files in this directory.
|
||||
|
||||
However, some of the semantic routines make use of helper C
|
||||
functions. This happens when the semantics of the instructions
|
||||
can't be expressed in RTL alone in a satisfactory way, or not at
|
||||
all.
|
||||
|
||||
The following functions implement these C helpers. */
|
||||
|
||||
DI
|
||||
bpfbf_endle (SIM_CPU *current_cpu, DI value, UINT bitsize)
|
||||
{
|
||||
switch (bitsize)
|
||||
{
|
||||
case 16: return endian_h2le_2(endian_t2h_2(value));
|
||||
case 32: return endian_h2le_4(endian_t2h_4(value));
|
||||
case 64: return endian_h2le_8(endian_t2h_8(value));
|
||||
default: assert(0);
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
DI
|
||||
bpfbf_endbe (SIM_CPU *current_cpu, DI value, UINT bitsize)
|
||||
{
|
||||
switch (bitsize)
|
||||
{
|
||||
case 16: return endian_h2be_2(endian_t2h_2(value));
|
||||
case 32: return endian_h2be_4(endian_t2h_4(value));
|
||||
case 64: return endian_h2be_8(endian_t2h_8(value));
|
||||
default: assert(0);
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
DI
|
||||
bpfbf_skb_data_offset (SIM_CPU *current_cpu)
|
||||
{
|
||||
/* Simply return the user-configured value.
|
||||
This will be 0 if it has not been set. */
|
||||
return skb_data_offset;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
bpfbf_call (SIM_CPU *current_cpu, INT disp32, UINT src)
|
||||
{
|
||||
/* eBPF supports two kind of CALL instructions: the so called pseudo
|
||||
calls ("bpf to bpf") and external calls ("bpf to helper").
|
||||
|
||||
Both kind of calls use the same instruction (CALL). However,
|
||||
external calls are constructed by passing a constant argument to
|
||||
the instruction, that identifies the helper, whereas pseudo calls
|
||||
result from expressions involving symbols.
|
||||
|
||||
We distinguish calls from pseudo-calls with the later having a 1
|
||||
stored in the SRC field of the instruction. */
|
||||
|
||||
if (src == 1)
|
||||
{
|
||||
/* This is a pseudo-call. */
|
||||
|
||||
/* XXX allocate a new stack frame and transfer control. For
|
||||
that we need to analyze the target function, like the kernel
|
||||
verifier does. We better populate a cache
|
||||
(function_start_address -> frame_size) so we avoid
|
||||
calculating this more than once. */
|
||||
/* XXX note that disp32 is PC-relative in number of 64-bit
|
||||
words, _minus one_. */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* This is a call to a helper.
|
||||
|
||||
DISP32 contains the helper number. Dispatch to the
|
||||
corresponding helper emulator in bpf-helpers.c. */
|
||||
|
||||
switch (disp32) {
|
||||
/* case TRACE_PRINTK: */
|
||||
case 7:
|
||||
bpf_trace_printk (current_cpu);
|
||||
break;
|
||||
default:;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
bpfbf_exit (SIM_CPU *current_cpu)
|
||||
{
|
||||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||||
|
||||
/* r0 holds "return code" */
|
||||
DI r0 = GET_H_GPR (0);
|
||||
|
||||
printf ("exit %" PRId64 " (0x%" PRIx64 ")\n", r0, r0);
|
||||
|
||||
sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu),
|
||||
sim_exited, 0 /* sigrc */);
|
||||
}
|
||||
|
||||
VOID
|
||||
bpfbf_breakpoint (SIM_CPU *current_cpu)
|
||||
{
|
||||
SIM_DESC sd = CPU_STATE (current_cpu);
|
||||
|
||||
sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu),
|
||||
sim_stopped, SIM_SIGTRAP);
|
||||
}
|
||||
|
||||
/* We use the definitions below instead of the cgen-generated model.c,
|
||||
because the later is not really able to work with cpus featuring
|
||||
several ISAs. This should be fixed in CGEN. */
|
||||
|
||||
static void
|
||||
bpf_def_model_init (SIM_CPU *cpu)
|
||||
{
|
||||
/* Do nothing. */
|
||||
}
|
||||
|
||||
static void
|
||||
bpfbf_prepare_run (SIM_CPU *cpu)
|
||||
{
|
||||
/* Nothing. */
|
||||
}
|
||||
|
||||
static void
|
||||
bpf_engine_run_full (SIM_CPU *cpu)
|
||||
{
|
||||
if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
|
||||
{
|
||||
if (!bpf_idesc_le)
|
||||
{
|
||||
bpfbf_ebpfle_init_idesc_table (cpu);
|
||||
bpf_idesc_le = CPU_IDESC (cpu);
|
||||
}
|
||||
else
|
||||
CPU_IDESC (cpu) = bpf_idesc_le;
|
||||
|
||||
bpfbf_ebpfle_engine_run_full (cpu);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (!bpf_idesc_be)
|
||||
{
|
||||
bpfbf_ebpfbe_init_idesc_table (cpu);
|
||||
bpf_idesc_be = CPU_IDESC (cpu);
|
||||
}
|
||||
else
|
||||
CPU_IDESC (cpu) = bpf_idesc_be;
|
||||
|
||||
bpfbf_ebpfbe_engine_run_full (cpu);
|
||||
}
|
||||
}
|
||||
|
||||
#if WITH_FAST
|
||||
|
||||
void
|
||||
bpf_engine_run_fast (SIM_CPU *cpu)
|
||||
{
|
||||
if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
|
||||
{
|
||||
if (!bpf_idesc_le)
|
||||
{
|
||||
bpfbf_ebpfle_init_idesc_table (cpu);
|
||||
bpf_idesc_le = CPU_IDESC (cpu);
|
||||
}
|
||||
else
|
||||
CPU_IDESC (cpu) = bpf_idesc_le;
|
||||
|
||||
bpfbf_ebpfle_engine_run_fast (cpu);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (!bpf_idesc_be)
|
||||
{
|
||||
bpfbf_ebpfbe_init_idesc_table (cpu);
|
||||
bpf_idesc_be = CPU_IDESC (cpu);
|
||||
}
|
||||
else
|
||||
CPU_IDESC (cpu) = bpf_idesc_be;
|
||||
|
||||
bpfbf_ebpfbe_engine_run_fast (cpu);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* WITH_FAST */
|
||||
|
||||
static const CGEN_INSN *
|
||||
bpfbf_get_idata (SIM_CPU *cpu, int inum)
|
||||
{
|
||||
return CPU_IDESC (cpu) [inum].idata;
|
||||
}
|
||||
|
||||
static void
|
||||
bpf_init_cpu (SIM_CPU *cpu)
|
||||
{
|
||||
CPU_REG_FETCH (cpu) = bpfbf_fetch_register;
|
||||
CPU_REG_STORE (cpu) = bpfbf_store_register;
|
||||
CPU_PC_FETCH (cpu) = bpfbf_h_pc_get;
|
||||
CPU_PC_STORE (cpu) = bpfbf_h_pc_set;
|
||||
CPU_GET_IDATA (cpu) = bpfbf_get_idata;
|
||||
/* Only used by profiling. 0 disables it. */
|
||||
CPU_MAX_INSNS (cpu) = 0;
|
||||
CPU_INSN_NAME (cpu) = cgen_insn_name;
|
||||
CPU_FULL_ENGINE_FN (cpu) = bpf_engine_run_full;
|
||||
#if WITH_FAST
|
||||
CPU_FAST_ENGINE_FN (cpu) = bpf_engine_run_fast;
|
||||
#else
|
||||
CPU_FAST_ENGINE_FN (cpu) = bpf_engine_run_full;
|
||||
#endif
|
||||
}
|
||||
|
||||
static const SIM_MODEL bpf_models[] =
|
||||
{
|
||||
{ "bpf-def", & bpf_mach, MODEL_BPF_DEF, NULL, bpf_def_model_init },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
static const SIM_MACH_IMP_PROPERTIES bpfbf_imp_properties =
|
||||
{
|
||||
sizeof (SIM_CPU),
|
||||
#if WITH_SCACHE
|
||||
sizeof (SCACHE)
|
||||
#else
|
||||
0
|
||||
#endif
|
||||
};
|
||||
|
||||
const SIM_MACH bpf_mach =
|
||||
{
|
||||
"bpf", "bpf", MACH_BPF,
|
||||
32, 32, & bpf_models[0], & bpfbf_imp_properties,
|
||||
bpf_init_cpu,
|
||||
bpfbf_prepare_run
|
||||
};
|
||||
@@ -1,61 +0,0 @@
|
||||
/* Misc. support for CPU family bpfbf.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#define WANT_CPU bpfbf
|
||||
#define WANT_CPU_BPFBF
|
||||
|
||||
#include "sim-main.h"
|
||||
#include "cgen-ops.h"
|
||||
|
||||
/* Get the value of h-gpr. */
|
||||
|
||||
DI
|
||||
bpfbf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
|
||||
{
|
||||
return CPU (h_gpr[regno]);
|
||||
}
|
||||
|
||||
/* Set a value for h-gpr. */
|
||||
|
||||
void
|
||||
bpfbf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
|
||||
{
|
||||
CPU (h_gpr[regno]) = newval;
|
||||
}
|
||||
|
||||
/* Get the value of h-pc. */
|
||||
|
||||
UDI
|
||||
bpfbf_h_pc_get (SIM_CPU *current_cpu)
|
||||
{
|
||||
return GET_H_PC ();
|
||||
}
|
||||
|
||||
/* Set a value for h-pc. */
|
||||
|
||||
void
|
||||
bpfbf_h_pc_set (SIM_CPU *current_cpu, UDI newval)
|
||||
{
|
||||
SET_H_PC (newval);
|
||||
}
|
||||
@@ -1,81 +0,0 @@
|
||||
/* CPU family header for bpfbf.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef CPU_BPFBF_H
|
||||
#define CPU_BPFBF_H
|
||||
|
||||
/* Maximum number of instructions that are fetched at a time.
|
||||
This is for LIW type instructions sets (e.g. m32r). */
|
||||
#define MAX_LIW_INSNS 1
|
||||
|
||||
/* Maximum number of instructions that can be executed in parallel. */
|
||||
#define MAX_PARALLEL_INSNS 1
|
||||
|
||||
/* The size of an "int" needed to hold an instruction word.
|
||||
This is usually 32 bits, but some architectures needs 64 bits. */
|
||||
typedef CGEN_INSN_LGUINT CGEN_INSN_WORD;
|
||||
|
||||
#include "cgen-engine.h"
|
||||
|
||||
/* CPU state information. */
|
||||
typedef struct {
|
||||
/* Hardware elements. */
|
||||
struct {
|
||||
/* General Purpose Registers */
|
||||
DI h_gpr[16];
|
||||
#define GET_H_GPR(a1) CPU (h_gpr)[a1]
|
||||
#define SET_H_GPR(a1, x) (CPU (h_gpr)[a1] = (x))
|
||||
/* program counter */
|
||||
UDI h_pc;
|
||||
#define GET_H_PC() CPU (h_pc)
|
||||
#define SET_H_PC(x) \
|
||||
do { \
|
||||
CPU (h_pc) = (x);\
|
||||
;} while (0)
|
||||
} hardware;
|
||||
#define CPU_CGEN_HW(cpu) (& BPF_SIM_CPU (cpu)->cpu_data.hardware)
|
||||
} BPFBF_CPU_DATA;
|
||||
|
||||
/* Cover fns for register access. */
|
||||
DI bpfbf_h_gpr_get (SIM_CPU *, UINT);
|
||||
void bpfbf_h_gpr_set (SIM_CPU *, UINT, DI);
|
||||
UDI bpfbf_h_pc_get (SIM_CPU *);
|
||||
void bpfbf_h_pc_set (SIM_CPU *, UDI);
|
||||
|
||||
/* These must be hand-written. */
|
||||
extern CPUREG_FETCH_FN bpfbf_fetch_register;
|
||||
extern CPUREG_STORE_FN bpfbf_store_register;
|
||||
|
||||
typedef struct {
|
||||
int empty;
|
||||
} MODEL_BPF_DEF_DATA;
|
||||
|
||||
/* Collection of various things for the trace handler to use. */
|
||||
|
||||
typedef struct trace_record {
|
||||
IADDR pc;
|
||||
/* FIXME:wip */
|
||||
} TRACE_RECORD;
|
||||
|
||||
#endif /* CPU_BPFBF_H */
|
||||
@@ -1,65 +0,0 @@
|
||||
/* Simulator CPU header for bpf.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef BPF_CPUALL_H
|
||||
#define BPF_CPUALL_H
|
||||
|
||||
/* Include files for each cpu family. */
|
||||
|
||||
#ifdef WANT_CPU_BPFBF
|
||||
#include "eng.h"
|
||||
#include "cpu.h"
|
||||
#include "decode.h"
|
||||
#endif
|
||||
|
||||
extern const SIM_MACH bpf_mach;
|
||||
|
||||
#ifndef WANT_CPU
|
||||
/* The ARGBUF struct. */
|
||||
struct argbuf {
|
||||
/* These are the baseclass definitions. */
|
||||
IADDR addr;
|
||||
const IDESC *idesc;
|
||||
char trace_p;
|
||||
char profile_p;
|
||||
/* ??? Temporary hack for skip insns. */
|
||||
char skip_count;
|
||||
char unused;
|
||||
/* cpu specific data follows */
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifndef WANT_CPU
|
||||
/* A cached insn.
|
||||
|
||||
??? SCACHE used to contain more than just argbuf. We could delete the
|
||||
type entirely and always just use ARGBUF, but for future concerns and as
|
||||
a level of abstraction it is left in. */
|
||||
|
||||
struct scache {
|
||||
struct argbuf argbuf;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* BPF_CPUALL_H */
|
||||
-1131
File diff suppressed because it is too large
Load Diff
@@ -1,94 +0,0 @@
|
||||
/* Decode header for bpfbf_ebpfbe.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef BPFBF_EBPFBE_DECODE_H
|
||||
#define BPFBF_EBPFBE_DECODE_H
|
||||
|
||||
extern const IDESC *bpfbf_ebpfbe_decode (SIM_CPU *, IADDR,
|
||||
CGEN_INSN_WORD,
|
||||
ARGBUF *);
|
||||
extern void bpfbf_ebpfbe_init_idesc_table (SIM_CPU *);
|
||||
extern void bpfbf_ebpfbe_sem_init_idesc_table (SIM_CPU *);
|
||||
extern void bpfbf_ebpfbe_semf_init_idesc_table (SIM_CPU *);
|
||||
|
||||
/* Enum declaration for instructions in cpu family bpfbf. */
|
||||
typedef enum bpfbf_ebpfbe_insn_type {
|
||||
BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_AFTER, BPFBF_EBPFBE_INSN_X_BEFORE, BPFBF_EBPFBE_INSN_X_CTI_CHAIN
|
||||
, BPFBF_EBPFBE_INSN_X_CHAIN, BPFBF_EBPFBE_INSN_X_BEGIN, BPFBF_EBPFBE_INSN_ADDIBE, BPFBF_EBPFBE_INSN_ADDRBE
|
||||
, BPFBF_EBPFBE_INSN_ADD32IBE, BPFBF_EBPFBE_INSN_ADD32RBE, BPFBF_EBPFBE_INSN_SUBIBE, BPFBF_EBPFBE_INSN_SUBRBE
|
||||
, BPFBF_EBPFBE_INSN_SUB32IBE, BPFBF_EBPFBE_INSN_SUB32RBE, BPFBF_EBPFBE_INSN_MULIBE, BPFBF_EBPFBE_INSN_MULRBE
|
||||
, BPFBF_EBPFBE_INSN_MUL32IBE, BPFBF_EBPFBE_INSN_MUL32RBE, BPFBF_EBPFBE_INSN_DIVIBE, BPFBF_EBPFBE_INSN_DIVRBE
|
||||
, BPFBF_EBPFBE_INSN_DIV32IBE, BPFBF_EBPFBE_INSN_DIV32RBE, BPFBF_EBPFBE_INSN_ORIBE, BPFBF_EBPFBE_INSN_ORRBE
|
||||
, BPFBF_EBPFBE_INSN_OR32IBE, BPFBF_EBPFBE_INSN_OR32RBE, BPFBF_EBPFBE_INSN_ANDIBE, BPFBF_EBPFBE_INSN_ANDRBE
|
||||
, BPFBF_EBPFBE_INSN_AND32IBE, BPFBF_EBPFBE_INSN_AND32RBE, BPFBF_EBPFBE_INSN_LSHIBE, BPFBF_EBPFBE_INSN_LSHRBE
|
||||
, BPFBF_EBPFBE_INSN_LSH32IBE, BPFBF_EBPFBE_INSN_LSH32RBE, BPFBF_EBPFBE_INSN_RSHIBE, BPFBF_EBPFBE_INSN_RSHRBE
|
||||
, BPFBF_EBPFBE_INSN_RSH32IBE, BPFBF_EBPFBE_INSN_RSH32RBE, BPFBF_EBPFBE_INSN_MODIBE, BPFBF_EBPFBE_INSN_MODRBE
|
||||
, BPFBF_EBPFBE_INSN_MOD32IBE, BPFBF_EBPFBE_INSN_MOD32RBE, BPFBF_EBPFBE_INSN_XORIBE, BPFBF_EBPFBE_INSN_XORRBE
|
||||
, BPFBF_EBPFBE_INSN_XOR32IBE, BPFBF_EBPFBE_INSN_XOR32RBE, BPFBF_EBPFBE_INSN_ARSHIBE, BPFBF_EBPFBE_INSN_ARSHRBE
|
||||
, BPFBF_EBPFBE_INSN_ARSH32IBE, BPFBF_EBPFBE_INSN_ARSH32RBE, BPFBF_EBPFBE_INSN_NEGBE, BPFBF_EBPFBE_INSN_NEG32BE
|
||||
, BPFBF_EBPFBE_INSN_MOVIBE, BPFBF_EBPFBE_INSN_MOVRBE, BPFBF_EBPFBE_INSN_MOV32IBE, BPFBF_EBPFBE_INSN_MOV32RBE
|
||||
, BPFBF_EBPFBE_INSN_ENDLEBE, BPFBF_EBPFBE_INSN_ENDBEBE, BPFBF_EBPFBE_INSN_LDDWBE, BPFBF_EBPFBE_INSN_LDABSW
|
||||
, BPFBF_EBPFBE_INSN_LDABSH, BPFBF_EBPFBE_INSN_LDABSB, BPFBF_EBPFBE_INSN_LDABSDW, BPFBF_EBPFBE_INSN_LDINDWBE
|
||||
, BPFBF_EBPFBE_INSN_LDINDHBE, BPFBF_EBPFBE_INSN_LDINDBBE, BPFBF_EBPFBE_INSN_LDINDDWBE, BPFBF_EBPFBE_INSN_LDXWBE
|
||||
, BPFBF_EBPFBE_INSN_LDXHBE, BPFBF_EBPFBE_INSN_LDXBBE, BPFBF_EBPFBE_INSN_LDXDWBE, BPFBF_EBPFBE_INSN_STXWBE
|
||||
, BPFBF_EBPFBE_INSN_STXHBE, BPFBF_EBPFBE_INSN_STXBBE, BPFBF_EBPFBE_INSN_STXDWBE, BPFBF_EBPFBE_INSN_STBBE
|
||||
, BPFBF_EBPFBE_INSN_STHBE, BPFBF_EBPFBE_INSN_STWBE, BPFBF_EBPFBE_INSN_STDWBE, BPFBF_EBPFBE_INSN_JEQIBE
|
||||
, BPFBF_EBPFBE_INSN_JEQRBE, BPFBF_EBPFBE_INSN_JEQ32IBE, BPFBF_EBPFBE_INSN_JEQ32RBE, BPFBF_EBPFBE_INSN_JGTIBE
|
||||
, BPFBF_EBPFBE_INSN_JGTRBE, BPFBF_EBPFBE_INSN_JGT32IBE, BPFBF_EBPFBE_INSN_JGT32RBE, BPFBF_EBPFBE_INSN_JGEIBE
|
||||
, BPFBF_EBPFBE_INSN_JGERBE, BPFBF_EBPFBE_INSN_JGE32IBE, BPFBF_EBPFBE_INSN_JGE32RBE, BPFBF_EBPFBE_INSN_JLTIBE
|
||||
, BPFBF_EBPFBE_INSN_JLTRBE, BPFBF_EBPFBE_INSN_JLT32IBE, BPFBF_EBPFBE_INSN_JLT32RBE, BPFBF_EBPFBE_INSN_JLEIBE
|
||||
, BPFBF_EBPFBE_INSN_JLERBE, BPFBF_EBPFBE_INSN_JLE32IBE, BPFBF_EBPFBE_INSN_JLE32RBE, BPFBF_EBPFBE_INSN_JSETIBE
|
||||
, BPFBF_EBPFBE_INSN_JSETRBE, BPFBF_EBPFBE_INSN_JSET32IBE, BPFBF_EBPFBE_INSN_JSET32RBE, BPFBF_EBPFBE_INSN_JNEIBE
|
||||
, BPFBF_EBPFBE_INSN_JNERBE, BPFBF_EBPFBE_INSN_JNE32IBE, BPFBF_EBPFBE_INSN_JNE32RBE, BPFBF_EBPFBE_INSN_JSGTIBE
|
||||
, BPFBF_EBPFBE_INSN_JSGTRBE, BPFBF_EBPFBE_INSN_JSGT32IBE, BPFBF_EBPFBE_INSN_JSGT32RBE, BPFBF_EBPFBE_INSN_JSGEIBE
|
||||
, BPFBF_EBPFBE_INSN_JSGERBE, BPFBF_EBPFBE_INSN_JSGE32IBE, BPFBF_EBPFBE_INSN_JSGE32RBE, BPFBF_EBPFBE_INSN_JSLTIBE
|
||||
, BPFBF_EBPFBE_INSN_JSLTRBE, BPFBF_EBPFBE_INSN_JSLT32IBE, BPFBF_EBPFBE_INSN_JSLT32RBE, BPFBF_EBPFBE_INSN_JSLEIBE
|
||||
, BPFBF_EBPFBE_INSN_JSLERBE, BPFBF_EBPFBE_INSN_JSLE32IBE, BPFBF_EBPFBE_INSN_JSLE32RBE, BPFBF_EBPFBE_INSN_CALLBE
|
||||
, BPFBF_EBPFBE_INSN_JA, BPFBF_EBPFBE_INSN_EXIT, BPFBF_EBPFBE_INSN_XADDDWBE, BPFBF_EBPFBE_INSN_XADDWBE
|
||||
, BPFBF_EBPFBE_INSN_BRKPT, BPFBF_EBPFBE_INSN__MAX
|
||||
} BPFBF_EBPFBE_INSN_TYPE;
|
||||
|
||||
/* Enum declaration for semantic formats in cpu family bpfbf. */
|
||||
typedef enum bpfbf_ebpfbe_sfmt_type {
|
||||
BPFBF_EBPFBE_SFMT_EMPTY, BPFBF_EBPFBE_SFMT_ADDIBE, BPFBF_EBPFBE_SFMT_ADDRBE, BPFBF_EBPFBE_SFMT_NEGBE
|
||||
, BPFBF_EBPFBE_SFMT_MOVIBE, BPFBF_EBPFBE_SFMT_MOVRBE, BPFBF_EBPFBE_SFMT_ENDLEBE, BPFBF_EBPFBE_SFMT_LDDWBE
|
||||
, BPFBF_EBPFBE_SFMT_LDABSW, BPFBF_EBPFBE_SFMT_LDABSH, BPFBF_EBPFBE_SFMT_LDABSB, BPFBF_EBPFBE_SFMT_LDABSDW
|
||||
, BPFBF_EBPFBE_SFMT_LDINDWBE, BPFBF_EBPFBE_SFMT_LDINDHBE, BPFBF_EBPFBE_SFMT_LDINDBBE, BPFBF_EBPFBE_SFMT_LDINDDWBE
|
||||
, BPFBF_EBPFBE_SFMT_LDXWBE, BPFBF_EBPFBE_SFMT_LDXHBE, BPFBF_EBPFBE_SFMT_LDXBBE, BPFBF_EBPFBE_SFMT_LDXDWBE
|
||||
, BPFBF_EBPFBE_SFMT_STXWBE, BPFBF_EBPFBE_SFMT_STXHBE, BPFBF_EBPFBE_SFMT_STXBBE, BPFBF_EBPFBE_SFMT_STXDWBE
|
||||
, BPFBF_EBPFBE_SFMT_STBBE, BPFBF_EBPFBE_SFMT_STHBE, BPFBF_EBPFBE_SFMT_STWBE, BPFBF_EBPFBE_SFMT_STDWBE
|
||||
, BPFBF_EBPFBE_SFMT_JEQIBE, BPFBF_EBPFBE_SFMT_JEQRBE, BPFBF_EBPFBE_SFMT_CALLBE, BPFBF_EBPFBE_SFMT_JA
|
||||
, BPFBF_EBPFBE_SFMT_EXIT, BPFBF_EBPFBE_SFMT_XADDDWBE, BPFBF_EBPFBE_SFMT_XADDWBE
|
||||
} BPFBF_EBPFBE_SFMT_TYPE;
|
||||
|
||||
/* Function unit handlers (user written). */
|
||||
|
||||
extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
|
||||
/* Profiling before/after handlers (user written) */
|
||||
|
||||
extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
|
||||
extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
|
||||
|
||||
#endif /* BPFBF_EBPFBE_DECODE_H */
|
||||
-1131
File diff suppressed because it is too large
Load Diff
@@ -1,94 +0,0 @@
|
||||
/* Decode header for bpfbf_ebpfle.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef BPFBF_EBPFLE_DECODE_H
|
||||
#define BPFBF_EBPFLE_DECODE_H
|
||||
|
||||
extern const IDESC *bpfbf_ebpfle_decode (SIM_CPU *, IADDR,
|
||||
CGEN_INSN_WORD,
|
||||
ARGBUF *);
|
||||
extern void bpfbf_ebpfle_init_idesc_table (SIM_CPU *);
|
||||
extern void bpfbf_ebpfle_sem_init_idesc_table (SIM_CPU *);
|
||||
extern void bpfbf_ebpfle_semf_init_idesc_table (SIM_CPU *);
|
||||
|
||||
/* Enum declaration for instructions in cpu family bpfbf. */
|
||||
typedef enum bpfbf_ebpfle_insn_type {
|
||||
BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_AFTER, BPFBF_EBPFLE_INSN_X_BEFORE, BPFBF_EBPFLE_INSN_X_CTI_CHAIN
|
||||
, BPFBF_EBPFLE_INSN_X_CHAIN, BPFBF_EBPFLE_INSN_X_BEGIN, BPFBF_EBPFLE_INSN_ADDILE, BPFBF_EBPFLE_INSN_ADDRLE
|
||||
, BPFBF_EBPFLE_INSN_ADD32ILE, BPFBF_EBPFLE_INSN_ADD32RLE, BPFBF_EBPFLE_INSN_SUBILE, BPFBF_EBPFLE_INSN_SUBRLE
|
||||
, BPFBF_EBPFLE_INSN_SUB32ILE, BPFBF_EBPFLE_INSN_SUB32RLE, BPFBF_EBPFLE_INSN_MULILE, BPFBF_EBPFLE_INSN_MULRLE
|
||||
, BPFBF_EBPFLE_INSN_MUL32ILE, BPFBF_EBPFLE_INSN_MUL32RLE, BPFBF_EBPFLE_INSN_DIVILE, BPFBF_EBPFLE_INSN_DIVRLE
|
||||
, BPFBF_EBPFLE_INSN_DIV32ILE, BPFBF_EBPFLE_INSN_DIV32RLE, BPFBF_EBPFLE_INSN_ORILE, BPFBF_EBPFLE_INSN_ORRLE
|
||||
, BPFBF_EBPFLE_INSN_OR32ILE, BPFBF_EBPFLE_INSN_OR32RLE, BPFBF_EBPFLE_INSN_ANDILE, BPFBF_EBPFLE_INSN_ANDRLE
|
||||
, BPFBF_EBPFLE_INSN_AND32ILE, BPFBF_EBPFLE_INSN_AND32RLE, BPFBF_EBPFLE_INSN_LSHILE, BPFBF_EBPFLE_INSN_LSHRLE
|
||||
, BPFBF_EBPFLE_INSN_LSH32ILE, BPFBF_EBPFLE_INSN_LSH32RLE, BPFBF_EBPFLE_INSN_RSHILE, BPFBF_EBPFLE_INSN_RSHRLE
|
||||
, BPFBF_EBPFLE_INSN_RSH32ILE, BPFBF_EBPFLE_INSN_RSH32RLE, BPFBF_EBPFLE_INSN_MODILE, BPFBF_EBPFLE_INSN_MODRLE
|
||||
, BPFBF_EBPFLE_INSN_MOD32ILE, BPFBF_EBPFLE_INSN_MOD32RLE, BPFBF_EBPFLE_INSN_XORILE, BPFBF_EBPFLE_INSN_XORRLE
|
||||
, BPFBF_EBPFLE_INSN_XOR32ILE, BPFBF_EBPFLE_INSN_XOR32RLE, BPFBF_EBPFLE_INSN_ARSHILE, BPFBF_EBPFLE_INSN_ARSHRLE
|
||||
, BPFBF_EBPFLE_INSN_ARSH32ILE, BPFBF_EBPFLE_INSN_ARSH32RLE, BPFBF_EBPFLE_INSN_NEGLE, BPFBF_EBPFLE_INSN_NEG32LE
|
||||
, BPFBF_EBPFLE_INSN_MOVILE, BPFBF_EBPFLE_INSN_MOVRLE, BPFBF_EBPFLE_INSN_MOV32ILE, BPFBF_EBPFLE_INSN_MOV32RLE
|
||||
, BPFBF_EBPFLE_INSN_ENDLELE, BPFBF_EBPFLE_INSN_ENDBELE, BPFBF_EBPFLE_INSN_LDDWLE, BPFBF_EBPFLE_INSN_LDABSW
|
||||
, BPFBF_EBPFLE_INSN_LDABSH, BPFBF_EBPFLE_INSN_LDABSB, BPFBF_EBPFLE_INSN_LDABSDW, BPFBF_EBPFLE_INSN_LDINDWLE
|
||||
, BPFBF_EBPFLE_INSN_LDINDHLE, BPFBF_EBPFLE_INSN_LDINDBLE, BPFBF_EBPFLE_INSN_LDINDDWLE, BPFBF_EBPFLE_INSN_LDXWLE
|
||||
, BPFBF_EBPFLE_INSN_LDXHLE, BPFBF_EBPFLE_INSN_LDXBLE, BPFBF_EBPFLE_INSN_LDXDWLE, BPFBF_EBPFLE_INSN_STXWLE
|
||||
, BPFBF_EBPFLE_INSN_STXHLE, BPFBF_EBPFLE_INSN_STXBLE, BPFBF_EBPFLE_INSN_STXDWLE, BPFBF_EBPFLE_INSN_STBLE
|
||||
, BPFBF_EBPFLE_INSN_STHLE, BPFBF_EBPFLE_INSN_STWLE, BPFBF_EBPFLE_INSN_STDWLE, BPFBF_EBPFLE_INSN_JEQILE
|
||||
, BPFBF_EBPFLE_INSN_JEQRLE, BPFBF_EBPFLE_INSN_JEQ32ILE, BPFBF_EBPFLE_INSN_JEQ32RLE, BPFBF_EBPFLE_INSN_JGTILE
|
||||
, BPFBF_EBPFLE_INSN_JGTRLE, BPFBF_EBPFLE_INSN_JGT32ILE, BPFBF_EBPFLE_INSN_JGT32RLE, BPFBF_EBPFLE_INSN_JGEILE
|
||||
, BPFBF_EBPFLE_INSN_JGERLE, BPFBF_EBPFLE_INSN_JGE32ILE, BPFBF_EBPFLE_INSN_JGE32RLE, BPFBF_EBPFLE_INSN_JLTILE
|
||||
, BPFBF_EBPFLE_INSN_JLTRLE, BPFBF_EBPFLE_INSN_JLT32ILE, BPFBF_EBPFLE_INSN_JLT32RLE, BPFBF_EBPFLE_INSN_JLEILE
|
||||
, BPFBF_EBPFLE_INSN_JLERLE, BPFBF_EBPFLE_INSN_JLE32ILE, BPFBF_EBPFLE_INSN_JLE32RLE, BPFBF_EBPFLE_INSN_JSETILE
|
||||
, BPFBF_EBPFLE_INSN_JSETRLE, BPFBF_EBPFLE_INSN_JSET32ILE, BPFBF_EBPFLE_INSN_JSET32RLE, BPFBF_EBPFLE_INSN_JNEILE
|
||||
, BPFBF_EBPFLE_INSN_JNERLE, BPFBF_EBPFLE_INSN_JNE32ILE, BPFBF_EBPFLE_INSN_JNE32RLE, BPFBF_EBPFLE_INSN_JSGTILE
|
||||
, BPFBF_EBPFLE_INSN_JSGTRLE, BPFBF_EBPFLE_INSN_JSGT32ILE, BPFBF_EBPFLE_INSN_JSGT32RLE, BPFBF_EBPFLE_INSN_JSGEILE
|
||||
, BPFBF_EBPFLE_INSN_JSGERLE, BPFBF_EBPFLE_INSN_JSGE32ILE, BPFBF_EBPFLE_INSN_JSGE32RLE, BPFBF_EBPFLE_INSN_JSLTILE
|
||||
, BPFBF_EBPFLE_INSN_JSLTRLE, BPFBF_EBPFLE_INSN_JSLT32ILE, BPFBF_EBPFLE_INSN_JSLT32RLE, BPFBF_EBPFLE_INSN_JSLEILE
|
||||
, BPFBF_EBPFLE_INSN_JSLERLE, BPFBF_EBPFLE_INSN_JSLE32ILE, BPFBF_EBPFLE_INSN_JSLE32RLE, BPFBF_EBPFLE_INSN_CALLLE
|
||||
, BPFBF_EBPFLE_INSN_JA, BPFBF_EBPFLE_INSN_EXIT, BPFBF_EBPFLE_INSN_XADDDWLE, BPFBF_EBPFLE_INSN_XADDWLE
|
||||
, BPFBF_EBPFLE_INSN_BRKPT, BPFBF_EBPFLE_INSN__MAX
|
||||
} BPFBF_EBPFLE_INSN_TYPE;
|
||||
|
||||
/* Enum declaration for semantic formats in cpu family bpfbf. */
|
||||
typedef enum bpfbf_ebpfle_sfmt_type {
|
||||
BPFBF_EBPFLE_SFMT_EMPTY, BPFBF_EBPFLE_SFMT_ADDILE, BPFBF_EBPFLE_SFMT_ADDRLE, BPFBF_EBPFLE_SFMT_NEGLE
|
||||
, BPFBF_EBPFLE_SFMT_MOVILE, BPFBF_EBPFLE_SFMT_MOVRLE, BPFBF_EBPFLE_SFMT_ENDLELE, BPFBF_EBPFLE_SFMT_LDDWLE
|
||||
, BPFBF_EBPFLE_SFMT_LDABSW, BPFBF_EBPFLE_SFMT_LDABSH, BPFBF_EBPFLE_SFMT_LDABSB, BPFBF_EBPFLE_SFMT_LDABSDW
|
||||
, BPFBF_EBPFLE_SFMT_LDINDWLE, BPFBF_EBPFLE_SFMT_LDINDHLE, BPFBF_EBPFLE_SFMT_LDINDBLE, BPFBF_EBPFLE_SFMT_LDINDDWLE
|
||||
, BPFBF_EBPFLE_SFMT_LDXWLE, BPFBF_EBPFLE_SFMT_LDXHLE, BPFBF_EBPFLE_SFMT_LDXBLE, BPFBF_EBPFLE_SFMT_LDXDWLE
|
||||
, BPFBF_EBPFLE_SFMT_STXWLE, BPFBF_EBPFLE_SFMT_STXHLE, BPFBF_EBPFLE_SFMT_STXBLE, BPFBF_EBPFLE_SFMT_STXDWLE
|
||||
, BPFBF_EBPFLE_SFMT_STBLE, BPFBF_EBPFLE_SFMT_STHLE, BPFBF_EBPFLE_SFMT_STWLE, BPFBF_EBPFLE_SFMT_STDWLE
|
||||
, BPFBF_EBPFLE_SFMT_JEQILE, BPFBF_EBPFLE_SFMT_JEQRLE, BPFBF_EBPFLE_SFMT_CALLLE, BPFBF_EBPFLE_SFMT_JA
|
||||
, BPFBF_EBPFLE_SFMT_EXIT, BPFBF_EBPFLE_SFMT_XADDDWLE, BPFBF_EBPFLE_SFMT_XADDWLE
|
||||
} BPFBF_EBPFLE_SFMT_TYPE;
|
||||
|
||||
/* Function unit handlers (user written). */
|
||||
|
||||
extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
|
||||
|
||||
/* Profiling before/after handlers (user written) */
|
||||
|
||||
extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
|
||||
extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
|
||||
|
||||
#endif /* BPFBF_EBPFLE_DECODE_H */
|
||||
@@ -1,37 +0,0 @@
|
||||
/* Decode declarations.
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
Contributed by Oracle, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* Include declarations for eBPF LE and eBPF BE ISAs. */
|
||||
|
||||
#ifndef DECODE_H
|
||||
#define DECODE_H
|
||||
|
||||
#undef WITH_PROFILE_MODEL_P
|
||||
|
||||
#ifdef WANT_ISA_EBPFLE
|
||||
#include "decode-le.h"
|
||||
#include "defs-le.h"
|
||||
#endif /* WANT_ISA_EBPFLE */
|
||||
|
||||
#ifdef WANT_ISA_EBPFBE
|
||||
#include "decode-be.h"
|
||||
#include "defs-be.h"
|
||||
#endif /* WANT_ISA_EBPFBE */
|
||||
|
||||
#endif /* DECODE_H */
|
||||
@@ -1,383 +0,0 @@
|
||||
/* ISA definitions header for ebpfbe.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef DEFS_BPFBF_EBPFBE_H
|
||||
#define DEFS_BPFBF_EBPFBE_H
|
||||
|
||||
/* Instruction argument buffer. */
|
||||
|
||||
union sem_fields {
|
||||
struct { /* no operands */
|
||||
int empty;
|
||||
} sfmt_empty;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_srcbe;
|
||||
} sfmt_ldindwbe;
|
||||
struct { /* */
|
||||
DI f_imm64;
|
||||
UINT f_dstbe;
|
||||
} sfmt_lddwbe;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_dstbe;
|
||||
HI f_offset16;
|
||||
} sfmt_stbbe;
|
||||
struct { /* */
|
||||
UINT f_dstbe;
|
||||
UINT f_srcbe;
|
||||
HI f_offset16;
|
||||
} sfmt_ldxwbe;
|
||||
#if WITH_SCACHE_PBB
|
||||
/* Writeback handler. */
|
||||
struct {
|
||||
/* Pointer to argbuf entry for insn whose results need writing back. */
|
||||
const struct argbuf *abuf;
|
||||
} write;
|
||||
/* x-before handler */
|
||||
struct {
|
||||
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
|
||||
int first_p;
|
||||
} before;
|
||||
/* x-after handler */
|
||||
struct {
|
||||
int empty;
|
||||
} after;
|
||||
/* This entry is used to terminate each pbb. */
|
||||
struct {
|
||||
/* Number of insns in pbb. */
|
||||
int insn_count;
|
||||
/* Next pbb to execute. */
|
||||
SCACHE *next;
|
||||
SCACHE *branch_target;
|
||||
} chain;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The ARGBUF struct. */
|
||||
struct argbuf {
|
||||
/* These are the baseclass definitions. */
|
||||
IADDR addr;
|
||||
const IDESC *idesc;
|
||||
char trace_p;
|
||||
char profile_p;
|
||||
/* ??? Temporary hack for skip insns. */
|
||||
char skip_count;
|
||||
char unused;
|
||||
/* cpu specific data follows */
|
||||
union sem semantic;
|
||||
int written;
|
||||
union sem_fields fields;
|
||||
};
|
||||
|
||||
/* A cached insn.
|
||||
|
||||
??? SCACHE used to contain more than just argbuf. We could delete the
|
||||
type entirely and always just use ARGBUF, but for future concerns and as
|
||||
a level of abstraction it is left in. */
|
||||
|
||||
struct scache {
|
||||
struct argbuf argbuf;
|
||||
};
|
||||
|
||||
/* Macros to simplify extraction, reading and semantic code.
|
||||
These define and assign the local vars that contain the insn's fields. */
|
||||
|
||||
#define EXTRACT_IFMT_EMPTY_VARS \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EMPTY_CODE \
|
||||
length = 0; \
|
||||
|
||||
#define EXTRACT_IFMT_ADDIBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDIBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ADDRBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDRBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_NEGBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_NEGBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ENDLEBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ENDLEBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDDWBE_VARS \
|
||||
UINT f_imm64_a; \
|
||||
UINT f_imm64_b; \
|
||||
UINT f_imm64_c; \
|
||||
DI f_imm64; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
/* Contents of trailing part of insn. */ \
|
||||
UINT word_1; \
|
||||
UINT word_2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDDWBE_CODE \
|
||||
length = 16; \
|
||||
word_1 = GETIMEMUSI (current_cpu, pc + 8); \
|
||||
word_2 = GETIMEMUSI (current_cpu, pc + 12); \
|
||||
f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
|
||||
f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \
|
||||
{\
|
||||
f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\
|
||||
}\
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDABSW_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDABSW_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDINDWBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDINDWBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDXWBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDXWBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_STBBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_STBBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQIBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQIBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQRBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_dstbe; \
|
||||
UINT f_op_code; \
|
||||
UINT f_srcbe; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQRBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_CALLBE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_CALLBE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JA_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JA_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_EXIT_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EXIT_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#endif /* DEFS_BPFBF_EBPFBE_H */
|
||||
@@ -1,383 +0,0 @@
|
||||
/* ISA definitions header for ebpfle.
|
||||
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
|
||||
Copyright (C) 1996-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
It is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef DEFS_BPFBF_EBPFLE_H
|
||||
#define DEFS_BPFBF_EBPFLE_H
|
||||
|
||||
/* Instruction argument buffer. */
|
||||
|
||||
union sem_fields {
|
||||
struct { /* no operands */
|
||||
int empty;
|
||||
} sfmt_empty;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_srcle;
|
||||
} sfmt_ldindwle;
|
||||
struct { /* */
|
||||
DI f_imm64;
|
||||
UINT f_dstle;
|
||||
} sfmt_lddwle;
|
||||
struct { /* */
|
||||
INT f_imm32;
|
||||
UINT f_dstle;
|
||||
HI f_offset16;
|
||||
} sfmt_stble;
|
||||
struct { /* */
|
||||
UINT f_dstle;
|
||||
UINT f_srcle;
|
||||
HI f_offset16;
|
||||
} sfmt_ldxwle;
|
||||
#if WITH_SCACHE_PBB
|
||||
/* Writeback handler. */
|
||||
struct {
|
||||
/* Pointer to argbuf entry for insn whose results need writing back. */
|
||||
const struct argbuf *abuf;
|
||||
} write;
|
||||
/* x-before handler */
|
||||
struct {
|
||||
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
|
||||
int first_p;
|
||||
} before;
|
||||
/* x-after handler */
|
||||
struct {
|
||||
int empty;
|
||||
} after;
|
||||
/* This entry is used to terminate each pbb. */
|
||||
struct {
|
||||
/* Number of insns in pbb. */
|
||||
int insn_count;
|
||||
/* Next pbb to execute. */
|
||||
SCACHE *next;
|
||||
SCACHE *branch_target;
|
||||
} chain;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The ARGBUF struct. */
|
||||
struct argbuf {
|
||||
/* These are the baseclass definitions. */
|
||||
IADDR addr;
|
||||
const IDESC *idesc;
|
||||
char trace_p;
|
||||
char profile_p;
|
||||
/* ??? Temporary hack for skip insns. */
|
||||
char skip_count;
|
||||
char unused;
|
||||
/* cpu specific data follows */
|
||||
union sem semantic;
|
||||
int written;
|
||||
union sem_fields fields;
|
||||
};
|
||||
|
||||
/* A cached insn.
|
||||
|
||||
??? SCACHE used to contain more than just argbuf. We could delete the
|
||||
type entirely and always just use ARGBUF, but for future concerns and as
|
||||
a level of abstraction it is left in. */
|
||||
|
||||
struct scache {
|
||||
struct argbuf argbuf;
|
||||
};
|
||||
|
||||
/* Macros to simplify extraction, reading and semantic code.
|
||||
These define and assign the local vars that contain the insn's fields. */
|
||||
|
||||
#define EXTRACT_IFMT_EMPTY_VARS \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EMPTY_CODE \
|
||||
length = 0; \
|
||||
|
||||
#define EXTRACT_IFMT_ADDILE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDILE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ADDRLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDRLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_NEGLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_NEGLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_ENDLELE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ENDLELE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDDWLE_VARS \
|
||||
UINT f_imm64_a; \
|
||||
UINT f_imm64_b; \
|
||||
UINT f_imm64_c; \
|
||||
DI f_imm64; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
/* Contents of trailing part of insn. */ \
|
||||
UINT word_1; \
|
||||
UINT word_2; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDDWLE_CODE \
|
||||
length = 16; \
|
||||
word_1 = GETIMEMUSI (current_cpu, pc + 8); \
|
||||
word_2 = GETIMEMUSI (current_cpu, pc + 12); \
|
||||
f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
|
||||
f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \
|
||||
{\
|
||||
f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\
|
||||
}\
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDABSW_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDABSW_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDINDWLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDINDWLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_LDXWLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDXWLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_STBLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_mode; \
|
||||
UINT f_op_size; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_STBLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
|
||||
f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQILE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQILE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JEQRLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_srcle; \
|
||||
UINT f_op_code; \
|
||||
UINT f_dstle; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JEQRLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_CALLLE_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_CALLLE_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_JA_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_JA_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#define EXTRACT_IFMT_EXIT_VARS \
|
||||
INT f_imm32; \
|
||||
HI f_offset16; \
|
||||
UINT f_regs; \
|
||||
UINT f_op_code; \
|
||||
UINT f_op_src; \
|
||||
UINT f_op_class; \
|
||||
unsigned int length;
|
||||
#define EXTRACT_IFMT_EXIT_CODE \
|
||||
length = 8; \
|
||||
f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
|
||||
f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
|
||||
f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
|
||||
f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
|
||||
f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
|
||||
f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
|
||||
|
||||
#endif /* DEFS_BPFBF_EBPFLE_H */
|
||||
@@ -1,23 +0,0 @@
|
||||
/* Engine declarations.
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
Contributed by Oracle, Inc.
|
||||
|
||||
This file is part of the GNU simulators.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* Include declarations for eBPF LE and eBPF BE ISAs. */
|
||||
|
||||
#include "eng-le.h"
|
||||
#include "eng-be.h"
|
||||
+5
-103
@@ -1,6 +1,8 @@
|
||||
## See sim/Makefile.am
|
||||
##
|
||||
## Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
## Contributed by Oracle Inc.
|
||||
##
|
||||
## Copyright (C) 2023 Free Software Foundation, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
@@ -15,40 +17,15 @@
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
AM_CPPFLAGS_%C% = -DWITH_TARGET_WORD_BITSIZE=64
|
||||
AM_CPPFLAGS_%C%_mloop_le.o = -DWANT_ISA_EBPFLE
|
||||
AM_CPPFLAGS_%C%_mloop_be.o = -DWANT_ISA_EBPFBE
|
||||
AM_CPPFLAGS_%C%_decode_le.o = -DWANT_ISA_EBPFLE
|
||||
AM_CPPFLAGS_%C%_decode_be.o = -DWANT_ISA_EBPFBE
|
||||
AM_CPPFLAGS_%C%_sem_le.o = -DWANT_ISA_EBPFLE
|
||||
AM_CPPFLAGS_%C%_sem_be.o = -DWANT_ISA_EBPFBE
|
||||
|
||||
nodist_%C%_libsim_a_SOURCES = \
|
||||
%D%/modules.c
|
||||
%C%_libsim_a_SOURCES = \
|
||||
$(common_libcommon_a_SOURCES)
|
||||
%C%_libsim_a_LIBADD = \
|
||||
%D%/bpf-sim.o \
|
||||
$(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \
|
||||
$(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \
|
||||
\
|
||||
%D%/cgen-run.o \
|
||||
%D%/cgen-scache.o \
|
||||
%D%/cgen-trace.o \
|
||||
%D%/cgen-utils.o \
|
||||
\
|
||||
%D%/arch.o \
|
||||
%D%/cpu.o \
|
||||
%D%/decode-le.o \
|
||||
%D%/decode-be.o \
|
||||
%D%/sem-le.o \
|
||||
%D%/sem-be.o \
|
||||
%D%/mloop-le.o \
|
||||
%D%/mloop-be.o \
|
||||
\
|
||||
%D%/bpf.o \
|
||||
%D%/bpf-helpers.o \
|
||||
%D%/sim-if.o \
|
||||
%D%/traps.o
|
||||
%D%/sim-resume.o
|
||||
$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h
|
||||
|
||||
noinst_LIBRARIES += %D%/libsim.a
|
||||
@@ -66,78 +43,3 @@ noinst_LIBRARIES += %D%/libsim.a
|
||||
$(SIM_COMMON_LIBS)
|
||||
|
||||
noinst_PROGRAMS += %D%/run
|
||||
|
||||
## List all generated headers to help Automake dependency tracking.
|
||||
BUILT_SOURCES += \
|
||||
%D%/eng-le.h \
|
||||
%D%/eng-be.h
|
||||
%C%_BUILD_OUTPUTS = \
|
||||
%D%/mloop-le.c \
|
||||
%D%/stamp-mloop-le \
|
||||
%D%/mloop-be.c \
|
||||
%D%/stamp-mloop-be
|
||||
|
||||
## Generating modules.c requires all sources to scan.
|
||||
%D%/modules.c: | $(%C%_BUILD_OUTPUTS)
|
||||
|
||||
%D%/mloop-le.c %D%/eng-le.h: %D%/stamp-mloop-le ; @true
|
||||
%D%/stamp-mloop-le: $(srccom)/genmloop.sh %D%/mloop.in
|
||||
$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
|
||||
-mono -scache -prefix bpfbf_ebpfle -cpu bpfbf \
|
||||
-infile $(srcdir)/%D%/mloop.in \
|
||||
-outfile-prefix %D%/ -outfile-suffix -le
|
||||
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/eng-le.hin %D%/eng-le.h
|
||||
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop-le.cin %D%/mloop-le.c
|
||||
$(AM_V_at)touch $@
|
||||
|
||||
%D%/mloop-be.c %D%/eng-be.h: %D%/stamp-mloop-be ; @true
|
||||
%D%/stamp-mloop-be: $(srccom)/genmloop.sh %D%/mloop.in
|
||||
$(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
|
||||
-mono -scache -prefix bpfbf_ebpfbe -cpu bpfbf \
|
||||
-infile $(srcdir)/%D%/mloop.in \
|
||||
-outfile-prefix %D%/ -outfile-suffix -be
|
||||
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/eng-be.hin %D%/eng-be.h
|
||||
$(AM_V_at)$(SHELL) $(srcroot)/move-if-change %D%/mloop-be.cin %D%/mloop-be.c
|
||||
$(AM_V_at)touch $@
|
||||
|
||||
MOSTLYCLEANFILES += $(%C%_BUILD_OUTPUTS)
|
||||
|
||||
## Target that triggers all cgen targets that works when --disable-cgen-maint.
|
||||
%D%/cgen: %D%/cgen-arch %D%/cgen-cpu %D%/cgen-defs-le %D%/cgen-defs-be %D%/cgen-decode-le %D%/cgen-decode-be
|
||||
|
||||
%D%/cgen-arch:
|
||||
$(AM_V_GEN)mach=bpf cpu=bpfbf FLAGS="with-scache"; $(CGEN_GEN_ARCH)
|
||||
%D%/arch.h %D%/arch.c %D%/cpuall.h: @CGEN_MAINT@ %D%/cgen-arch
|
||||
|
||||
%D%/cgen-cpu:
|
||||
$(AM_V_GEN)isa=ebpfle,ebpfbe cpu=bpfbf mach=bpf FLAGS="with-multiple-isa with-scache"; $(CGEN_GEN_CPU)
|
||||
$(AM_V_at)rm -f $(srcdir)/%D%/model.c
|
||||
%D%/cpu.h %D%/cpu.c %D%/model.c: @CGEN_MAINT@ %D%/cgen-cpu
|
||||
|
||||
## We need to generate a group of files per ISA.
|
||||
## For eBPF little-endian:
|
||||
## defs-le.h
|
||||
## sem-le.c, decode-le.c, decode-le.h
|
||||
## $(objdir)/mloop-le.c $(objdir)/eng-le.h
|
||||
## For eBPF big-endian:
|
||||
## defs-be.h
|
||||
## sem-be.c, decode-be.c, decode-be.h
|
||||
## $(objdir)/mloop-be.c $(objdir)/eng-le.h
|
||||
##
|
||||
## The rules below take care of that.
|
||||
|
||||
%D%/cgen-defs-le:
|
||||
$(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le"; $(CGEN_GEN_DEFS)
|
||||
%D%/defs-le.h: @CGEN_MAINT@ %D%/cgen-defs-le
|
||||
|
||||
%D%/cgen-defs-be:
|
||||
$(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be"; $(CGEN_GEN_DEFS)
|
||||
%D%/defs-be.h: @CGEN_MAINT@ %D%/cgen-defs-be
|
||||
|
||||
%D%/cgen-decode-le:
|
||||
$(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
|
||||
%D%/sem-le.c %D%/decode-le.c %D%/decode-le.h: @CGEN_MAINT@ %D%/cgen-decode-vle
|
||||
|
||||
%D%/cgen-decode-be:
|
||||
$(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
|
||||
%D%/sem-be.c %D%/decode-be.c %D%/decode-be.h: @CGEN_MAINT@ %D%/cgen-decode-be
|
||||
|
||||
@@ -1,168 +0,0 @@
|
||||
# Simulator main loop for eBPF. -*- C -*-
|
||||
#
|
||||
# Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is part of the GNU Simulators.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
# Syntax:
|
||||
# /bin/sh mloop.in command
|
||||
#
|
||||
# Command is one of:
|
||||
#
|
||||
# init
|
||||
# support
|
||||
# extract-{simple,scache,pbb}
|
||||
# {full,fast}-exec-{simple,scache,pbb}
|
||||
#
|
||||
# A target need only provide a "full" version of one of simple,scache,pbb.
|
||||
# If the target wants it can also provide a fast version of same, or if
|
||||
# the slow (full featured) version is `simple', then the fast version can be
|
||||
# one of scache/pbb.
|
||||
# A target can't provide more than this.
|
||||
# However for illustration's sake this file provides examples of all.
|
||||
|
||||
# ??? After a few more ports are done, revisit.
|
||||
# Will eventually need to machine generate a lot of this.
|
||||
|
||||
case "x$1" in
|
||||
|
||||
xsupport)
|
||||
|
||||
cat <<EOF
|
||||
|
||||
static INLINE const IDESC *
|
||||
extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_WORD insn,
|
||||
ARGBUF *abuf, int fast_p)
|
||||
{
|
||||
const IDESC *id = @prefix@_decode (current_cpu, pc, insn, abuf);
|
||||
@prefix@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
|
||||
if (!fast_p)
|
||||
{
|
||||
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
|
||||
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
|
||||
@prefix@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
|
||||
}
|
||||
return id;
|
||||
}
|
||||
|
||||
static INLINE SEM_PC
|
||||
execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
|
||||
{
|
||||
SEM_PC vpc;
|
||||
|
||||
if (fast_p)
|
||||
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
|
||||
else
|
||||
{
|
||||
ARGBUF *abuf = &sc->argbuf;
|
||||
const IDESC *idesc = abuf->idesc;
|
||||
const CGEN_INSN *idata = idesc->idata;
|
||||
int virtual_p = 0;
|
||||
|
||||
if (! virtual_p)
|
||||
{
|
||||
/* FIXME: call x-before */
|
||||
if (ARGBUF_PROFILE_P (abuf))
|
||||
PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
|
||||
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
|
||||
if (PROFILE_MODEL_P (current_cpu)
|
||||
&& ARGBUF_PROFILE_P (abuf))
|
||||
@cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
|
||||
CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
|
||||
CGEN_TRACE_INSN (current_cpu, idata,
|
||||
(const struct argbuf *) abuf, abuf->addr);
|
||||
}
|
||||
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
|
||||
if (! virtual_p)
|
||||
{
|
||||
/* FIXME: call x-after */
|
||||
if (PROFILE_MODEL_P (current_cpu)
|
||||
&& ARGBUF_PROFILE_P (abuf))
|
||||
{
|
||||
int cycles;
|
||||
|
||||
cycles = (*idesc->timing->model_fn) (current_cpu, sc);
|
||||
@cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
|
||||
}
|
||||
CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
|
||||
}
|
||||
}
|
||||
|
||||
return vpc;
|
||||
}
|
||||
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xinit)
|
||||
|
||||
# Nothing needed.
|
||||
|
||||
;;
|
||||
|
||||
xextract-scache)
|
||||
|
||||
cat <<EOF
|
||||
{
|
||||
|
||||
UDI insn = GETIMEMUDI (current_cpu, vpc);
|
||||
|
||||
if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
|
||||
{
|
||||
UHI off16;
|
||||
USI imm32;
|
||||
|
||||
/* eBPF instructions are little-endian, but GETIMEMUDI reads according
|
||||
to target byte order. Swap to little-endian. */
|
||||
insn = SWAP_8 (insn);
|
||||
|
||||
/* But, the imm32 and offset16 fields within instructions follow target
|
||||
byte order. Swap those fields back. */
|
||||
off16 = (UHI) ((insn & 0x00000000ffff0000) >> 16);
|
||||
imm32 = (USI) ((insn & 0xffffffff00000000) >> 32);
|
||||
off16 = SWAP_2 (off16);
|
||||
imm32 = SWAP_4 (imm32);
|
||||
|
||||
insn = (((UDI) imm32) << 32) | (((UDI) off16) << 16) | (insn & 0xffff);
|
||||
}
|
||||
|
||||
extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
|
||||
|
||||
//XXX SEM_SKIP_COMPILE (current_cpu, sc, 1);
|
||||
}
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
xfull-exec-* | xfast-exec-*)
|
||||
|
||||
# Inputs: current_cpu, vpc, sc, FAST_P
|
||||
# Outputs: vpc
|
||||
# vpc is the virtual program counter.
|
||||
|
||||
cat <<EOF
|
||||
vpc = execute (current_cpu, sc, FAST_P);
|
||||
EOF
|
||||
|
||||
;;
|
||||
|
||||
*)
|
||||
echo "Invalid argument to mainloop.in: $1" >&2
|
||||
exit 1
|
||||
;;
|
||||
|
||||
esac
|
||||
-3207
File diff suppressed because it is too large
Load Diff
-3207
File diff suppressed because it is too large
Load Diff
@@ -1,228 +0,0 @@
|
||||
/* Main simulator entry points specific to the eBPF.
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* This must come before any other includes. */
|
||||
#include "defs.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "sim/callback.h"
|
||||
#include "sim-main.h"
|
||||
#include "sim-options.h"
|
||||
#include "libiberty.h"
|
||||
#include "bfd.h"
|
||||
|
||||
/* Globals. */
|
||||
|
||||
/* String with the name of the section containing the BPF program to
|
||||
run. */
|
||||
static char *bpf_program_section = NULL;
|
||||
|
||||
extern uint64_t skb_data_offset;
|
||||
|
||||
|
||||
/* Handle BPF-specific options. */
|
||||
|
||||
static SIM_RC bpf_option_handler (SIM_DESC, sim_cpu *, int, char *, int);
|
||||
|
||||
typedef enum
|
||||
{
|
||||
OPTION_BPF_SET_PROGRAM = OPTION_START,
|
||||
OPTION_BPF_LIST_PROGRAMS,
|
||||
OPTION_BPF_VERIFY_PROGRAM,
|
||||
OPTION_BPF_SKB_DATA_OFFSET,
|
||||
} BPF_OPTION;
|
||||
|
||||
static const OPTION bpf_options[] =
|
||||
{
|
||||
{ {"bpf-set-program", required_argument, NULL, OPTION_BPF_SET_PROGRAM},
|
||||
'\0', "SECTION_NAME", "Set the entry point",
|
||||
bpf_option_handler },
|
||||
{ {"bpf-list-programs", no_argument, NULL, OPTION_BPF_LIST_PROGRAMS},
|
||||
'\0', "", "List loaded bpf programs",
|
||||
bpf_option_handler },
|
||||
{ {"bpf-verify-program", required_argument, NULL, OPTION_BPF_VERIFY_PROGRAM},
|
||||
'\0', "PROGRAM", "Run the verifier on the given BPF program",
|
||||
bpf_option_handler },
|
||||
{ {"skb-data-offset", required_argument, NULL, OPTION_BPF_SKB_DATA_OFFSET},
|
||||
'\0', "OFFSET", "Configure offsetof(struct sk_buff, data)",
|
||||
bpf_option_handler },
|
||||
|
||||
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
|
||||
};
|
||||
|
||||
static SIM_RC
|
||||
bpf_option_handler (SIM_DESC sd, sim_cpu *cpu ATTRIBUTE_UNUSED, int opt,
|
||||
char *arg, int is_command ATTRIBUTE_UNUSED)
|
||||
{
|
||||
switch ((BPF_OPTION) opt)
|
||||
{
|
||||
case OPTION_BPF_VERIFY_PROGRAM:
|
||||
/* XXX call the verifier. */
|
||||
sim_io_printf (sd, "Verifying BPF program %s...\n", arg);
|
||||
break;
|
||||
|
||||
case OPTION_BPF_LIST_PROGRAMS:
|
||||
/* XXX list programs. */
|
||||
sim_io_printf (sd, "BPF programs available:\n");
|
||||
break;
|
||||
|
||||
case OPTION_BPF_SET_PROGRAM:
|
||||
/* XXX: check that the section exists and tell the user about a
|
||||
new start_address. */
|
||||
bpf_program_section = xstrdup (arg);
|
||||
break;
|
||||
|
||||
case OPTION_BPF_SKB_DATA_OFFSET:
|
||||
skb_data_offset = strtoul (arg, NULL, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
sim_io_eprintf (sd, "Unknown option `%s'\n", arg);
|
||||
return SIM_RC_FAIL;
|
||||
}
|
||||
|
||||
return SIM_RC_OK;
|
||||
}
|
||||
|
||||
/* Like sim_state_free, but free the cpu buffers as well. */
|
||||
|
||||
static void
|
||||
bpf_free_state (SIM_DESC sd)
|
||||
{
|
||||
if (STATE_MODULES (sd) != NULL)
|
||||
sim_module_uninstall (sd);
|
||||
|
||||
sim_cpu_free_all (sd);
|
||||
sim_state_free (sd);
|
||||
}
|
||||
|
||||
extern const SIM_MACH * const bpf_sim_machs[];
|
||||
|
||||
/* Create an instance of the simulator. */
|
||||
|
||||
SIM_DESC
|
||||
sim_open (SIM_OPEN_KIND kind,
|
||||
host_callback *callback,
|
||||
struct bfd *abfd,
|
||||
char * const *argv)
|
||||
{
|
||||
/* XXX Analyze the program, and collect per-function information
|
||||
like the kernel verifier does. The implementation of the CALL
|
||||
instruction will need that information, to update %fp. */
|
||||
|
||||
SIM_DESC sd = sim_state_alloc (kind, callback);
|
||||
|
||||
/* Set default options before parsing user options. */
|
||||
STATE_MACHS (sd) = bpf_sim_machs;
|
||||
STATE_MODEL_NAME (sd) = "bpf-def";
|
||||
|
||||
if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct bpf_sim_cpu)) != SIM_RC_OK)
|
||||
goto error;
|
||||
|
||||
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
|
||||
goto error;
|
||||
|
||||
/* Add the BPF-specific option list to the simulator. */
|
||||
if (sim_add_option_table (sd, NULL, bpf_options) != SIM_RC_OK)
|
||||
{
|
||||
bpf_free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (sim_parse_args (sd, argv) != SIM_RC_OK)
|
||||
goto error;
|
||||
|
||||
if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
|
||||
goto error;
|
||||
|
||||
if (sim_config (sd) != SIM_RC_OK)
|
||||
goto error;
|
||||
|
||||
if (sim_post_argv_init (sd) != SIM_RC_OK)
|
||||
goto error;
|
||||
|
||||
/* ... */
|
||||
|
||||
/* Initialize the CPU descriptors and the disassemble in the cpu
|
||||
descriptor table entries. */
|
||||
{
|
||||
int i;
|
||||
CGEN_CPU_DESC cd = bpf_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
|
||||
CGEN_ENDIAN_LITTLE);
|
||||
|
||||
/* We have one cpu per installed program! MAX_NR_PROCESSORS is an
|
||||
arbitrary upper limit. XXX where is it defined? */
|
||||
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
|
||||
{
|
||||
SIM_CPU *cpu = STATE_CPU (sd, i);
|
||||
|
||||
CPU_CPU_DESC (cpu) = cd;
|
||||
CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
|
||||
}
|
||||
|
||||
bpf_cgen_init_dis (cd);
|
||||
}
|
||||
|
||||
/* XXX do eBPF sim specific initializations. */
|
||||
|
||||
return sd;
|
||||
|
||||
error:
|
||||
bpf_free_state (sd);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
SIM_RC
|
||||
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
|
||||
char *const *argv, char *const *env)
|
||||
{
|
||||
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
|
||||
host_callback *cb = STATE_CALLBACK (sd);
|
||||
bfd_vma addr;
|
||||
|
||||
/* Determine the start address.
|
||||
|
||||
XXX acknowledge bpf_program_section. If it is NULL, emit a
|
||||
warning explaining that we are using the ELF file start address,
|
||||
which often is not what is actually wanted. */
|
||||
if (abfd != NULL)
|
||||
addr = bfd_get_start_address (abfd);
|
||||
else
|
||||
addr = 0;
|
||||
|
||||
sim_pc_set (current_cpu, addr);
|
||||
|
||||
if (STATE_PROG_ARGV (sd) != argv)
|
||||
{
|
||||
freeargv (STATE_PROG_ARGV (sd));
|
||||
STATE_PROG_ARGV (sd) = dupargv (argv);
|
||||
}
|
||||
|
||||
if (STATE_PROG_ENVP (sd) != env)
|
||||
{
|
||||
freeargv (STATE_PROG_ENVP (sd));
|
||||
STATE_PROG_ENVP (sd) = dupargv (env);
|
||||
}
|
||||
|
||||
cb->argv = STATE_PROG_ARGV (sd);
|
||||
cb->envp = STATE_PROG_ENVP (sd);
|
||||
|
||||
return SIM_RC_OK;
|
||||
}
|
||||
+3
-22
@@ -1,5 +1,7 @@
|
||||
/* eBPF simulator main header
|
||||
Copyright (C) 2020-2023 Free Software Foundation, Inc.
|
||||
Copyright (C) 2023 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Oracle Inc.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
@@ -20,27 +22,6 @@
|
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#define SIM_MAIN_H
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|
||||
#include "sim-basics.h"
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#include "opcodes/bpf-desc.h"
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#include "opcodes/bpf-opc.h"
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#include "arch.h"
|
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#include "sim-base.h"
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#include "cgen-sim.h"
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#include "bpf-sim.h"
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#include "bpf-helpers.h"
|
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|
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struct bpf_sim_cpu
|
||||
{
|
||||
/* CPU-model specific parts go here.
|
||||
Note that in files that don't need to access these pieces WANT_CPU_FOO
|
||||
won't be defined and thus these parts won't appear. This is ok in the
|
||||
sense that things work. It is a source of bugs though.
|
||||
One has to of course be careful to not take the size of this
|
||||
struct and no structure members accessed in non-cpu specific files can
|
||||
go after here. */
|
||||
#if defined (WANT_CPU_BPFBF)
|
||||
BPFBF_CPU_DATA cpu_data;
|
||||
#endif
|
||||
};
|
||||
#define BPF_SIM_CPU(cpu) ((struct bpf_sim_cpu *) CPU_ARCH_DATA (cpu))
|
||||
|
||||
#endif /* ! SIM_MAIN_H */
|
||||
|
||||
@@ -112,10 +112,10 @@ main:
|
||||
fail_ne %r1, 0
|
||||
|
||||
;; neg
|
||||
neg %r2
|
||||
neg %r2, %r2
|
||||
fail_ne %r2, -5
|
||||
mov %r1, -1025
|
||||
neg %r1
|
||||
neg %r1, %r1
|
||||
fail_ne %r1, 1025
|
||||
|
||||
pass
|
||||
|
||||
@@ -100,11 +100,11 @@ main:
|
||||
;; neg
|
||||
mov32 %r1, -1
|
||||
mov32 %r2, 0x7fffffff
|
||||
neg32 %r1
|
||||
neg32 %r2
|
||||
neg32 %r1, %r1
|
||||
neg32 %r2, %r2
|
||||
fail_ne32 %r1, 1
|
||||
fail_ne %r2, 0x80000001 ; Note: check for (bad) sign-extend
|
||||
neg32 %r2
|
||||
neg32 %r2, %r2
|
||||
fail_ne32 %r2, 0x7fffffff
|
||||
|
||||
pass
|
||||
|
||||
Reference in New Issue
Block a user