PowerPC SPE/SPE2 aliases in powerpc_macros
* ppc-opc.c (powerpc_macros): Move "evsadd", "evssub", "evsabs", "evsnabs", "evsneg", "evsmul", "evsdiv", "evscmpgt", "evsgmplt", "evsgmpeq", "evscfui", "evscfsi", "evscfuf", "evscfsf", "evsctui", "evsctsi", "evsctuf", "evsctsf", "evsctuiz", "evsctsiz", "evststgt", "evststlt", "evststeq".. (powerpc_opcodes): ..to here. (powerpc_macros): Move "evdotphsssi", "evdotphsssia", "evdotpwsssi", and "evdotpwsssia".. (spe2_opcodes): ..to here.
This commit is contained in:
Alan Modra
+27
-30
@@ -5254,48 +5254,71 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
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{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}},
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{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"evsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"evssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
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{"evsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
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{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
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{"evsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
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{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
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{"evsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
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{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}},
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{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"evsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"evsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}},
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{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"evscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
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{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"evsgmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"evsgmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
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{"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}},
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{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
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{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}},
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{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
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{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"evsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
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{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"evststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"evststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"evststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
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{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
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{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}},
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@@ -10495,36 +10518,6 @@ const unsigned int vle_num_opcodes =
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support extracting the whole word (32 bits in this case). */
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const struct powerpc_macro powerpc_macros[] = {
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/* old SPE instructions have new names with the same opcodes */
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{"evsadd", 3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"},
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{"evssub", 3, PPCSPE|PPCVLE, "efssub %0,%1,%2"},
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{"evsabs", 2, PPCSPE|PPCVLE, "efsabs %0,%1"},
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{"evsnabs", 2, PPCSPE|PPCVLE, "efsnabs %0,%1"},
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{"evsneg", 2, PPCSPE|PPCVLE, "efsneg %0,%1"},
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{"evsmul", 3, PPCSPE|PPCVLE, "efsmul %0,%1,%2"},
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{"evsdiv", 3, PPCSPE|PPCVLE, "efsdiv %0,%1,%2"},
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{"evscmpgt", 3, PPCSPE|PPCVLE, "efscmpgt %0,%1,%2"},
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{"evsgmplt", 3, PPCSPE|PPCVLE, "efscmplt %0,%1,%2"},
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{"evsgmpeq", 3, PPCSPE|PPCVLE, "efscmpeq %0,%1,%2"},
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{"evscfui", 2, PPCSPE|PPCVLE, "efscfui %0,%1"},
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{"evscfsi", 2, PPCSPE|PPCVLE, "efscfsi %0,%1"},
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{"evscfuf", 2, PPCSPE|PPCVLE, "efscfuf %0,%1"},
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{"evscfsf", 2, PPCSPE|PPCVLE, "efscfsf %0,%1"},
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{"evsctui", 2, PPCSPE|PPCVLE, "efsctui %0,%1"},
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{"evsctsi", 2, PPCSPE|PPCVLE, "efsctsi %0,%1"},
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{"evsctuf", 2, PPCSPE|PPCVLE, "efsctuf %0,%1"},
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{"evsctsf", 2, PPCSPE|PPCVLE, "efsctsf %0,%1"},
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{"evsctuiz", 2, PPCSPE|PPCVLE, "efsctuiz %0,%1"},
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{"evsctsiz", 2, PPCSPE|PPCVLE, "efsctsiz %0,%1"},
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{"evststgt", 3, PPCSPE|PPCVLE, "efststgt %0,%1,%2"},
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{"evststlt", 3, PPCSPE|PPCVLE, "efststlt %0,%1,%2"},
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{"evststeq", 3, PPCSPE|PPCVLE, "efststeq %0,%1,%2"},
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/* SPE2 instructions which just are mapped to SPE2 */
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{"evdotphsssi", 3, PPCSPE2, "evdotphssmi %0,%1,%2"},
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{"evdotphsssia", 3, PPCSPE2, "evdotphssmia %0,%1,%2"},
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{"evdotpwsssi", 3, PPCSPE2, "evdotpwssmi %0,%1,%2"},
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{"evdotpwsssia", 3, PPCSPE2, "evdotpwssmia %0,%1,%2"}
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};
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const int powerpc_num_macros =
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@@ -10622,6 +10615,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
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{"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphsssi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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@@ -10645,6 +10639,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
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{"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphsssia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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@@ -10717,6 +10712,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
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{"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwsssi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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@@ -10732,6 +10728,7 @@ const struct powerpc_opcode spe2_opcodes[] = {
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{"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwsssia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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{"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}},
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