Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.
sim/aarch64 * simulator.c (NEG, POS): Move before set_flags_for_add64. (set_flags_for_add64): Replace with a modified copy of set_flags_for_sub64. sim/testsuite/sim/aarch64 * testutils.inc (pass): Move .Lpass to start. (fail): Move .Lfail to start. Return 1 instead of 0. (start): Moved .Lpass and .Lfail to here. * adds.s: New. * fstur.s: New. * tbnz.s: New.
This commit is contained in:
Jim Wilson
@@ -1,3 +1,9 @@
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2016-12-13 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (NEG, POS): Move before set_flags_for_add64.
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(set_flags_for_add64): Replace with a modified copy of
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set_flags_for_sub64.
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2016-12-03 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
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+15
-36
@@ -1659,55 +1659,34 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2)
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aarch64_set_CPSR (cpu, flags);
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}
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#define NEG(a) (((a) & signbit) == signbit)
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#define POS(a) (((a) & signbit) == 0)
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static void
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set_flags_for_add64 (sim_cpu *cpu, uint64_t value1, uint64_t value2)
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{
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int64_t sval1 = value1;
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int64_t sval2 = value2;
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uint64_t result = value1 + value2;
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int64_t sresult = sval1 + sval2;
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uint32_t flags = 0;
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uint64_t result = value1 + value2;
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uint32_t flags = 0;
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uint64_t signbit = 1ULL << 63;
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if (result == 0)
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flags |= Z;
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if (result & (1ULL << 63))
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if (NEG (result))
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flags |= N;
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if (sval1 < 0)
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{
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if (sval2 < 0)
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{
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/* Negative plus a negative. Overflow happens if
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the result is greater than either of the operands. */
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if (sresult > sval1 || sresult > sval2)
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flags |= V;
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}
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/* else Negative plus a positive. Overflow cannot happen. */
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}
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else /* value1 is +ve. */
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{
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if (sval2 < 0)
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{
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/* Overflow can only occur if we computed "0 - MININT". */
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if (sval1 == 0 && sval2 == (1LL << 63))
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flags |= V;
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}
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else
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{
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/* Postive plus positive - overflow has happened if the
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result is smaller than either of the operands. */
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if (result < value1 || result < value2)
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flags |= V | C;
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}
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}
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if ( (NEG (value1) && NEG (value2))
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|| (NEG (value1) && POS (result))
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|| (NEG (value2) && POS (result)))
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flags |= C;
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if ( (NEG (value1) && NEG (value2) && POS (result))
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|| (POS (value1) && POS (value2) && NEG (result)))
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flags |= V;
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aarch64_set_CPSR (cpu, flags);
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}
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#define NEG(a) (((a) & signbit) == signbit)
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#define POS(a) (((a) & signbit) == 0)
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static void
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set_flags_for_sub32 (sim_cpu *cpu, uint32_t value1, uint32_t value2)
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{
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@@ -1,3 +1,12 @@
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2016-12-13 Jim Wilson <jim.wilson@linaro.org>
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* testutils.inc (pass): Move .Lpass to start.
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(fail): Move .Lfail to start. Return 1 instead of 0.
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(start): Moved .Lpass and .Lfail to here.
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* adds.s: New.
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* fstur.s: New.
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* tbnz.s: New.
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2015-11-24 Nick Clifton <nickc@redhat.com>
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* pass.s, allinsn.exp, testutils.inc: New files.
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@@ -0,0 +1,81 @@
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# mach: aarch64
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# Check the basic integer compare instructions: adds, adds64, subs, subs64.
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# For add, check value pairs 1 and -1 (Z), -1 and -1 (N), 2 and -1 (C),
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# and MIN_INT and -1 (V),
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# For sub, negate the second value.
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.include "testutils.inc"
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start
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mov w0, #1
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mov w1, #-1
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adds w2, w0, w1
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bne .Lfailure
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mov w0, #-1
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mov w1, #-1
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adds w2, w0, w1
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bpl .Lfailure
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mov w0, #2
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mov w1, #-1
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adds w2, w0, w1
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bcc .Lfailure
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mov w0, #0x80000000
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mov w1, #-1
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adds w2, w0, w1
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bvc .Lfailure
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mov x0, #1
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mov x1, #-1
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adds x2, x0, x1
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bne .Lfailure
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mov x0, #-1
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mov x1, #-1
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adds x2, x0, x1
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bpl .Lfailure
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mov x0, #2
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mov x1, #-1
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adds x2, x0, x1
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bcc .Lfailure
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mov x0, #0x8000000000000000
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mov x1, #-1
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adds x2, x0, x1
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bvc .Lfailure
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mov w0, #1
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mov w1, #1
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subs w2, w0, w1
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bne .Lfailure
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mov w0, #-1
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mov w1, #1
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subs w2, w0, w1
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bpl .Lfailure
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mov w0, #2
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mov w1, #1
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subs w2, w0, w1
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bcc .Lfailure
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mov w0, #0x80000000
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mov w1, #1
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subs w2, w0, w1
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bvc .Lfailure
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mov x0, #1
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mov x1, #1
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subs x2, x0, x1
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bne .Lfailure
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mov x0, #-1
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mov x1, #1
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subs x2, x0, x1
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bpl .Lfailure
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mov x0, #2
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mov x1, #1
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subs x2, x0, x1
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bcc .Lfailure
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mov x0, #0x8000000000000000
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mov x1, #1
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subs x2, x0, x1
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bvc .Lfailure
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pass
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.Lfailure:
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fail
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@@ -0,0 +1,136 @@
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# mach: aarch64
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# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq.
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# Check the values -1, and XXX_MAX, which tests all bits.
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# Check with offsets -256 and 255, which tests all bits.
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# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq.
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.include "testutils.inc"
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.data
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fm1:
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.word 3212836864
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fmax:
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.word 2139095039
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ftmp:
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.word 0
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dm1:
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.word 0
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.word -1074790400
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dmax:
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.word 4294967295
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.word 2146435071
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dtmp:
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.word 0
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.word 0
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ldm1:
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.word 0
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.word 0
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.word 0
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.word -1073807360
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ldmax:
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.word 4294967295
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.word 4294967295
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.word 4294967295
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.word 2147418111
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ldtmp:
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.word 0
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.word 0
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.word 0
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.word 0
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start
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adrp x1, ftmp
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add x1, x1, :lo12:ftmp
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adrp x0, fm1
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add x0, x0, :lo12:fm1
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sub x5, x0, #255
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sub x6, x1, #255
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movi d2, #0
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ldur s2, [x5, #255]
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stur s2, [x6, #255]
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ldr w3, [x0]
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ldr w4, [x1]
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cmp w3, w4
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bne .Lfailure
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adrp x0, fmax
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add x0, x0, :lo12:fmax
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add x5, x0, #256
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add x6, x1, #256
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movi d2, #0
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ldur s2, [x5, #-256]
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stur s2, [x6, #-256]
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ldr w3, [x0]
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ldr w4, [x1]
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cmp w3, w4
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bne .Lfailure
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adrp x1, dtmp
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add x1, x1, :lo12:dtmp
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adrp x0, dm1
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add x0, x0, :lo12:dm1
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sub x5, x0, #255
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sub x6, x1, #255
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movi d2, #0
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ldur d2, [x5, #255]
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stur d2, [x6, #255]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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adrp x0, dmax
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add x0, x0, :lo12:dmax
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add x5, x0, #256
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add x6, x1, #256
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movi d2, #0
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ldur d2, [x5, #-256]
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stur d2, [x6, #-256]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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adrp x1, ldtmp
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add x1, x1, :lo12:ldtmp
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adrp x0, ldm1
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add x0, x0, :lo12:ldm1
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sub x5, x0, #255
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sub x6, x1, #255
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movi v2.2d, #0
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ldur q2, [x5, #255]
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stur q2, [x6, #255]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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ldr x3, [x0, 8]
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ldr x4, [x1, 8]
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cmp x3, x4
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bne .Lfailure
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adrp x0, ldmax
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add x0, x0, :lo12:ldmax
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add x5, x0, #256
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add x6, x1, #256
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movi v2.2d, #0
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ldur q2, [x5, #-256]
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stur q2, [x6, #-256]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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ldr x3, [x0, 8]
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ldr x4, [x1, 8]
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cmp x3, x4
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bne .Lfailure
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pass
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.Lfailure:
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fail
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@@ -0,0 +1,55 @@
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# mach: aarch64
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# Check the test-bit-and-branch instructions: tbnz, and tbz.
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# We check the edge condition bit positions: 0, 1<<31, 1<<32, 1<<63.
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.include "testutils.inc"
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start
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mov x0, #1
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tbnz x0, #0, .L1
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fail
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.L1:
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tbz x0, #0, .Lfailure
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mov x0, #0xFFFFFFFFFFFFFFFE
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tbnz x0, #0, .Lfailure
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tbz x0, #0, .L2
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fail
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.L2:
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mov x0, #0x80000000
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tbnz x0, #31, .L3
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fail
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.L3:
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tbz x0, #31, .Lfailure
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mov x0, #0xFFFFFFFF7FFFFFFF
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tbnz x0, #31, .Lfailure
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tbz x0, #31, .L4
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fail
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.L4:
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mov x0, #0x100000000
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tbnz x0, #32, .L5
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fail
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.L5:
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tbz x0, #32, .Lfailure
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mov x0, #0xFFFFFFFEFFFFFFFF
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tbnz x0, #32, .Lfailure
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tbz x0, #32, .L6
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fail
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.L6:
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mov x0, #0x8000000000000000
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tbnz x0, #63, .L7
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fail
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.L7:
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tbz x0, #63, .Lfailure
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mov x0, #0x7FFFFFFFFFFFFFFF
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tbnz x0, #63, .Lfailure
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tbz x0, #63, .L8
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fail
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.L8:
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pass
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.Lfailure:
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fail
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@@ -43,10 +43,6 @@
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swiwrite 5
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exit 0
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.data
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.Lpass:
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.asciz "pass\n"
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.endm
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# MACRO: fail
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@@ -56,16 +52,18 @@
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adrp x1, .Lfail
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add x1, x1, :lo12:.Lfail
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swiwrite 5
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exit 0
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.data
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.Lfail:
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.asciz "fail\n"
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exit 1
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.endm
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# MACRO: start
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# All assembler tests should start with a call to "start"
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.macro start
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.data
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.Lpass:
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.asciz "pass\n"
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.Lfail:
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.asciz "fail\n"
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.text
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.global _start
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_start:
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