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2009-07-17 H.J. Lu <hongjiu.lu@intel.com>

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* config/tc-i386.c (md_assemble): Check implicit registers
	only for instructions with 3 operands or less.
This commit is contained in:
H.J. Lu 2009-07-17 17:08:34 +00:00
parent 831a0c4447
commit 9afe6eb82f
2 changed files with 14 additions and 6 deletions

5
gas/ChangeLog

@ -1,3 +1,8 @@
2009-07-17 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_assemble): Check implicit registers
only for instructions with 3 operands or less.
2009-07-17 Nick Clifton <nickc@redhat.com> 2009-07-17 Nick Clifton <nickc@redhat.com>
* config/tc-avr.c (md_apply_fix): Cast fixup reloc type to avoid * config/tc-avr.c (md_apply_fix): Cast fixup reloc type to avoid

15
gas/config/tc-i386.c

@ -2821,12 +2821,15 @@ md_assemble (char *line)
if (i.types[0].bitfield.imm1) if (i.types[0].bitfield.imm1)
i.imm_operands = 0; /* kludge for shift insns. */ i.imm_operands = 0; /* kludge for shift insns. */
for (j = 0; j < i.operands; j++) /* We only need to check those implicit registers for instructions
if (i.types[j].bitfield.inoutportreg with 3 operands or less. */
|| i.types[j].bitfield.shiftcount if (i.operands <= 3)
|| i.types[j].bitfield.acc for (j = 0; j < i.operands; j++)
|| i.types[j].bitfield.floatacc) if (i.types[j].bitfield.inoutportreg
i.reg_operands--; || i.types[j].bitfield.shiftcount
|| i.types[j].bitfield.acc
|| i.types[j].bitfield.floatacc)
i.reg_operands--;
/* ImmExt should be processed after SSE2AVX. */ /* ImmExt should be processed after SSE2AVX. */
if (!i.tm.opcode_modifier.sse2avx if (!i.tm.opcode_modifier.sse2avx