RISC-V: Updated the default ISA spec to 20191213.

Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1.  Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions.  Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.

bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
	recognize zicsr and zifencei.
gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
	* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
	* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
	into Tag_RISCV_arch since it is added implied when i's version is
	larger than 2.1.

bfd/elfxx-riscv.c

@@ -1562,7 +1562,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
 	rps->error_handler
 	  (_("x ISA extension `%s' must be set with the versions"),
 	   subset);
-      else
+      /* Allow old ISA spec can recognize zicsr and zifencei.  */
+      else if (strcmp (subset, "zicsr") != 0
+	       && strcmp (subset, "zifencei") != 0)
 	rps->error_handler
 	  (_("cannot find default versions of the ISA extension `%s'"),
 	   subset);

gas/config/tc-riscv.c

@@ -104,7 +104,7 @@ struct riscv_csr_extra
 
 /* Need to sync the version with RISC-V compiler.  */
 #ifndef DEFAULT_RISCV_ISA_SPEC
-#define DEFAULT_RISCV_ISA_SPEC "2.2"
+#define DEFAULT_RISCV_ISA_SPEC "20191213"
 #endif
 
 #ifndef DEFAULT_RISCV_PRIV_SPEC

gas/testsuite/gas/riscv/csr-version-1p10.d

@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.10
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10
 #source: csr.s
 #warning_output: csr-version-1p10.l
 #objdump: -dr -Mpriv-spec=1.10

gas/testsuite/gas/riscv/csr-version-1p11.d

@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.11
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11
 #source: csr.s
 #warning_output: csr-version-1p11.l
 #objdump: -dr -Mpriv-spec=1.11

gas/testsuite/gas/riscv/csr-version-1p12.d

@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.12
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12
 #source: csr.s
 #warning_output: csr-version-1p12.l
 #objdump: -dr -Mpriv-spec=1.12

gas/testsuite/gas/riscv/csr-version-1p9p1.d

@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1
 #source: csr.s
 #warning_output: csr-version-1p9p1.l
 #objdump: -dr -Mpriv-spec=1.9.1

gas/testsuite/gas/riscv/option-arch-03.d

@@ -4,5 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_c2p0"
+  Tag_RISCV_arch: "rv32i2p1_c2p0"
 #...

gas/testsuite/gas/riscv/option-arch-03.s

@@ -1,3 +1,3 @@
 .attribute arch, "rv64ic"
 .option arch, +d2p0, -c
-.option arch, rv32ic
+.option arch, rv32i2p1c2p0

ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d

@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s

@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s

@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d

@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s

@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s

@@ -1 +1 @@
-	.attribute arch, "rv32i2p0"
+	.attribute arch, "rv32i2p1"

ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d

@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s

@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0_xfoo2p0"
+	.attribute arch, "rv32i2p1_m2p0_xfoo2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s

@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_xbar2p0"
+	.attribute arch, "rv32i2p1_xbar2p0"

ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d

@@ -23,5 +23,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_xunknown4p0"
+  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_zifencei2p0_xunknown4p0"
 #..

ld/testsuite/ld-riscv-elf/call-relax.d

@@ -3,7 +3,7 @@
 #source: call-relax-1.s
 #source: call-relax-2.s
 #source: call-relax-3.s
-#as: -march=rv32ic -mno-arch-attr
+#as: -march=rv32ic_zicsr -mno-arch-attr
 #ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d
 #pass