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aarch64: Allow writes to MFAR_EL3

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MFAR_EL3 is a read/write register, but was incorrectly marked as
read-only
[https://developer.arm.com/documentation/ddi0601/2021-09/AArch64-Registers/MFAR-EL3--PA-Fault-Address-Register?lang=en]

opcodes/
	* aarch64-opc.c (aarch64_sys_regs): Mark mfar_el3 as read-write.

gas/
	* testsuite/gas/aarch64/rme.s: Test writing to mfar_el3.
	* testsuite/gas/aarch64/rme.d: Update accordingly.
	* testsuite/gas/aarch64/rme-invalid.s: Delete.
	* testsuite/gas/aarch64/rme-invalid.l: Likewise.
	* testsuite/gas/aarch64/rme-invalid.d: Likewise.
This commit is contained in:
Richard Sandiford 2021-11-30 17:50:24 +00:00
parent 1864b6578b
commit b009f915c9
6 changed files with 14 additions and 21 deletions
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3
gas/testsuite/gas/aarch64/rme-invalid.d
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@ -1,3 +0,0 @@
#name: Invalid RME System registers usage
#source: rme-invalid.s
#warning_output: rme-invalid.l

2
gas/testsuite/gas/aarch64/rme-invalid.l
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@ -1,2 +0,0 @@
.*: Assembler messages:
.*: Warning: specified register cannot be written to at operand 1 -- `msr mfar_el3,x0'

4
gas/testsuite/gas/aarch64/rme-invalid.s
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@ -1,4 +0,0 @@
/* Realm Management Extension. */
/* Illegal write to RME system registers. */
msr mfar_el3, x0

23
gas/testsuite/gas/aarch64/rme.d
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@ -7,14 +7,15 @@ Disassembly of section \.text:
0+ <.*>:
0: d53e60a0 mrs x0, mfar_el3
4: d53e21c0 mrs x0, gpccr_el3
8: d53e2180 mrs x0, gptbr_el3
c: d51e21c0 msr gpccr_el3, x0
10: d51e2180 msr gptbr_el3, x0
14: d50e7e20 dc cipapa, x0
18: d50e7ea0 dc cigdpapa, x0
1c: d50e8460 tlbi rpaos, x0
20: d50e84e0 tlbi rpalos, x0
24: d50e819f tlbi paallos
28: d50e879f tlbi paall
[^:]*: d53e60a0 mrs x0, mfar_el3
[^:]*: d53e21c0 mrs x0, gpccr_el3
[^:]*: d53e2180 mrs x0, gptbr_el3
[^:]*: d51e60a0 msr mfar_el3, x0
[^:]*: d51e21c0 msr gpccr_el3, x0
[^:]*: d51e2180 msr gptbr_el3, x0
[^:]*: d50e7e20 dc cipapa, x0
[^:]*: d50e7ea0 dc cigdpapa, x0
[^:]*: d50e8460 tlbi rpaos, x0
[^:]*: d50e84e0 tlbi rpalos, x0
[^:]*: d50e819f tlbi paallos
[^:]*: d50e879f tlbi paall

1
gas/testsuite/gas/aarch64/rme.s
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@ -6,6 +6,7 @@ mrs x0, gpccr_el3
mrs x0, gptbr_el3
/* Write to RME system registers. */
msr mfar_el3, x0
msr gpccr_el3, x0
msr gptbr_el3, x0

2
opcodes/aarch64-opc.c
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@ -4833,7 +4833,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0),
SR_CORE ("mfar_el3", CPENC (3,6,C6,C0,5), F_REG_READ),
SR_CORE ("mfar_el3", CPENC (3,6,C6,C0,5), 0),
SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0),
SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0),