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aarch64: Add SVE2.1 Contiguous load/store instructions.

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Hi,

This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.
This commit is contained in:
Srinath Parvathaneni
2024-01-15 09:40:11 +00:00
committed by Nick Clifton
parent b34104edab
commit b33f1bcd15
9 changed files with 108 additions and 2 deletions
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include/opcode/aarch64.h
+3
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@@ -797,6 +797,9 @@ enum aarch64_opnd
AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */
AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */
AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */
AARCH64_OPND_SME_Zt2, /* Qobule SVE vector register list. */
AARCH64_OPND_SME_Zt3, /* Trible SVE vector register list. */
AARCH64_OPND_SME_Zt4, /* Quad SVE vector register list. */
};
/* Qualifier constrains an operand. It either specifies a variant of an