bfd:
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo . (ALL_MACHINES_CFILES): Add cpu-epiphany.c . (BFD32_BACKENDS): Add elf32-epiphany.lo . (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c . * Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate. * archures.c (bfd_arch_epiphany): Add. (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. (bfd_epiphany_arch): Declare. (bfd_archures_list): Add &bfd_epiphany_arch. * config.bfd (epiphany-*-elf): New target case. * configure.in (bfd_elf32_epiphany_vec): New target vector case. * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. * targets.c (bfd_elf32_epiphany_vec): Declare. (_bfd_target_vector): Add bfd_elf32_epiphany_vec. * po/SRC-POTFILES.in, po/bfd.pot: Regenerate. * cpu-epiphany.c, elf32-epiphany.c: New files. binutils: * readelf.c (include "elf/epiphany.h") (guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY. (get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise. (is_16bit_abs_reloc, is_none_reloc): Likewise. * po/binutils.pot: Regenerate. cpu: * cpu/epiphany.cpu, cpu/epiphany.opc: New files. gas: * NEWS: Mention addition of Adapteva Epiphany support. * config/tc-epiphany.c, config/tc-epiphany.h: New files. * Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c . (TARGET_CPU_HFILES): Add config/tc-epiphany.h . * Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate. * configure.in: Also set using_cgen for epiphany. * configure.tgt: Handle epiphany. * doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi . * doc/all.texi: Set EPIPHANY. * doc/as.texinfo: Add EPIPHANY-specific text. * doc/c-epiphany.texi: New file. * po/gas.pot: Regenerate. gas/testsuite: * gas/epiphany: New directory. include: * dis-asm.h (print_insn_epiphany): Declare. * elf/epiphany.h: New file. * elf/common.h (EM_ADAPTEVA_EPIPHANY): Define. ld: * NEWS: Mention addition of Adapteva Epiphany support. * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c . (eelf32epiphany.c): New rule. * Makefile.in: Regenerate. * configure.tgt: Handle epiphany-*-elf. * po/ld.pot: Regenerate. * testsuite/ld-srec/srec.exp: xfail epiphany. * emulparams/elf32epiphany.sh: New file. opcodes: * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . (CLEANFILES): Add stamp-epiphany. (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. (stamp-epiphany): New rule. * Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate. * configure.in: Handle bfd_epiphany_arch. * disassemble.c (ARCH_epiphany): Define. (disassembler): Handle bfd_arch_epiphany. * epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files. * epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise. * epiphany-opc.h: Likewise.
This commit is contained in:
Nick Clifton
parent
0a394bfbad
commit
cfb8c0921c
@ -1,3 +1,30 @@
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2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
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* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo.
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(ALL_MACHINES_CFILES): Add cpu-epiphany.c.
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(BFD32_BACKENDS): Add elf32-epiphany.lo.
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(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c.
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* archures.c (bfd_arch_epiphany): Add.
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(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
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(bfd_epiphany_arch): Declare.
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(bfd_archures_list): Add &bfd_epiphany_arch.
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* config.bfd (epiphany-*-elf): New target case.
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* configure.in (bfd_elf32_epiphany_vec): New target vector case.
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* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
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(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
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(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
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(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
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* targets.c (bfd_elf32_epiphany_vec): Declare.
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(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
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* Makefile.in: Regenerate.
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* bfd-in2.h: Regenerate.
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* configure: Regenerate.
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* libbfd.h: Regenerate.
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* po/SRC-POTFILES.in: Regenerate.
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* po/bfd.pot: Regenerate.
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* cpu-epiphany.c: New file.
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* elf32-epiphany.c: New file.
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2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
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2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
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* elfxx-mips.c (_bfd_mips_elf_symbol_processing): Remove
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* elfxx-mips.c (_bfd_mips_elf_symbol_processing): Remove
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@ -83,6 +83,7 @@ ALL_MACHINES = \
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cpu-d10v.lo \
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cpu-d10v.lo \
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cpu-d30v.lo \
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cpu-d30v.lo \
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cpu-dlx.lo \
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cpu-dlx.lo \
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cpu-epiphany.lo \
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cpu-fr30.lo \
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cpu-fr30.lo \
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cpu-frv.lo \
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cpu-frv.lo \
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cpu-h8300.lo \
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cpu-h8300.lo \
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@ -158,6 +159,7 @@ ALL_MACHINES_CFILES = \
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cpu-d10v.c \
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cpu-d10v.c \
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cpu-d30v.c \
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cpu-d30v.c \
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cpu-dlx.c \
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cpu-dlx.c \
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cpu-epiphany.c \
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cpu-fr30.c \
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cpu-fr30.c \
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cpu-frv.c \
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cpu-frv.c \
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cpu-h8300.c \
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cpu-h8300.c \
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@ -286,6 +288,7 @@ BFD32_BACKENDS = \
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elf32-d10v.lo \
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elf32-d10v.lo \
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elf32-d30v.lo \
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elf32-d30v.lo \
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elf32-dlx.lo \
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elf32-dlx.lo \
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elf32-epiphany.lo \
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elf32-fr30.lo \
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elf32-fr30.lo \
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elf32-frv.lo \
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elf32-frv.lo \
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elf32-gen.lo \
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elf32-gen.lo \
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@ -470,6 +473,7 @@ BFD32_BACKENDS_CFILES = \
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elf32-d10v.c \
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elf32-d10v.c \
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elf32-d30v.c \
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elf32-d30v.c \
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elf32-dlx.c \
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elf32-dlx.c \
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elf32-epiphany.c \
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elf32-fr30.c \
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elf32-fr30.c \
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elf32-frv.c \
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elf32-frv.c \
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elf32-gen.c \
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elf32-gen.c \
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@ -382,6 +382,7 @@ ALL_MACHINES = \
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cpu-d10v.lo \
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cpu-d10v.lo \
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cpu-d30v.lo \
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cpu-d30v.lo \
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cpu-dlx.lo \
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cpu-dlx.lo \
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cpu-epiphany.lo \
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cpu-fr30.lo \
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cpu-fr30.lo \
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cpu-frv.lo \
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cpu-frv.lo \
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cpu-h8300.lo \
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cpu-h8300.lo \
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@ -457,6 +458,7 @@ ALL_MACHINES_CFILES = \
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cpu-d10v.c \
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cpu-d10v.c \
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cpu-d30v.c \
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cpu-d30v.c \
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cpu-dlx.c \
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cpu-dlx.c \
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cpu-epiphany.c \
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cpu-fr30.c \
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cpu-fr30.c \
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cpu-frv.c \
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cpu-frv.c \
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cpu-h8300.c \
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cpu-h8300.c \
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@ -586,6 +588,7 @@ BFD32_BACKENDS = \
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elf32-d10v.lo \
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elf32-d10v.lo \
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elf32-d30v.lo \
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elf32-d30v.lo \
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elf32-dlx.lo \
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elf32-dlx.lo \
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elf32-epiphany.lo \
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elf32-fr30.lo \
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elf32-fr30.lo \
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elf32-frv.lo \
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elf32-frv.lo \
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elf32-gen.lo \
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elf32-gen.lo \
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@ -770,6 +773,7 @@ BFD32_BACKENDS_CFILES = \
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elf32-d10v.c \
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elf32-d10v.c \
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elf32-d30v.c \
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elf32-d30v.c \
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elf32-dlx.c \
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elf32-dlx.c \
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elf32-epiphany.c \
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elf32-fr30.c \
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elf32-fr30.c \
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elf32-frv.c \
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elf32-frv.c \
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elf32-gen.c \
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elf32-gen.c \
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@ -1260,6 +1264,7 @@ distclean-compile:
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d10v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d10v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d30v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d30v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-dlx.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-dlx.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-epiphany.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-fr30.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-fr30.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-frv.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-frv.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-h8300.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-h8300.Plo@am__quote@
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@ -1346,6 +1351,7 @@ distclean-compile:
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d10v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d10v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d30v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d30v.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-dlx.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-dlx.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-epiphany.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-fr30.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-fr30.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-frv.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-frv.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-gen.Plo@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-gen.Plo@am__quote@
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@ -365,6 +365,9 @@ DESCRIPTION
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. bfd_arch_iq2000, {* Vitesse IQ2000. *}
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. bfd_arch_iq2000, {* Vitesse IQ2000. *}
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.#define bfd_mach_iq2000 1
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.#define bfd_mach_iq2000 1
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.#define bfd_mach_iq10 2
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.#define bfd_mach_iq10 2
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. bfd_arch_epiphany, {* Adapteva EPIPHANY *}
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.#define bfd_mach_epiphany16 1
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.#define bfd_mach_epiphany32 2
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. bfd_arch_mt,
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. bfd_arch_mt,
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.#define bfd_mach_ms1 1
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.#define bfd_mach_ms1 1
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.#define bfd_mach_mrisc2 2
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.#define bfd_mach_mrisc2 2
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@ -496,6 +499,7 @@ extern const bfd_arch_info_type bfd_crx_arch;
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extern const bfd_arch_info_type bfd_d10v_arch;
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extern const bfd_arch_info_type bfd_d10v_arch;
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extern const bfd_arch_info_type bfd_d30v_arch;
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extern const bfd_arch_info_type bfd_d30v_arch;
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extern const bfd_arch_info_type bfd_dlx_arch;
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extern const bfd_arch_info_type bfd_dlx_arch;
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extern const bfd_arch_info_type bfd_epiphany_arch;
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extern const bfd_arch_info_type bfd_fr30_arch;
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extern const bfd_arch_info_type bfd_fr30_arch;
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extern const bfd_arch_info_type bfd_frv_arch;
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extern const bfd_arch_info_type bfd_frv_arch;
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extern const bfd_arch_info_type bfd_h8300_arch;
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extern const bfd_arch_info_type bfd_h8300_arch;
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@ -576,6 +580,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
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&bfd_d10v_arch,
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&bfd_d10v_arch,
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&bfd_d30v_arch,
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&bfd_d30v_arch,
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&bfd_dlx_arch,
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&bfd_dlx_arch,
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&bfd_epiphany_arch,
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&bfd_fr30_arch,
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&bfd_fr30_arch,
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&bfd_frv_arch,
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&bfd_frv_arch,
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&bfd_h8300_arch,
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&bfd_h8300_arch,
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@ -2071,6 +2071,9 @@ enum bfd_architecture
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bfd_arch_iq2000, /* Vitesse IQ2000. */
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bfd_arch_iq2000, /* Vitesse IQ2000. */
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#define bfd_mach_iq2000 1
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#define bfd_mach_iq2000 1
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#define bfd_mach_iq10 2
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#define bfd_mach_iq10 2
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bfd_arch_epiphany, /* Adapteva EPIPHANY */
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#define bfd_mach_epiphany16 1
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#define bfd_mach_epiphany32 2
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bfd_arch_mt,
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bfd_arch_mt,
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#define bfd_mach_ms1 1
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#define bfd_mach_ms1 1
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#define bfd_mach_mrisc2 2
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#define bfd_mach_mrisc2 2
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@ -5023,6 +5026,27 @@ the dynamic object into the runtime process image. */
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BFD_RELOC_TILEGX_TLS_DTPMOD32,
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BFD_RELOC_TILEGX_TLS_DTPMOD32,
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BFD_RELOC_TILEGX_TLS_DTPOFF32,
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BFD_RELOC_TILEGX_TLS_DTPOFF32,
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BFD_RELOC_TILEGX_TLS_TPOFF32,
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BFD_RELOC_TILEGX_TLS_TPOFF32,
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/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */
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BFD_RELOC_EPIPHANY_SIMM8,
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/* Adapteva EPIPHANY - 24 bit signed pc-relative displacement */
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BFD_RELOC_EPIPHANY_SIMM24,
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/* Adapteva EPIPHANY - 16 most-significant bits of absolute address */
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BFD_RELOC_EPIPHANY_HIGH,
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/* Adapteva EPIPHANY - 16 least-significant bits of absolute address */
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BFD_RELOC_EPIPHANY_LOW,
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/* Adapteva EPIPHANY - 11 bit signed number - add/sub immediate */
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BFD_RELOC_EPIPHANY_SIMM11,
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/* Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) */
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BFD_RELOC_EPIPHANY_IMM11,
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/* Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. */
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BFD_RELOC_EPIPHANY_IMM8,
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BFD_RELOC_UNUSED };
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BFD_RELOC_UNUSED };
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typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
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typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
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reloc_howto_type *bfd_reloc_type_lookup
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reloc_howto_type *bfd_reloc_type_lookup
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@ -361,6 +361,10 @@ case "${targ}" in
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targ_defvec=bfd_elf32_d30v_vec
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targ_defvec=bfd_elf32_d30v_vec
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;;
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;;
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epiphany-*-elf)
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targ_defvec=bfd_elf32_epiphany_vec
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;;
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fido-*-elf* )
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fido-*-elf* )
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targ_defvec=bfd_elf32_m68k_vec
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targ_defvec=bfd_elf32_m68k_vec
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targ_selvecs="m68kcoff_vec ieee_vec"
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targ_selvecs="m68kcoff_vec ieee_vec"
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1
bfd/configure
vendored
1
bfd/configure
vendored
@ -15199,6 +15199,7 @@ do
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bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;;
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bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;;
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bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;;
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bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;;
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bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;;
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bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;;
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bfd_elf32_epiphany_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;;
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bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
|
bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
|
||||||
bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
||||||
bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
||||||
|
|||||||
@ -698,6 +698,7 @@ do
|
|||||||
bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;;
|
bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;;
|
||||||
bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;;
|
bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;;
|
||||||
bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;;
|
bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;;
|
||||||
|
bfd_elf32_epiphany_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;;
|
||||||
bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
|
bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;;
|
||||||
bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
||||||
bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;;
|
||||||
|
|||||||
56
bfd/cpu-epiphany.c
Normal file
56
bfd/cpu-epiphany.c
Normal file
@ -0,0 +1,56 @@
|
|||||||
|
/* BFD support for the Adapteva EPIPHANY processor.
|
||||||
|
Copyright 2011 Free Software Foundation, Inc.
|
||||||
|
Contributed by Embecosm on behalf of Adapteva, Inc.
|
||||||
|
|
||||||
|
This file is part of BFD, the Binary File Descriptor library.
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
This program is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program; if not, write to the Free Software
|
||||||
|
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||||
|
MA 02110-1301, USA. */
|
||||||
|
|
||||||
|
#include "sysdep.h"
|
||||||
|
#include "bfd.h"
|
||||||
|
#include "libbfd.h"
|
||||||
|
|
||||||
|
const bfd_arch_info_type bfd_epiphany16_arch =
|
||||||
|
{
|
||||||
|
32, /* Bits per word */
|
||||||
|
32, /* Bits per address. */
|
||||||
|
8, /* Bits per byte. */
|
||||||
|
bfd_arch_epiphany, /* Architecture. */
|
||||||
|
bfd_mach_epiphany16, /* Machine. */
|
||||||
|
"epiphany", /* Architecture name. */
|
||||||
|
"epiphany16", /* Machine name. */
|
||||||
|
1, /* Section align power. */
|
||||||
|
FALSE, /* The default ? */
|
||||||
|
bfd_default_compatible, /* Architecture comparison fn. */
|
||||||
|
bfd_default_scan, /* String to architecture convert fn. */
|
||||||
|
NULL /* Next in list. */
|
||||||
|
};
|
||||||
|
|
||||||
|
const bfd_arch_info_type bfd_epiphany_arch =
|
||||||
|
{
|
||||||
|
32, /* Bits per word - not really true. */
|
||||||
|
32, /* Bits per address. */
|
||||||
|
8, /* Bits per byte. */
|
||||||
|
bfd_arch_epiphany, /* Architecture. */
|
||||||
|
bfd_mach_epiphany32, /* Machine. */
|
||||||
|
"epiphany", /* Architecture name. */
|
||||||
|
"epiphany32", /* Machine name. */
|
||||||
|
2, /* Section align power. */
|
||||||
|
TRUE, /* The default ? */
|
||||||
|
bfd_default_compatible, /* Architecture comparison fn. */
|
||||||
|
bfd_default_scan, /* String to architecture convert fn. */
|
||||||
|
& bfd_epiphany16_arch /* Next in list. */
|
||||||
|
};
|
||||||
608
bfd/elf32-epiphany.c
Normal file
608
bfd/elf32-epiphany.c
Normal file
@ -0,0 +1,608 @@
|
|||||||
|
/* Adapteva epiphany specific support for 32-bit ELF
|
||||||
|
Copyright 2011
|
||||||
|
Free Software Foundation, Inc.
|
||||||
|
Contributed by Embecosm on behalf of Adapteva, Inc.
|
||||||
|
|
||||||
|
This file is part of BFD, the Binary File Descriptor library.
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
This program is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program; if not, write to the Free Software
|
||||||
|
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||||
|
MA 02110-1301, USA. */
|
||||||
|
|
||||||
|
#include "sysdep.h"
|
||||||
|
#include "bfd.h"
|
||||||
|
#include "libbfd.h"
|
||||||
|
#include "elf-bfd.h"
|
||||||
|
#include "elf/epiphany.h"
|
||||||
|
#include "libiberty.h"
|
||||||
|
|
||||||
|
/* Struct used to pass miscellaneous paramaters which
|
||||||
|
helps to avoid overly long parameter lists. */
|
||||||
|
struct misc
|
||||||
|
{
|
||||||
|
Elf_Internal_Shdr * symtab_hdr;
|
||||||
|
Elf_Internal_Rela * irelbase;
|
||||||
|
bfd_byte * contents;
|
||||||
|
Elf_Internal_Sym * isymbuf;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct epiphany_opcode
|
||||||
|
{
|
||||||
|
unsigned short opcode;
|
||||||
|
unsigned short mask;
|
||||||
|
};
|
||||||
|
|
||||||
|
static bfd_boolean epiphany_relaxed = FALSE;
|
||||||
|
|
||||||
|
/* Relocation tables. */
|
||||||
|
static reloc_howto_type epiphany_elf_howto_table [] =
|
||||||
|
{
|
||||||
|
#define AHOW(t,rs,s,bs,pr,bp,co,name,sm,dm) \
|
||||||
|
HOWTO(t, /* type */ \
|
||||||
|
rs, /* rightshift */ \
|
||||||
|
s, /* size (0 = byte, 1 = short, 2 = long) */ \
|
||||||
|
bs, /* bitsize */ \
|
||||||
|
pr, /* pc_relative */ \
|
||||||
|
bp, /* bitpos */ \
|
||||||
|
co, /* complain_on_overflow */ \
|
||||||
|
bfd_elf_generic_reloc,/* special_function */ \
|
||||||
|
name, /* name */ \
|
||||||
|
FALSE, /* partial_inplace */ \
|
||||||
|
sm, /* src_mask */ \
|
||||||
|
dm, /* dst_mask */ \
|
||||||
|
pr) /* pcrel_offset */
|
||||||
|
|
||||||
|
/* This reloc does nothing. */
|
||||||
|
AHOW (R_EPIPHANY_NONE, 0, 0,32, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_NONE", 0, 0),
|
||||||
|
|
||||||
|
/* 8 bit absolute (not likely) */
|
||||||
|
AHOW (R_EPIPHANY_8, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_8", 0x000000ff, 0x000000ff),
|
||||||
|
/* 16 bit absolute */
|
||||||
|
AHOW (R_EPIPHANY_16, 0, 1,16, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_16", 0x0000ffff, 0x00ff1fe0),
|
||||||
|
/* A 32 bit absolute relocation. */
|
||||||
|
AHOW (R_EPIPHANY_32, 0, 2,32, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_32", 0xffffffff, 0xffffffff),
|
||||||
|
|
||||||
|
/* 8 bit relative relocation */
|
||||||
|
HOWTO ( R_EPIPHANY_8_PCREL, 0, 0, 8, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE),
|
||||||
|
/* 16 bit relative relocation */
|
||||||
|
HOWTO ( R_EPIPHANY_16_PCREL, 0, 1, 16, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE),
|
||||||
|
/* 32 bit relative relocation */
|
||||||
|
HOWTO ( R_EPIPHANY_32_PCREL, 0, 2, 32, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE),
|
||||||
|
|
||||||
|
/* 8 bit pc-relative relocation */
|
||||||
|
AHOW (R_EPIPHANY_SIMM8, 1, 0, 8, TRUE, 8, complain_overflow_signed, "R_EPIPHANY_SIMM8", 0x000000ff, 0x0000ff00),
|
||||||
|
/* 24 bit pc-relative relocation */
|
||||||
|
AHOW (R_EPIPHANY_SIMM24, 1, 2,24, TRUE, 8, complain_overflow_signed, "R_EPIPHANY_SIMM24", 0x00ffffff, 0xffffff00),
|
||||||
|
|
||||||
|
/* %HIGH(EA) */
|
||||||
|
AHOW (R_EPIPHANY_HIGH, 0, 2,16, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_HIGH", 0x0ff01fe0, 0x0ff01fe0),
|
||||||
|
|
||||||
|
/* %LOW(EA) */
|
||||||
|
AHOW (R_EPIPHANY_LOW, 0, 2,16, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_LOW", 0x0ff01fe0, 0x0ff01fe0),
|
||||||
|
|
||||||
|
/* simm11 */
|
||||||
|
AHOW (R_EPIPHANY_SIMM11, 0, 2,11, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_SIMM11", 0x00ff0380, 0x00ff0380),
|
||||||
|
/* imm12 - sign-magnitude */
|
||||||
|
AHOW (R_EPIPHANY_IMM11, 0, 2,11, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_IMM12", 0x00ff0380, 0x00ff0380),
|
||||||
|
/* imm8 */
|
||||||
|
AHOW (R_EPIPHANY_IMM8, 0, 1, 8, FALSE, 8, complain_overflow_signed, "R_EPIPHANY_IMM8", 0x0000ff00, 0x0000ff00)
|
||||||
|
|
||||||
|
|
||||||
|
};
|
||||||
|
#undef AHOW
|
||||||
|
|
||||||
|
/* Map BFD reloc types to EPIPHANY ELF reloc types. */
|
||||||
|
|
||||||
|
static reloc_howto_type *
|
||||||
|
epiphany_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
|
||||||
|
bfd_reloc_code_real_type code)
|
||||||
|
{
|
||||||
|
/* Note that the epiphany_elf_howto_table is indxed by the R_
|
||||||
|
constants. Thus, the order that the howto records appear in the
|
||||||
|
table *must* match the order of the relocation types defined in
|
||||||
|
include/elf/epiphany.h. */
|
||||||
|
|
||||||
|
switch (code)
|
||||||
|
{
|
||||||
|
case BFD_RELOC_NONE:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_NONE];
|
||||||
|
|
||||||
|
case BFD_RELOC_EPIPHANY_SIMM8:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM8];
|
||||||
|
case BFD_RELOC_EPIPHANY_SIMM24:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM24];
|
||||||
|
|
||||||
|
case BFD_RELOC_8_PCREL:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_8_PCREL];
|
||||||
|
case BFD_RELOC_16_PCREL:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_16_PCREL];
|
||||||
|
case BFD_RELOC_32_PCREL:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_32_PCREL];
|
||||||
|
|
||||||
|
case BFD_RELOC_8:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_8];
|
||||||
|
case BFD_RELOC_16:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_16];
|
||||||
|
case BFD_RELOC_32:
|
||||||
|
return &epiphany_elf_howto_table[ (int) R_EPIPHANY_32];
|
||||||
|
|
||||||
|
case BFD_RELOC_EPIPHANY_HIGH:
|
||||||
|
return & epiphany_elf_howto_table[ (int) R_EPIPHANY_HIGH];
|
||||||
|
case BFD_RELOC_EPIPHANY_LOW:
|
||||||
|
return & epiphany_elf_howto_table[ (int) R_EPIPHANY_LOW];
|
||||||
|
|
||||||
|
case BFD_RELOC_EPIPHANY_SIMM11:
|
||||||
|
return & epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM11];
|
||||||
|
case BFD_RELOC_EPIPHANY_IMM11:
|
||||||
|
return & epiphany_elf_howto_table[ (int) R_EPIPHANY_IMM11];
|
||||||
|
|
||||||
|
case BFD_RELOC_EPIPHANY_IMM8:
|
||||||
|
return & epiphany_elf_howto_table[ (int) R_EPIPHANY_IMM8];
|
||||||
|
|
||||||
|
default:
|
||||||
|
/* Pacify gcc -Wall. */
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static reloc_howto_type *
|
||||||
|
epiphany_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE (epiphany_elf_howto_table); i++)
|
||||||
|
if (epiphany_elf_howto_table[i].name != NULL
|
||||||
|
&& strcasecmp (epiphany_elf_howto_table[i].name, r_name) == 0)
|
||||||
|
return &epiphany_elf_howto_table[i];
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PAGENO(ABSADDR) ((ABSADDR) & 0xFFFFC000)
|
||||||
|
#define BASEADDR(SEC) ((SEC)->output_section->vma + (SEC)->output_offset)
|
||||||
|
|
||||||
|
/* This function handles relaxing for the epiphany.
|
||||||
|
Dummy placeholder for future optimizations. */
|
||||||
|
|
||||||
|
static bfd_boolean
|
||||||
|
epiphany_elf_relax_section (bfd *abfd, asection *sec,
|
||||||
|
struct bfd_link_info *link_info,
|
||||||
|
bfd_boolean *again)
|
||||||
|
{
|
||||||
|
Elf_Internal_Shdr *symtab_hdr;
|
||||||
|
Elf_Internal_Rela *internal_relocs;
|
||||||
|
bfd_byte *contents = NULL;
|
||||||
|
Elf_Internal_Sym *isymbuf = NULL;
|
||||||
|
static asection * first_section = NULL;
|
||||||
|
static unsigned long search_addr;
|
||||||
|
static unsigned long page_start = 0;
|
||||||
|
static unsigned long page_end = 0;
|
||||||
|
static unsigned int pass = 0;
|
||||||
|
static bfd_boolean new_pass = FALSE;
|
||||||
|
static bfd_boolean changed = FALSE;
|
||||||
|
struct misc misc ATTRIBUTE_UNUSED;
|
||||||
|
asection *stab;
|
||||||
|
|
||||||
|
/* Assume nothing changes. */
|
||||||
|
*again = FALSE;
|
||||||
|
|
||||||
|
if (first_section == NULL)
|
||||||
|
{
|
||||||
|
epiphany_relaxed = TRUE;
|
||||||
|
first_section = sec;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (first_section == sec)
|
||||||
|
{
|
||||||
|
pass++;
|
||||||
|
new_pass = TRUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* We don't have to do anything for a relocatable link,
|
||||||
|
if this section does not have relocs, or if this is
|
||||||
|
not a code section. */
|
||||||
|
if (link_info->relocatable
|
||||||
|
|| (sec->flags & SEC_RELOC) == 0
|
||||||
|
|| sec->reloc_count == 0
|
||||||
|
|| (sec->flags & SEC_CODE) == 0)
|
||||||
|
return TRUE;
|
||||||
|
|
||||||
|
symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
|
||||||
|
|
||||||
|
internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL,
|
||||||
|
link_info->keep_memory);
|
||||||
|
if (internal_relocs == NULL)
|
||||||
|
goto error_return;
|
||||||
|
|
||||||
|
/* Make sure the stac.rela stuff gets read in. */
|
||||||
|
stab = bfd_get_section_by_name (abfd, ".stab");
|
||||||
|
|
||||||
|
if (stab)
|
||||||
|
{
|
||||||
|
/* So stab does exits. */
|
||||||
|
Elf_Internal_Rela * irelbase ATTRIBUTE_UNUSED;
|
||||||
|
|
||||||
|
irelbase = _bfd_elf_link_read_relocs (abfd, stab, NULL, NULL,
|
||||||
|
link_info->keep_memory);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get section contents cached copy if it exists. */
|
||||||
|
if (contents == NULL)
|
||||||
|
{
|
||||||
|
/* Get cached copy if it exists. */
|
||||||
|
if (elf_section_data (sec)->this_hdr.contents != NULL)
|
||||||
|
contents = elf_section_data (sec)->this_hdr.contents;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Go get them off disk. */
|
||||||
|
if (!bfd_malloc_and_get_section (abfd, sec, &contents))
|
||||||
|
goto error_return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Read this BFD's symbols cached copy if it exists. */
|
||||||
|
if (isymbuf == NULL && symtab_hdr->sh_info != 0)
|
||||||
|
{
|
||||||
|
isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
|
||||||
|
if (isymbuf == NULL)
|
||||||
|
isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
|
||||||
|
symtab_hdr->sh_info, 0,
|
||||||
|
NULL, NULL, NULL);
|
||||||
|
if (isymbuf == NULL)
|
||||||
|
goto error_return;
|
||||||
|
}
|
||||||
|
|
||||||
|
misc.symtab_hdr = symtab_hdr;
|
||||||
|
misc.isymbuf = isymbuf;
|
||||||
|
misc.irelbase = internal_relocs;
|
||||||
|
misc.contents = contents;
|
||||||
|
|
||||||
|
/* This is where all the relaxation actually get done. */
|
||||||
|
if ((pass == 1) || (new_pass && !changed))
|
||||||
|
{
|
||||||
|
/* On the first pass we simply search for the lowest page that
|
||||||
|
we havn't relaxed yet. Note that the pass count is reset
|
||||||
|
each time a page is complete in order to move on to the next page.
|
||||||
|
If we can't find any more pages then we are finished. */
|
||||||
|
if (new_pass)
|
||||||
|
{
|
||||||
|
pass = 1;
|
||||||
|
new_pass = FALSE;
|
||||||
|
changed = TRUE; /* Pre-initialize to break out of pass 1. */
|
||||||
|
search_addr = 0xFFFFFFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((BASEADDR (sec) + sec->size < search_addr)
|
||||||
|
&& (BASEADDR (sec) + sec->size > page_end))
|
||||||
|
{
|
||||||
|
if (BASEADDR (sec) <= page_end)
|
||||||
|
search_addr = page_end + 1;
|
||||||
|
else
|
||||||
|
search_addr = BASEADDR (sec);
|
||||||
|
|
||||||
|
/* Found a page => more work to do. */
|
||||||
|
*again = TRUE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (new_pass)
|
||||||
|
{
|
||||||
|
new_pass = FALSE;
|
||||||
|
changed = FALSE;
|
||||||
|
page_start = PAGENO (search_addr);
|
||||||
|
page_end = page_start | 0x00003FFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Only process sections in range. */
|
||||||
|
if ((BASEADDR (sec) + sec->size >= page_start)
|
||||||
|
&& (BASEADDR (sec) <= page_end))
|
||||||
|
{
|
||||||
|
#if 0
|
||||||
|
if (!epiphany_elf_relax_section_page (abfd, sec, &changed, &misc,
|
||||||
|
page_start, page_end))
|
||||||
|
#endif
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
*again = TRUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Perform some house keeping after relaxing the section. */
|
||||||
|
|
||||||
|
if (isymbuf != NULL
|
||||||
|
&& symtab_hdr->contents != (unsigned char *) isymbuf)
|
||||||
|
{
|
||||||
|
if (! link_info->keep_memory)
|
||||||
|
free (isymbuf);
|
||||||
|
else
|
||||||
|
symtab_hdr->contents = (unsigned char *) isymbuf;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (contents != NULL
|
||||||
|
&& elf_section_data (sec)->this_hdr.contents != contents)
|
||||||
|
{
|
||||||
|
if (! link_info->keep_memory)
|
||||||
|
free (contents);
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Cache the section contents for elf_link_input_bfd. */
|
||||||
|
elf_section_data (sec)->this_hdr.contents = contents;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (internal_relocs != NULL
|
||||||
|
&& elf_section_data (sec)->relocs != internal_relocs)
|
||||||
|
free (internal_relocs);
|
||||||
|
|
||||||
|
return TRUE;
|
||||||
|
|
||||||
|
error_return:
|
||||||
|
if (isymbuf != NULL
|
||||||
|
&& symtab_hdr->contents != (unsigned char *) isymbuf)
|
||||||
|
free (isymbuf);
|
||||||
|
if (contents != NULL
|
||||||
|
&& elf_section_data (sec)->this_hdr.contents != contents)
|
||||||
|
free (contents);
|
||||||
|
if (internal_relocs != NULL
|
||||||
|
&& elf_section_data (sec)->relocs != internal_relocs)
|
||||||
|
free (internal_relocs);
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the howto pointer for a EPIPHANY ELF reloc. */
|
||||||
|
|
||||||
|
static void
|
||||||
|
epiphany_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
|
||||||
|
arelent * cache_ptr,
|
||||||
|
Elf_Internal_Rela * dst)
|
||||||
|
{
|
||||||
|
unsigned int r_type;
|
||||||
|
|
||||||
|
r_type = ELF32_R_TYPE (dst->r_info);
|
||||||
|
cache_ptr->howto = & epiphany_elf_howto_table [r_type];
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Perform a single relocation.
|
||||||
|
By default we use the standard BFD routines. */
|
||||||
|
|
||||||
|
static bfd_reloc_status_type
|
||||||
|
epiphany_final_link_relocate (reloc_howto_type * howto,
|
||||||
|
bfd * input_bfd,
|
||||||
|
asection * input_section,
|
||||||
|
bfd_byte * contents,
|
||||||
|
Elf_Internal_Rela * rel,
|
||||||
|
bfd_vma relocation)
|
||||||
|
{
|
||||||
|
switch (howto->type)
|
||||||
|
{
|
||||||
|
/* Handle 16 bit immediates. */
|
||||||
|
case R_EPIPHANY_HIGH:
|
||||||
|
relocation += rel->r_addend;
|
||||||
|
relocation >>= 16;
|
||||||
|
goto common;
|
||||||
|
|
||||||
|
case R_EPIPHANY_LOW:
|
||||||
|
relocation += rel->r_addend;
|
||||||
|
common:
|
||||||
|
relocation = ((relocation & 0xff00L) << 12)
|
||||||
|
| ((relocation & 0x00ffL) << 5);
|
||||||
|
/* Sanity check the address. */
|
||||||
|
if (rel->r_offset > bfd_get_section_limit (input_bfd, input_section))
|
||||||
|
return bfd_reloc_outofrange;
|
||||||
|
|
||||||
|
return _bfd_relocate_contents (howto, input_bfd, relocation,
|
||||||
|
contents + rel->r_offset);
|
||||||
|
|
||||||
|
case R_EPIPHANY_SIMM11:
|
||||||
|
relocation += rel->r_addend;
|
||||||
|
/* Check signed overflow. */
|
||||||
|
if ((int)relocation > 1023 || (int)relocation < -1024)
|
||||||
|
return bfd_reloc_outofrange;
|
||||||
|
goto disp11;
|
||||||
|
|
||||||
|
case R_EPIPHANY_IMM11:
|
||||||
|
relocation += rel->r_addend;
|
||||||
|
if ((unsigned int) relocation > 0x7ff)
|
||||||
|
return bfd_reloc_outofrange;
|
||||||
|
disp11:
|
||||||
|
relocation = ((relocation & 7) << 5)
|
||||||
|
|| ((relocation & 0x7f8 ) << 13);
|
||||||
|
return _bfd_relocate_contents (howto, input_bfd, relocation,
|
||||||
|
contents + rel->r_offset);
|
||||||
|
|
||||||
|
/* Pass others through. */
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Only install relocation if above tests did not disqualify it. */
|
||||||
|
return _bfd_final_link_relocate (howto, input_bfd, input_section,
|
||||||
|
contents, rel->r_offset,
|
||||||
|
relocation, rel->r_addend);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Relocate an EPIPHANY ELF section.
|
||||||
|
|
||||||
|
The RELOCATE_SECTION function is called by the new ELF backend linker
|
||||||
|
to handle the relocations for a section.
|
||||||
|
|
||||||
|
The relocs are always passed as Rela structures; if the section
|
||||||
|
actually uses Rel structures, the r_addend field will always be
|
||||||
|
zero.
|
||||||
|
|
||||||
|
This function is responsible for adjusting the section contents as
|
||||||
|
necessary, and (if using Rela relocs and generating a relocatable
|
||||||
|
output file) adjusting the reloc addend as necessary.
|
||||||
|
|
||||||
|
This function does not have to worry about setting the reloc
|
||||||
|
address or the reloc symbol index.
|
||||||
|
|
||||||
|
LOCAL_SYMS is a pointer to the swapped in local symbols.
|
||||||
|
|
||||||
|
LOCAL_SECTIONS is an array giving the section in the input file
|
||||||
|
corresponding to the st_shndx field of each local symbol.
|
||||||
|
|
||||||
|
The global hash table entry for the global symbols can be found
|
||||||
|
via elf_sym_hashes (input_bfd).
|
||||||
|
|
||||||
|
When generating relocatable output, this function must handle
|
||||||
|
STB_LOCAL/STT_SECTION symbols specially. The output symbol is
|
||||||
|
going to be the section symbol corresponding to the output
|
||||||
|
section, which means that the addend must be adjusted
|
||||||
|
accordingly. */
|
||||||
|
|
||||||
|
static bfd_boolean
|
||||||
|
epiphany_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
|
||||||
|
struct bfd_link_info *info,
|
||||||
|
bfd *input_bfd,
|
||||||
|
asection *input_section,
|
||||||
|
bfd_byte *contents,
|
||||||
|
Elf_Internal_Rela *relocs,
|
||||||
|
Elf_Internal_Sym *local_syms,
|
||||||
|
asection **local_sections)
|
||||||
|
{
|
||||||
|
Elf_Internal_Shdr *symtab_hdr;
|
||||||
|
struct elf_link_hash_entry **sym_hashes;
|
||||||
|
Elf_Internal_Rela *rel;
|
||||||
|
Elf_Internal_Rela *relend;
|
||||||
|
|
||||||
|
symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
|
||||||
|
sym_hashes = elf_sym_hashes (input_bfd);
|
||||||
|
relend = relocs + input_section->reloc_count;
|
||||||
|
|
||||||
|
for (rel = relocs; rel < relend; rel ++)
|
||||||
|
{
|
||||||
|
reloc_howto_type * howto;
|
||||||
|
unsigned long r_symndx;
|
||||||
|
Elf_Internal_Sym * sym;
|
||||||
|
asection * sec;
|
||||||
|
struct elf_link_hash_entry * h;
|
||||||
|
bfd_vma relocation;
|
||||||
|
bfd_reloc_status_type r;
|
||||||
|
const char * name = NULL;
|
||||||
|
int r_type ATTRIBUTE_UNUSED;
|
||||||
|
|
||||||
|
r_type = ELF32_R_TYPE (rel->r_info);
|
||||||
|
r_symndx = ELF32_R_SYM (rel->r_info);
|
||||||
|
howto = epiphany_elf_howto_table + ELF32_R_TYPE (rel->r_info);
|
||||||
|
h = NULL;
|
||||||
|
sym = NULL;
|
||||||
|
sec = NULL;
|
||||||
|
|
||||||
|
if (r_symndx < symtab_hdr->sh_info)
|
||||||
|
{
|
||||||
|
sym = local_syms + r_symndx;
|
||||||
|
sec = local_sections [r_symndx];
|
||||||
|
relocation = BASEADDR (sec) + sym->st_value;
|
||||||
|
|
||||||
|
name = bfd_elf_string_from_elf_section
|
||||||
|
(input_bfd, symtab_hdr->sh_link, sym->st_name);
|
||||||
|
name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bfd_boolean warned ATTRIBUTE_UNUSED;
|
||||||
|
bfd_boolean unresolved_reloc ATTRIBUTE_UNUSED;
|
||||||
|
|
||||||
|
RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
|
||||||
|
r_symndx, symtab_hdr, sym_hashes,
|
||||||
|
h, sec, relocation,
|
||||||
|
unresolved_reloc, warned);
|
||||||
|
|
||||||
|
name = h->root.root.string;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (sec != NULL && elf_discarded_section (sec))
|
||||||
|
RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
|
||||||
|
rel, relend, howto, contents);
|
||||||
|
|
||||||
|
if (info->relocatable)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* Finally, the sole EPIPHANY-specific part. */
|
||||||
|
r = epiphany_final_link_relocate (howto, input_bfd, input_section,
|
||||||
|
contents, rel, relocation);
|
||||||
|
|
||||||
|
if (r != bfd_reloc_ok)
|
||||||
|
{
|
||||||
|
const char * msg = NULL;
|
||||||
|
|
||||||
|
switch (r)
|
||||||
|
{
|
||||||
|
case bfd_reloc_overflow:
|
||||||
|
r = info->callbacks->reloc_overflow
|
||||||
|
(info, (h ? &h->root : NULL), name, howto->name,
|
||||||
|
(bfd_vma) 0, input_bfd, input_section, rel->r_offset);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case bfd_reloc_undefined:
|
||||||
|
r = info->callbacks->undefined_symbol
|
||||||
|
(info, name, input_bfd, input_section, rel->r_offset, TRUE);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case bfd_reloc_outofrange:
|
||||||
|
msg = _("internal error: out of range error");
|
||||||
|
break;
|
||||||
|
|
||||||
|
/* This is how epiphany_final_link_relocate tells us of a
|
||||||
|
non-kosher reference between insn & data address spaces. */
|
||||||
|
case bfd_reloc_notsupported:
|
||||||
|
if (sym != NULL) /* Only if it's not an unresolved symbol. */
|
||||||
|
msg = _("unsupported relocation between data/insn address spaces");
|
||||||
|
break;
|
||||||
|
|
||||||
|
case bfd_reloc_dangerous:
|
||||||
|
msg = _("internal error: dangerous relocation");
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
msg = _("internal error: unknown error");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (msg)
|
||||||
|
r = info->callbacks->warning
|
||||||
|
(info, msg, name, input_bfd, input_section, rel->r_offset);
|
||||||
|
|
||||||
|
if (! r)
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return TRUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* We only have a little-endian target. */
|
||||||
|
#define TARGET_LITTLE_SYM bfd_elf32_epiphany_vec
|
||||||
|
#define TARGET_LITTLE_NAME "elf32-epiphany"
|
||||||
|
|
||||||
|
#define ELF_ARCH bfd_arch_epiphany
|
||||||
|
#define ELF_MACHINE_CODE EM_ADAPTEVA_EPIPHANY
|
||||||
|
|
||||||
|
#define ELF_MAXPAGESIZE 0x8000 /* No pages on the EPIPHANY. */
|
||||||
|
|
||||||
|
#define elf_info_to_howto_rel NULL
|
||||||
|
#define elf_info_to_howto epiphany_info_to_howto_rela
|
||||||
|
|
||||||
|
#define elf_backend_can_gc_sections 1
|
||||||
|
#define elf_backend_rela_normal 1
|
||||||
|
#define elf_backend_relocate_section epiphany_elf_relocate_section
|
||||||
|
|
||||||
|
#define elf_symbol_leading_char '_'
|
||||||
|
#define bfd_elf32_bfd_reloc_type_lookup epiphany_reloc_type_lookup
|
||||||
|
#define bfd_elf32_bfd_reloc_name_lookup epiphany_reloc_name_lookup
|
||||||
|
#define bfd_elf32_bfd_relax_section epiphany_elf_relax_section
|
||||||
|
|
||||||
|
#include "elf32-target.h"
|
||||||
@ -2476,6 +2476,13 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
|
|||||||
"BFD_RELOC_TILEGX_TLS_DTPMOD32",
|
"BFD_RELOC_TILEGX_TLS_DTPMOD32",
|
||||||
"BFD_RELOC_TILEGX_TLS_DTPOFF32",
|
"BFD_RELOC_TILEGX_TLS_DTPOFF32",
|
||||||
"BFD_RELOC_TILEGX_TLS_TPOFF32",
|
"BFD_RELOC_TILEGX_TLS_TPOFF32",
|
||||||
|
"BFD_RELOC_EPIPHANY_SIMM8",
|
||||||
|
"BFD_RELOC_EPIPHANY_SIMM24",
|
||||||
|
"BFD_RELOC_EPIPHANY_HIGH",
|
||||||
|
"BFD_RELOC_EPIPHANY_LOW",
|
||||||
|
"BFD_RELOC_EPIPHANY_SIMM11",
|
||||||
|
"BFD_RELOC_EPIPHANY_IMM11",
|
||||||
|
"BFD_RELOC_EPIPHANY_IMM8",
|
||||||
"@@overflow: BFD_RELOC_UNUSED@@",
|
"@@overflow: BFD_RELOC_UNUSED@@",
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -73,6 +73,7 @@ cpu-crx.c
|
|||||||
cpu-d10v.c
|
cpu-d10v.c
|
||||||
cpu-d30v.c
|
cpu-d30v.c
|
||||||
cpu-dlx.c
|
cpu-dlx.c
|
||||||
|
cpu-epiphany.c
|
||||||
cpu-fr30.c
|
cpu-fr30.c
|
||||||
cpu-frv.c
|
cpu-frv.c
|
||||||
cpu-h8300.c
|
cpu-h8300.c
|
||||||
@ -85,6 +86,7 @@ cpu-i960.c
|
|||||||
cpu-ia64.c
|
cpu-ia64.c
|
||||||
cpu-ip2k.c
|
cpu-ip2k.c
|
||||||
cpu-iq2000.c
|
cpu-iq2000.c
|
||||||
|
cpu-k1om.c
|
||||||
cpu-l1om.c
|
cpu-l1om.c
|
||||||
cpu-lm32.c
|
cpu-lm32.c
|
||||||
cpu-m10200.c
|
cpu-m10200.c
|
||||||
@ -161,6 +163,7 @@ elf32-crx.c
|
|||||||
elf32-d10v.c
|
elf32-d10v.c
|
||||||
elf32-d30v.c
|
elf32-d30v.c
|
||||||
elf32-dlx.c
|
elf32-dlx.c
|
||||||
|
elf32-epiphany.c
|
||||||
elf32-fr30.c
|
elf32-fr30.c
|
||||||
elf32-frv.c
|
elf32-frv.c
|
||||||
elf32-gen.c
|
elf32-gen.c
|
||||||
|
|||||||
2159
bfd/po/bfd.pot
2159
bfd/po/bfd.pot
File diff suppressed because it is too large
Load Diff
29
bfd/reloc.c
29
bfd/reloc.c
@ -5960,6 +5960,35 @@ ENUMX
|
|||||||
ENUMDOC
|
ENUMDOC
|
||||||
Tilera TILE-Gx Relocations.
|
Tilera TILE-Gx Relocations.
|
||||||
|
|
||||||
|
ENUM
|
||||||
|
BFD_RELOC_EPIPHANY_SIMM8
|
||||||
|
ENUMDOC
|
||||||
|
Adapteva EPIPHANY - 8 bit signed pc-relative displacement
|
||||||
|
ENUM
|
||||||
|
BFD_RELOC_EPIPHANY_SIMM24
|
||||||
|
ENUMDOC
|
||||||
|
Adapteva EPIPHANY - 24 bit signed pc-relative displacement
|
||||||
|
ENUM
|
||||||
|
BFD_RELOC_EPIPHANY_HIGH
|
||||||
|
ENUMDOC
|
||||||
|
Adapteva EPIPHANY - 16 most-significant bits of absolute address
|
||||||
|
ENUM
|
||||||
|
BFD_RELOC_EPIPHANY_LOW
|
||||||
|
ENUMDOC
|
||||||
|
Adapteva EPIPHANY - 16 least-significant bits of absolute address
|
||||||
|
ENUM
|
||||||
|
BFD_RELOC_EPIPHANY_SIMM11
|
||||||
|
ENUMDOC
|
||||||
|
Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
|
||||||
|
ENUM
|
||||||
|
BFD_RELOC_EPIPHANY_IMM11
|
||||||
|
ENUMDOC
|
||||||
|
Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
|
||||||
|
ENUM
|
||||||
|
BFD_RELOC_EPIPHANY_IMM8
|
||||||
|
ENUMDOC
|
||||||
|
Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
|
||||||
|
|
||||||
|
|
||||||
ENDSENUM
|
ENDSENUM
|
||||||
BFD_RELOC_UNUSED
|
BFD_RELOC_UNUSED
|
||||||
|
|||||||
@ -607,6 +607,7 @@ extern const bfd_target bfd_elf32_crx_vec;
|
|||||||
extern const bfd_target bfd_elf32_d10v_vec;
|
extern const bfd_target bfd_elf32_d10v_vec;
|
||||||
extern const bfd_target bfd_elf32_d30v_vec;
|
extern const bfd_target bfd_elf32_d30v_vec;
|
||||||
extern const bfd_target bfd_elf32_dlx_big_vec;
|
extern const bfd_target bfd_elf32_dlx_big_vec;
|
||||||
|
extern const bfd_target bfd_elf32_epiphany_vec;
|
||||||
extern const bfd_target bfd_elf32_fr30_vec;
|
extern const bfd_target bfd_elf32_fr30_vec;
|
||||||
extern const bfd_target bfd_elf32_frv_vec;
|
extern const bfd_target bfd_elf32_frv_vec;
|
||||||
extern const bfd_target bfd_elf32_frvfdpic_vec;
|
extern const bfd_target bfd_elf32_frvfdpic_vec;
|
||||||
@ -968,6 +969,7 @@ static const bfd_target * const _bfd_target_vector[] =
|
|||||||
&bfd_elf32_d10v_vec,
|
&bfd_elf32_d10v_vec,
|
||||||
&bfd_elf32_d30v_vec,
|
&bfd_elf32_d30v_vec,
|
||||||
&bfd_elf32_dlx_big_vec,
|
&bfd_elf32_dlx_big_vec,
|
||||||
|
&bfd_elf32_epiphany_vec,
|
||||||
&bfd_elf32_fr30_vec,
|
&bfd_elf32_fr30_vec,
|
||||||
&bfd_elf32_frv_vec,
|
&bfd_elf32_frv_vec,
|
||||||
&bfd_elf32_frvfdpic_vec,
|
&bfd_elf32_frvfdpic_vec,
|
||||||
|
|||||||
@ -1,3 +1,11 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* readelf.c: Include "elf/epiphany.h".
|
||||||
|
(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
|
||||||
|
(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
|
||||||
|
(is_16bit_abs_reloc, is_none_reloc): Likewise.
|
||||||
|
* po/binutils.pot: Regenerate.
|
||||||
|
|
||||||
2011-10-25 Kai Tietz <ktietz@redhat.com>
|
2011-10-25 Kai Tietz <ktietz@redhat.com>
|
||||||
|
|
||||||
* winduni.h (unicode_from_ascii_len): New prototype.
|
* winduni.h (unicode_from_ascii_len): New prototype.
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@ -103,6 +103,7 @@
|
|||||||
#include "elf/d10v.h"
|
#include "elf/d10v.h"
|
||||||
#include "elf/d30v.h"
|
#include "elf/d30v.h"
|
||||||
#include "elf/dlx.h"
|
#include "elf/dlx.h"
|
||||||
|
#include "elf/epiphany.h"
|
||||||
#include "elf/fr30.h"
|
#include "elf/fr30.h"
|
||||||
#include "elf/frv.h"
|
#include "elf/frv.h"
|
||||||
#include "elf/h8.h"
|
#include "elf/h8.h"
|
||||||
@ -552,6 +553,7 @@ guess_is_rela (unsigned int e_machine)
|
|||||||
/* Targets that use RELA relocations. */
|
/* Targets that use RELA relocations. */
|
||||||
case EM_68K:
|
case EM_68K:
|
||||||
case EM_860:
|
case EM_860:
|
||||||
|
case EM_ADAPTEVA_EPIPHANY:
|
||||||
case EM_ALPHA:
|
case EM_ALPHA:
|
||||||
case EM_ALTERA_NIOS2:
|
case EM_ALTERA_NIOS2:
|
||||||
case EM_AVR:
|
case EM_AVR:
|
||||||
@ -1168,6 +1170,10 @@ dump_relocations (FILE * file,
|
|||||||
rtype = elf_vax_reloc_type (type);
|
rtype = elf_vax_reloc_type (type);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case EM_ADAPTEVA_EPIPHANY:
|
||||||
|
rtype = elf_epiphany_reloc_type (type);
|
||||||
|
break;
|
||||||
|
|
||||||
case EM_IP2K:
|
case EM_IP2K:
|
||||||
case EM_IP2K_OLD:
|
case EM_IP2K_OLD:
|
||||||
rtype = elf_ip2k_reloc_type (type);
|
rtype = elf_ip2k_reloc_type (type);
|
||||||
@ -1911,6 +1917,7 @@ get_machine_name (unsigned e_machine)
|
|||||||
case EM_OR32: return "OpenRISC";
|
case EM_OR32: return "OpenRISC";
|
||||||
case EM_ARC_A5: return "ARC International ARCompact processor";
|
case EM_ARC_A5: return "ARC International ARCompact processor";
|
||||||
case EM_CRX: return "National Semiconductor CRX microprocessor";
|
case EM_CRX: return "National Semiconductor CRX microprocessor";
|
||||||
|
case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY";
|
||||||
case EM_DLX: return "OpenDLX";
|
case EM_DLX: return "OpenDLX";
|
||||||
case EM_IP2K_OLD:
|
case EM_IP2K_OLD:
|
||||||
case EM_IP2K: return "Ubicom IP2xxx 8-bit microcontrollers";
|
case EM_IP2K: return "Ubicom IP2xxx 8-bit microcontrollers";
|
||||||
@ -9680,6 +9687,8 @@ is_32bit_abs_reloc (unsigned int reloc_type)
|
|||||||
case EM_AVR_OLD:
|
case EM_AVR_OLD:
|
||||||
case EM_AVR:
|
case EM_AVR:
|
||||||
return reloc_type == 1;
|
return reloc_type == 1;
|
||||||
|
case EM_ADAPTEVA_EPIPHANY:
|
||||||
|
return reloc_type == 3;
|
||||||
case EM_BLACKFIN:
|
case EM_BLACKFIN:
|
||||||
return reloc_type == 0x12; /* R_byte4_data. */
|
return reloc_type == 0x12; /* R_byte4_data. */
|
||||||
case EM_CRIS:
|
case EM_CRIS:
|
||||||
@ -9820,6 +9829,8 @@ is_32bit_pcrel_reloc (unsigned int reloc_type)
|
|||||||
return reloc_type == 2; /* R_386_PC32. */
|
return reloc_type == 2; /* R_386_PC32. */
|
||||||
case EM_68K:
|
case EM_68K:
|
||||||
return reloc_type == 4; /* R_68K_PC32. */
|
return reloc_type == 4; /* R_68K_PC32. */
|
||||||
|
case EM_ADAPTEVA_EPIPHANY:
|
||||||
|
return reloc_type == 6;
|
||||||
case EM_ALPHA:
|
case EM_ALPHA:
|
||||||
return reloc_type == 10; /* R_ALPHA_SREL32. */
|
return reloc_type == 10; /* R_ALPHA_SREL32. */
|
||||||
case EM_ARM:
|
case EM_ARM:
|
||||||
@ -9961,6 +9972,8 @@ is_16bit_abs_reloc (unsigned int reloc_type)
|
|||||||
case EM_AVR_OLD:
|
case EM_AVR_OLD:
|
||||||
case EM_AVR:
|
case EM_AVR:
|
||||||
return reloc_type == 4; /* R_AVR_16. */
|
return reloc_type == 4; /* R_AVR_16. */
|
||||||
|
case EM_ADAPTEVA_EPIPHANY:
|
||||||
|
return reloc_type == 5;
|
||||||
case EM_CYGNUS_D10V:
|
case EM_CYGNUS_D10V:
|
||||||
case EM_D10V:
|
case EM_D10V:
|
||||||
return reloc_type == 3; /* R_D10V_16. */
|
return reloc_type == 3; /* R_D10V_16. */
|
||||||
@ -10006,6 +10019,7 @@ is_none_reloc (unsigned int reloc_type)
|
|||||||
case EM_MIPS: /* R_MIPS_NONE. */
|
case EM_MIPS: /* R_MIPS_NONE. */
|
||||||
case EM_PARISC: /* R_PARISC_NONE. */
|
case EM_PARISC: /* R_PARISC_NONE. */
|
||||||
case EM_ALPHA: /* R_ALPHA_NONE. */
|
case EM_ALPHA: /* R_ALPHA_NONE. */
|
||||||
|
case EM_ADAPTEVA_EPIPHANY:
|
||||||
case EM_PPC: /* R_PPC_NONE. */
|
case EM_PPC: /* R_PPC_NONE. */
|
||||||
case EM_PPC64: /* R_PPC64_NONE. */
|
case EM_PPC64: /* R_PPC64_NONE. */
|
||||||
case EM_ARM: /* R_ARM_NONE. */
|
case EM_ARM: /* R_ARM_NONE. */
|
||||||
|
|||||||
@ -1,3 +1,8 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* cpu/epiphany.cpu: New file.
|
||||||
|
* cpu/epiphany.opc: New file.
|
||||||
|
|
||||||
2011-08-22 Nick Clifton <nickc@redhat.com>
|
2011-08-22 Nick Clifton <nickc@redhat.com>
|
||||||
|
|
||||||
* fr30.cpu: Newly contributed file.
|
* fr30.cpu: Newly contributed file.
|
||||||
|
|||||||
2935
cpu/epiphany.cpu
Normal file
2935
cpu/epiphany.cpu
Normal file
File diff suppressed because it is too large
Load Diff
416
cpu/epiphany.opc
Executable file
416
cpu/epiphany.opc
Executable file
@ -0,0 +1,416 @@
|
|||||||
|
/* Adapteva epiphany opcode support. -*- C -*-
|
||||||
|
|
||||||
|
Copyright 2011 Free Software Foundation, Inc.
|
||||||
|
|
||||||
|
Contributed by Embecosm on behalf of Adapteva, Inc.
|
||||||
|
|
||||||
|
This file is part of the GNU Binutils and of GDB.
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
This program is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program; if not, write to the Free Software
|
||||||
|
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||||
|
MA 02110-1301, USA. */
|
||||||
|
|
||||||
|
/*
|
||||||
|
Each section is delimited with start and end markers.
|
||||||
|
|
||||||
|
<arch>-opc.h additions use: "-- opc.h"
|
||||||
|
<arch>-opc.c additions use: "-- opc.c"
|
||||||
|
<arch>-asm.c additions use: "-- asm.c"
|
||||||
|
<arch>-dis.c additions use: "-- dis.c"
|
||||||
|
<arch>-ibd.h additions use: "-- ibd.h". */
|
||||||
|
|
||||||
|
/* -- opc.h */
|
||||||
|
|
||||||
|
/* enumerate relaxation types for gas. */
|
||||||
|
typedef enum epiphany_relax_types
|
||||||
|
{
|
||||||
|
EPIPHANY_RELAX_NONE=0,
|
||||||
|
EPIPHANY_RELAX_NEED_RELAXING,
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */
|
||||||
|
EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */
|
||||||
|
EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */
|
||||||
|
EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */
|
||||||
|
EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */
|
||||||
|
|
||||||
|
} EPIPHANY_RELAX_TYPES;
|
||||||
|
|
||||||
|
/* Override disassembly hashing... */
|
||||||
|
|
||||||
|
/* Can only depend on instruction having 4 decode bits which gets us to the
|
||||||
|
major groups of 16/32 instructions. */
|
||||||
|
#undef CGEN_DIS_HASH_SIZE
|
||||||
|
#if 1
|
||||||
|
|
||||||
|
/* hash code on the 4 LSBs */
|
||||||
|
#define CGEN_DIS_HASH_SIZE 16
|
||||||
|
|
||||||
|
#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf)
|
||||||
|
#else
|
||||||
|
#define CGEN_DIS_HASH_SIZE 1
|
||||||
|
#define CGEN_DIS_HASH(buf, value) 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern const char * parse_shortregs (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
CGEN_KEYWORD * keywords,
|
||||||
|
long * valuep);
|
||||||
|
|
||||||
|
extern const char * parse_branch_addr (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
int opinfo,
|
||||||
|
enum cgen_parse_operand_result * resultp,
|
||||||
|
unsigned long * valuep);
|
||||||
|
|
||||||
|
/* Allows reason codes to be output when assembler errors occur. */
|
||||||
|
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||||||
|
|
||||||
|
|
||||||
|
/* -- opc.c */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* -- asm.c */
|
||||||
|
const char *
|
||||||
|
parse_shortregs (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
CGEN_KEYWORD * keywords,
|
||||||
|
long * regno)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
|
||||||
|
/* Parse register. */
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, keywords, regno);
|
||||||
|
|
||||||
|
if (errmsg)
|
||||||
|
return errmsg;
|
||||||
|
|
||||||
|
if (*regno > 7)
|
||||||
|
errmsg = _("register unavailable for short instructions");
|
||||||
|
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int,
|
||||||
|
long *);
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_uimm_not_reg (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
unsigned long * valuep)
|
||||||
|
{
|
||||||
|
long * svalp = (void *) valuep;
|
||||||
|
return parse_simm_not_reg (cd, strp, opindex, svalp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Handle simm3/simm11/imm3/imm12. */
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_simm_not_reg (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
long * valuep)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
|
||||||
|
int sign = 0;
|
||||||
|
int bits = 0;
|
||||||
|
|
||||||
|
switch (opindex)
|
||||||
|
{
|
||||||
|
case EPIPHANY_OPERAND_SIMM3:
|
||||||
|
sign = 1; bits = 3; break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM11:
|
||||||
|
sign = 1; bits = 11; break;
|
||||||
|
case EPIPHANY_OPERAND_DISP3:
|
||||||
|
sign = 0; bits = 3; break;
|
||||||
|
case EPIPHANY_OPERAND_DISP11:
|
||||||
|
/* Load/store displacement is a sign-magnitude 12 bit value. */
|
||||||
|
sign = 0; bits = 11; break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* First try to parse as a register name and reject the operand. */
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep);
|
||||||
|
if (!errmsg)
|
||||||
|
return _("register name used as immediate value");
|
||||||
|
|
||||||
|
errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep)
|
||||||
|
: cgen_parse_unsigned_integer (cd, strp, opindex,
|
||||||
|
(unsigned long *) valuep));
|
||||||
|
if (errmsg)
|
||||||
|
return errmsg;
|
||||||
|
|
||||||
|
if (sign)
|
||||||
|
errmsg = cgen_validate_signed_integer (*valuep,
|
||||||
|
-((1L << bits) - 1), (1 << (bits - 1)) - 1);
|
||||||
|
else
|
||||||
|
errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1);
|
||||||
|
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma * valuep)
|
||||||
|
{
|
||||||
|
if (**strp == '#')
|
||||||
|
++*strp; /* Skip leading hashes. */
|
||||||
|
|
||||||
|
if (**strp == '-')
|
||||||
|
{
|
||||||
|
*valuep = 1;
|
||||||
|
++*strp;
|
||||||
|
}
|
||||||
|
else if (**strp == '+')
|
||||||
|
{
|
||||||
|
*valuep = 0;
|
||||||
|
++*strp;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
*valuep = 0;
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_imm8 (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
bfd_reloc_code_real_type code,
|
||||||
|
enum cgen_parse_operand_result * result_type,
|
||||||
|
bfd_vma * valuep)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
enum cgen_parse_operand_result rt;
|
||||||
|
long dummyval;
|
||||||
|
|
||||||
|
if (!result_type)
|
||||||
|
result_type = &rt;
|
||||||
|
|
||||||
|
code = BFD_RELOC_NONE;
|
||||||
|
|
||||||
|
if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval)
|
||||||
|
|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
|
||||||
|
&dummyval))
|
||||||
|
/* Don't treat "mov ip,ip" as a move-immediate. */
|
||||||
|
return _("register source in immediate move");
|
||||||
|
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep);
|
||||||
|
if (errmsg)
|
||||||
|
return errmsg;
|
||||||
|
|
||||||
|
if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||||
|
errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff);
|
||||||
|
else
|
||||||
|
errmsg = _("byte relocation unsupported");
|
||||||
|
|
||||||
|
*valuep &= 0xff;
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'");
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_imm16 (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
bfd_reloc_code_real_type code ATTRIBUTE_UNUSED,
|
||||||
|
enum cgen_parse_operand_result * result_type,
|
||||||
|
bfd_vma * valuep)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
enum cgen_parse_operand_result rt;
|
||||||
|
long dummyval;
|
||||||
|
|
||||||
|
if (!result_type)
|
||||||
|
result_type = &rt;
|
||||||
|
|
||||||
|
if (strncasecmp (*strp, "%high(", 6) == 0)
|
||||||
|
{
|
||||||
|
*strp += 6;
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH,
|
||||||
|
result_type, valuep);
|
||||||
|
if (**strp != ')')
|
||||||
|
return MISSING_CLOSE_PARENTHESIS;
|
||||||
|
++*strp;
|
||||||
|
*valuep >>= 16;
|
||||||
|
}
|
||||||
|
else if (strncasecmp (*strp, "%low(", 5) == 0)
|
||||||
|
{
|
||||||
|
*strp += 5;
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW,
|
||||||
|
result_type, valuep);
|
||||||
|
if (**strp != ')')
|
||||||
|
return MISSING_CLOSE_PARENTHESIS;
|
||||||
|
++*strp;
|
||||||
|
}
|
||||||
|
else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names,
|
||||||
|
&dummyval)
|
||||||
|
|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
|
||||||
|
&dummyval))
|
||||||
|
/* Don't treat "mov ip,ip" as a move-immediate. */
|
||||||
|
return _("register source in immediate move");
|
||||||
|
else
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
|
||||||
|
result_type, valuep);
|
||||||
|
|
||||||
|
if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||||
|
errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff);
|
||||||
|
|
||||||
|
*valuep &= 0xffff;
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
const char *
|
||||||
|
parse_branch_addr (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
int opinfo ATTRIBUTE_UNUSED,
|
||||||
|
enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED,
|
||||||
|
unsigned long * valuep ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
enum cgen_parse_operand_result result_type;
|
||||||
|
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
|
||||||
|
bfd_vma value;
|
||||||
|
|
||||||
|
switch (opindex)
|
||||||
|
{
|
||||||
|
case EPIPHANY_OPERAND_SIMM24:
|
||||||
|
code = BFD_RELOC_EPIPHANY_SIMM24;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EPIPHANY_OPERAND_SIMM8:
|
||||||
|
code = BFD_RELOC_EPIPHANY_SIMM8;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
errmsg = _("ABORT: unknown operand");
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, code,
|
||||||
|
&result_type, &value);
|
||||||
|
if (errmsg == NULL)
|
||||||
|
{
|
||||||
|
if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||||
|
{
|
||||||
|
/* Act as if we had done a PC-relative branch, ala .+num. */
|
||||||
|
char buf[20];
|
||||||
|
const char * bufp = (const char *) buf;
|
||||||
|
|
||||||
|
sprintf (buf, ".+%ld", value);
|
||||||
|
errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type,
|
||||||
|
&value);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
|
||||||
|
{
|
||||||
|
/* This will happen for things like (s2-s1) where s2 and s1
|
||||||
|
are labels. */
|
||||||
|
/* Nothing further to be done. */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
errmsg = _("Not a pc-relative address.");
|
||||||
|
}
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* -- dis.c */
|
||||||
|
|
||||||
|
#define CGEN_PRINT_INSN epiphany_print_insn
|
||||||
|
|
||||||
|
static int
|
||||||
|
epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||||
|
{
|
||||||
|
bfd_byte buf[CGEN_MAX_INSN_SIZE];
|
||||||
|
int buflen;
|
||||||
|
int status;
|
||||||
|
|
||||||
|
info->bytes_per_chunk = 2;
|
||||||
|
|
||||||
|
/* Attempt to read the base part of the insn. */
|
||||||
|
info->bytes_per_line = buflen = cd->base_insn_bitsize / 8;
|
||||||
|
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||||
|
|
||||||
|
/* Try again with the minimum part, if min < base. */
|
||||||
|
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
|
||||||
|
{
|
||||||
|
info->bytes_per_line = buflen = cd->min_insn_bitsize / 8;
|
||||||
|
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status != 0)
|
||||||
|
{
|
||||||
|
(*info->memory_error_func) (status, pc, info);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return print_insn (cd, pc, info, buf, buflen);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void * dis_info,
|
||||||
|
long value,
|
||||||
|
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *) dis_info;
|
||||||
|
(*info->fprintf_func) (info->stream, value ? "-" : "+");
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void * dis_info,
|
||||||
|
long value,
|
||||||
|
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
print_address (cd, dis_info, value, attrs, pc, length);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void * dis_info,
|
||||||
|
unsigned long value,
|
||||||
|
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *)dis_info;
|
||||||
|
|
||||||
|
if (value & 0x800)
|
||||||
|
(*info->fprintf_func) (info->stream, "-");
|
||||||
|
|
||||||
|
value &= 0x7ff;
|
||||||
|
print_address (cd, dis_info, value, attrs, pc, length);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* -- */
|
||||||
|
|
||||||
@ -1,3 +1,22 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* NEWS: Mention addition of Adapteva Epiphany support.
|
||||||
|
* config/tc-epiphany.c: New file.
|
||||||
|
* config/tc-epiphany.h: New file.
|
||||||
|
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
|
||||||
|
(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
|
||||||
|
* configure.in: Also set using_cgen for epiphany.
|
||||||
|
* configure.tgt: Handle epiphany.
|
||||||
|
* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
|
||||||
|
* doc/all.texi: Set EPIPHANY.
|
||||||
|
* doc/as.texinfo: Add EPIPHANY-specific text.
|
||||||
|
* doc/c-epiphany.texi: New file.
|
||||||
|
* po/gas.pot: Regenerate.
|
||||||
|
* Makefile.in: Regenerate.
|
||||||
|
* configure: Regenerate.
|
||||||
|
* doc/Makefile.in: Regenerate.
|
||||||
|
* po/POTFILES.in: Regenerate.
|
||||||
|
|
||||||
2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
|
2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
|
||||||
|
|
||||||
* config/tc-mips.c (move_register): Fix formatting.
|
* config/tc-mips.c (move_register): Fix formatting.
|
||||||
|
|||||||
@ -118,6 +118,7 @@ TARGET_CPU_CFILES = \
|
|||||||
config/tc-d10v.c \
|
config/tc-d10v.c \
|
||||||
config/tc-d30v.c \
|
config/tc-d30v.c \
|
||||||
config/tc-dlx.c \
|
config/tc-dlx.c \
|
||||||
|
config/tc-epiphany.c \
|
||||||
config/tc-fr30.c \
|
config/tc-fr30.c \
|
||||||
config/tc-frv.c \
|
config/tc-frv.c \
|
||||||
config/tc-h8300.c \
|
config/tc-h8300.c \
|
||||||
@ -184,6 +185,7 @@ TARGET_CPU_HFILES = \
|
|||||||
config/tc-d10v.h \
|
config/tc-d10v.h \
|
||||||
config/tc-d30v.h \
|
config/tc-d30v.h \
|
||||||
config/tc-dlx.h \
|
config/tc-dlx.h \
|
||||||
|
config/tc-epiphany.h \
|
||||||
config/tc-fr30.h \
|
config/tc-fr30.h \
|
||||||
config/tc-frv.h \
|
config/tc-frv.h \
|
||||||
config/tc-h8300.h \
|
config/tc-h8300.h \
|
||||||
|
|||||||
@ -385,6 +385,7 @@ TARGET_CPU_CFILES = \
|
|||||||
config/tc-d10v.c \
|
config/tc-d10v.c \
|
||||||
config/tc-d30v.c \
|
config/tc-d30v.c \
|
||||||
config/tc-dlx.c \
|
config/tc-dlx.c \
|
||||||
|
config/tc-epiphany.c \
|
||||||
config/tc-fr30.c \
|
config/tc-fr30.c \
|
||||||
config/tc-frv.c \
|
config/tc-frv.c \
|
||||||
config/tc-h8300.c \
|
config/tc-h8300.c \
|
||||||
@ -451,6 +452,7 @@ TARGET_CPU_HFILES = \
|
|||||||
config/tc-d10v.h \
|
config/tc-d10v.h \
|
||||||
config/tc-d30v.h \
|
config/tc-d30v.h \
|
||||||
config/tc-dlx.h \
|
config/tc-dlx.h \
|
||||||
|
config/tc-epiphany.h \
|
||||||
config/tc-fr30.h \
|
config/tc-fr30.h \
|
||||||
config/tc-frv.h \
|
config/tc-frv.h \
|
||||||
config/tc-h8300.h \
|
config/tc-h8300.h \
|
||||||
@ -796,6 +798,7 @@ distclean-compile:
|
|||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-d10v.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-d10v.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-d30v.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-d30v.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-dlx.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-dlx.Po@am__quote@
|
||||||
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-epiphany.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-fr30.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-fr30.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-frv.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-frv.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-h8300.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-h8300.Po@am__quote@
|
||||||
@ -1027,6 +1030,20 @@ tc-dlx.obj: config/tc-dlx.c
|
|||||||
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
|
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
|
||||||
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-dlx.obj `if test -f 'config/tc-dlx.c'; then $(CYGPATH_W) 'config/tc-dlx.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-dlx.c'; fi`
|
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-dlx.obj `if test -f 'config/tc-dlx.c'; then $(CYGPATH_W) 'config/tc-dlx.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-dlx.c'; fi`
|
||||||
|
|
||||||
|
tc-epiphany.o: config/tc-epiphany.c
|
||||||
|
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-epiphany.o -MD -MP -MF $(DEPDIR)/tc-epiphany.Tpo -c -o tc-epiphany.o `test -f 'config/tc-epiphany.c' || echo '$(srcdir)/'`config/tc-epiphany.c
|
||||||
|
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-epiphany.Tpo $(DEPDIR)/tc-epiphany.Po
|
||||||
|
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-epiphany.c' object='tc-epiphany.o' libtool=no @AMDEPBACKSLASH@
|
||||||
|
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
|
||||||
|
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-epiphany.o `test -f 'config/tc-epiphany.c' || echo '$(srcdir)/'`config/tc-epiphany.c
|
||||||
|
|
||||||
|
tc-epiphany.obj: config/tc-epiphany.c
|
||||||
|
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-epiphany.obj -MD -MP -MF $(DEPDIR)/tc-epiphany.Tpo -c -o tc-epiphany.obj `if test -f 'config/tc-epiphany.c'; then $(CYGPATH_W) 'config/tc-epiphany.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-epiphany.c'; fi`
|
||||||
|
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-epiphany.Tpo $(DEPDIR)/tc-epiphany.Po
|
||||||
|
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-epiphany.c' object='tc-epiphany.obj' libtool=no @AMDEPBACKSLASH@
|
||||||
|
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
|
||||||
|
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-epiphany.obj `if test -f 'config/tc-epiphany.c'; then $(CYGPATH_W) 'config/tc-epiphany.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-epiphany.c'; fi`
|
||||||
|
|
||||||
tc-fr30.o: config/tc-fr30.c
|
tc-fr30.o: config/tc-fr30.c
|
||||||
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-fr30.o -MD -MP -MF $(DEPDIR)/tc-fr30.Tpo -c -o tc-fr30.o `test -f 'config/tc-fr30.c' || echo '$(srcdir)/'`config/tc-fr30.c
|
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-fr30.o -MD -MP -MF $(DEPDIR)/tc-fr30.Tpo -c -o tc-fr30.o `test -f 'config/tc-fr30.c' || echo '$(srcdir)/'`config/tc-fr30.c
|
||||||
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-fr30.Tpo $(DEPDIR)/tc-fr30.Po
|
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-fr30.Tpo $(DEPDIR)/tc-fr30.Po
|
||||||
|
|||||||
2
gas/NEWS
2
gas/NEWS
@ -1,5 +1,7 @@
|
|||||||
-*- text -*-
|
-*- text -*-
|
||||||
|
|
||||||
|
* Add support for the Adapteva EPIPHANY architecture.
|
||||||
|
|
||||||
Changes in 2.22:
|
Changes in 2.22:
|
||||||
|
|
||||||
* Add support for the Tilera TILEPRO and TILE-Gx architectures.
|
* Add support for the Tilera TILEPRO and TILE-Gx architectures.
|
||||||
|
|||||||
1110
gas/config/tc-epiphany.c
Executable file
1110
gas/config/tc-epiphany.c
Executable file
File diff suppressed because it is too large
Load Diff
102
gas/config/tc-epiphany.h
Executable file
102
gas/config/tc-epiphany.h
Executable file
@ -0,0 +1,102 @@
|
|||||||
|
/* tc-epiphany.h -- Header file for tc-epiphany.c.
|
||||||
|
Copyright 2011 Free Software Foundation, Inc.
|
||||||
|
Contributed by Embecosm on behalf of Adapteva, Inc.
|
||||||
|
|
||||||
|
This file is part of GAS, the GNU Assembler.
|
||||||
|
|
||||||
|
GAS is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3, or (at your option)
|
||||||
|
any later version.
|
||||||
|
|
||||||
|
GAS is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with GAS; see the file COPYING. If not, write to the Free
|
||||||
|
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||||
|
02110-1301, USA. */
|
||||||
|
|
||||||
|
#define TC_EPIPHANY
|
||||||
|
|
||||||
|
#define LISTING_HEADER "EPIPHANY GAS "
|
||||||
|
|
||||||
|
/* The target BFD architecture. */
|
||||||
|
#define TARGET_ARCH bfd_arch_epiphany
|
||||||
|
|
||||||
|
#define TARGET_FORMAT "elf32-epiphany"
|
||||||
|
|
||||||
|
/* Permit temporary numeric labels. */
|
||||||
|
#define LOCAL_LABELS_FB 1
|
||||||
|
|
||||||
|
/* .-foo gets turned into PC relative relocs. */
|
||||||
|
#define DIFF_EXPR_OK
|
||||||
|
|
||||||
|
/* We don't need to handle .word strangely. */
|
||||||
|
#define WORKING_DOT_WORD
|
||||||
|
|
||||||
|
#define LITERAL_PREFIXDOLLAR_HEX
|
||||||
|
#define LITERAL_PREFIXPERCENT_BIN
|
||||||
|
#define DOUBLESLASH_LINE_COMMENTS
|
||||||
|
|
||||||
|
#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)
|
||||||
|
|
||||||
|
/* Values passed to md_apply_fix don't include the symbol value. */
|
||||||
|
#define MD_APPLY_SYM_VALUE(FIX) 0
|
||||||
|
|
||||||
|
#define tc_fix_adjustable(FIX) epiphany_fix_adjustable (FIX)
|
||||||
|
extern bfd_boolean epiphany_fix_adjustable (struct fix *);
|
||||||
|
|
||||||
|
extern long md_pcrel_from_section (struct fix *, segT);
|
||||||
|
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP,SEC)
|
||||||
|
|
||||||
|
#define TC_HANDLES_FX_DONE
|
||||||
|
|
||||||
|
#define elf_tc_final_processing epiphany_elf_final_processing
|
||||||
|
extern void epiphany_elf_final_processing (void);
|
||||||
|
|
||||||
|
#define md_elf_section_flags epiphany_elf_section_flags
|
||||||
|
extern int epiphany_elf_section_flags (int, int, int);
|
||||||
|
|
||||||
|
#define md_operand(x) epiphany_cgen_md_operand (x)
|
||||||
|
extern void epiphany_cgen_md_operand (expressionS *);
|
||||||
|
|
||||||
|
/* Values passed to md_apply_fix don't include the symbol value. */
|
||||||
|
#define MD_APPLY_SYM_VALUE(FIX) 0
|
||||||
|
|
||||||
|
#define TC_CGEN_MAX_RELAX(insn, len) 4
|
||||||
|
|
||||||
|
#define O_PIC_reloc O_md1
|
||||||
|
|
||||||
|
#define TC_CGEN_PARSE_FIX_EXP(opinfo, exp) \
|
||||||
|
epiphany_cgen_parse_fix_exp (opinfo, exp)
|
||||||
|
extern int epiphany_cgen_parse_fix_exp (int, expressionS *);
|
||||||
|
|
||||||
|
#define HANDLE_ALIGN(f) epiphany_handle_align (f)
|
||||||
|
extern void epiphany_handle_align (fragS *);
|
||||||
|
|
||||||
|
#define TARGET_FORMAT "elf32-epiphany"
|
||||||
|
|
||||||
|
#define md_relax_frag epiphany_relax_frag
|
||||||
|
|
||||||
|
extern long epiphany_relax_frag (segT, fragS *, long);
|
||||||
|
|
||||||
|
/* If you don't define md_relax_frag, md_cgen_record_fixup_exp
|
||||||
|
but do have TC_GENERIC_RELAX_TABLE gas will do the relaxation for you.
|
||||||
|
|
||||||
|
If we have to add support for %LO and %HI relocations, we probably need
|
||||||
|
to define the fixup_exp function to generate fancier relocations. */
|
||||||
|
|
||||||
|
/* For 8 vs 24 bit branch selection. */
|
||||||
|
extern const struct relax_type md_relax_table[];
|
||||||
|
#define TC_GENERIC_RELAX_TABLE md_relax_table
|
||||||
|
|
||||||
|
#define tc_gen_reloc gas_cgen_tc_gen_reloc
|
||||||
|
|
||||||
|
|
||||||
|
#define md_apply_fix epiphany_apply_fix
|
||||||
|
#include "write.h"
|
||||||
|
|
||||||
|
extern void epiphany_apply_fix (fixS *fixP, valueT *valP, segT seg);
|
||||||
2
gas/configure
vendored
2
gas/configure
vendored
@ -12143,7 +12143,7 @@ _ACEOF
|
|||||||
fi
|
fi
|
||||||
;;
|
;;
|
||||||
|
|
||||||
fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
|
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
|
||||||
using_cgen=yes
|
using_cgen=yes
|
||||||
;;
|
;;
|
||||||
|
|
||||||
|
|||||||
@ -305,7 +305,7 @@ changequote([,])dnl
|
|||||||
fi
|
fi
|
||||||
;;
|
;;
|
||||||
|
|
||||||
fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
|
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc)
|
||||||
using_cgen=yes
|
using_cgen=yes
|
||||||
;;
|
;;
|
||||||
|
|
||||||
|
|||||||
@ -38,6 +38,7 @@ case ${cpu} in
|
|||||||
cr16*) cpu_type=cr16 endian=little ;;
|
cr16*) cpu_type=cr16 endian=little ;;
|
||||||
crisv32) cpu_type=cris arch=crisv32 ;;
|
crisv32) cpu_type=cris arch=crisv32 ;;
|
||||||
crx*) cpu_type=crx endian=little ;;
|
crx*) cpu_type=crx endian=little ;;
|
||||||
|
epiphany*) cpu_type=epiphany endian=little ;;
|
||||||
fido) cpu_type=m68k ;;
|
fido) cpu_type=m68k ;;
|
||||||
hppa*) cpu_type=hppa ;;
|
hppa*) cpu_type=hppa ;;
|
||||||
i[3-7]86) cpu_type=i386 arch=i386;;
|
i[3-7]86) cpu_type=i386 arch=i386;;
|
||||||
@ -141,6 +142,8 @@ case ${generic_target} in
|
|||||||
d30v-*-*) fmt=elf ;;
|
d30v-*-*) fmt=elf ;;
|
||||||
dlx-*-*) fmt=elf ;;
|
dlx-*-*) fmt=elf ;;
|
||||||
|
|
||||||
|
epiphany-*-*) fmt=elf ;;
|
||||||
|
|
||||||
fr30-*-*) fmt=elf ;;
|
fr30-*-*) fmt=elf ;;
|
||||||
frv-*-*linux*) fmt=elf em=linux;;
|
frv-*-*linux*) fmt=elf em=linux;;
|
||||||
frv-*-*) fmt=elf ;;
|
frv-*-*) fmt=elf ;;
|
||||||
|
|||||||
@ -35,8 +35,9 @@ CPU_DOCS = \
|
|||||||
c-avr.texi \
|
c-avr.texi \
|
||||||
c-bfin.texi \
|
c-bfin.texi \
|
||||||
c-cr16.texi \
|
c-cr16.texi \
|
||||||
c-d10v.texi \
|
|
||||||
c-cris.texi \
|
c-cris.texi \
|
||||||
|
c-d10v.texi \
|
||||||
|
c-epiphany.texi \
|
||||||
c-h8300.texi \
|
c-h8300.texi \
|
||||||
c-hppa.texi \
|
c-hppa.texi \
|
||||||
c-i370.texi \
|
c-i370.texi \
|
||||||
|
|||||||
@ -275,8 +275,9 @@ CPU_DOCS = \
|
|||||||
c-avr.texi \
|
c-avr.texi \
|
||||||
c-bfin.texi \
|
c-bfin.texi \
|
||||||
c-cr16.texi \
|
c-cr16.texi \
|
||||||
c-d10v.texi \
|
|
||||||
c-cris.texi \
|
c-cris.texi \
|
||||||
|
c-d10v.texi \
|
||||||
|
c-epiphany.texi \
|
||||||
c-h8300.texi \
|
c-h8300.texi \
|
||||||
c-hppa.texi \
|
c-hppa.texi \
|
||||||
c-i370.texi \
|
c-i370.texi \
|
||||||
|
|||||||
@ -35,6 +35,7 @@
|
|||||||
@set CRIS
|
@set CRIS
|
||||||
@set D10V
|
@set D10V
|
||||||
@set D30V
|
@set D30V
|
||||||
|
@set EPIPHANY
|
||||||
@set H8/300
|
@set H8/300
|
||||||
@set HPPA
|
@set HPPA
|
||||||
@set I370
|
@set I370
|
||||||
|
|||||||
@ -307,6 +307,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
|
|||||||
@emph{Target D30V options:}
|
@emph{Target D30V options:}
|
||||||
[@b{-O}|@b{-n}|@b{-N}]
|
[@b{-O}|@b{-n}|@b{-N}]
|
||||||
@end ifset
|
@end ifset
|
||||||
|
@ifset EPIPHANY
|
||||||
|
|
||||||
|
@emph{Target EPIPHANY options:}
|
||||||
|
[@b{-mepiphany}|@b{-mepiphany16}]
|
||||||
|
@end ifset
|
||||||
@ifset H8
|
@ifset H8
|
||||||
|
|
||||||
@emph{Target H8/300 options:}
|
@emph{Target H8/300 options:}
|
||||||
@ -843,6 +848,22 @@ Warn when a nop after a 32-bit multiply instruction is generated.
|
|||||||
@end ifset
|
@end ifset
|
||||||
@c man end
|
@c man end
|
||||||
|
|
||||||
|
@ifset EPIPHANY
|
||||||
|
The following options are available when @value{AS} is configured for the
|
||||||
|
Adapteva EPIPHANY series.
|
||||||
|
|
||||||
|
@table @gcctabopt
|
||||||
|
|
||||||
|
@item -mepiphany
|
||||||
|
Specifies that the both 32 and 16 bit instructions are allowed. This is the
|
||||||
|
default behavior.
|
||||||
|
|
||||||
|
@item -mepiphany16
|
||||||
|
Restricts the permitted instructions to just the 16 bit set.
|
||||||
|
|
||||||
|
@end table
|
||||||
|
@end ifset
|
||||||
|
|
||||||
@ifset I80386
|
@ifset I80386
|
||||||
|
|
||||||
@ifclear man
|
@ifclear man
|
||||||
@ -6849,6 +6870,9 @@ subject, see the hardware manufacturer's manual.
|
|||||||
@ifset D30V
|
@ifset D30V
|
||||||
* D30V-Dependent:: D30V Dependent Features
|
* D30V-Dependent:: D30V Dependent Features
|
||||||
@end ifset
|
@end ifset
|
||||||
|
@ifset EPIPHANY
|
||||||
|
* Epiphany-Dependent:: EPIPHANY Dependent Features
|
||||||
|
@end ifset
|
||||||
@ifset H8/300
|
@ifset H8/300
|
||||||
* H8/300-Dependent:: Renesas H8/300 Dependent Features
|
* H8/300-Dependent:: Renesas H8/300 Dependent Features
|
||||||
@end ifset
|
@end ifset
|
||||||
@ -7025,6 +7049,10 @@ family.
|
|||||||
@include c-d30v.texi
|
@include c-d30v.texi
|
||||||
@end ifset
|
@end ifset
|
||||||
|
|
||||||
|
@ifset EPIPHANY
|
||||||
|
@include c-epiphany.texi
|
||||||
|
@end ifset
|
||||||
|
|
||||||
@ifset H8/300
|
@ifset H8/300
|
||||||
@include c-h8300.texi
|
@include c-h8300.texi
|
||||||
@end ifset
|
@end ifset
|
||||||
|
|||||||
67
gas/doc/c-epiphany.texi
Normal file
67
gas/doc/c-epiphany.texi
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
@c Copyright 2011 Free Software Foundation, Inc.
|
||||||
|
@c This is part of the GAS manual.
|
||||||
|
@c For copying conditions, see the file as.texinfo.
|
||||||
|
@c man end
|
||||||
|
|
||||||
|
@ifset GENERIC
|
||||||
|
@page
|
||||||
|
@node Epiphany-Dependent
|
||||||
|
@chapter Epiphany Dependent Features
|
||||||
|
@end ifset
|
||||||
|
@ifclear GENERIC
|
||||||
|
@node Machine Dependencies
|
||||||
|
@chapter Epiphany Dependent Features
|
||||||
|
@end ifclear
|
||||||
|
|
||||||
|
@cindex Epiphany support
|
||||||
|
@menu
|
||||||
|
* Epiphany Options:: Options
|
||||||
|
* Epiphany Syntax:: Epiphany Syntax
|
||||||
|
@end menu
|
||||||
|
|
||||||
|
@node Epiphany Options
|
||||||
|
@section Options
|
||||||
|
|
||||||
|
@cindex Epiphany options
|
||||||
|
@cindex options, Epiphany
|
||||||
|
@code{@value{AS}} has two additional command-line options for the Epiphany
|
||||||
|
architecture.
|
||||||
|
|
||||||
|
@c man begin OPTIONS
|
||||||
|
@table @gcctabopt
|
||||||
|
|
||||||
|
@cindex @code{-mepiphany} command line option, Epiphany
|
||||||
|
@item -mepiphany
|
||||||
|
Specifies that the both 32 and 16 bit instructions are allowed. This is the
|
||||||
|
default behavior.
|
||||||
|
|
||||||
|
@cindex @code{-mepiphany16} command line option, Epiphany
|
||||||
|
@item -mepiphany16
|
||||||
|
Restricts the permitted instructions to just the 16 bit set.
|
||||||
|
@end table
|
||||||
|
@c man end
|
||||||
|
|
||||||
|
@node Epiphany Syntax
|
||||||
|
@section Epiphany Syntax
|
||||||
|
@menu
|
||||||
|
* Epiphany-Chars:: Special Characters
|
||||||
|
@end menu
|
||||||
|
|
||||||
|
@node Epiphany-Chars
|
||||||
|
@subsection Special Characters
|
||||||
|
|
||||||
|
@cindex line comment character, Epiphany
|
||||||
|
@cindex Epiphany line comment character
|
||||||
|
The presence of a @samp{;} on a line indicates the start
|
||||||
|
of a comment that extends to the end of the current line.
|
||||||
|
|
||||||
|
If a @samp{#} appears as the first character of a line then the whole
|
||||||
|
line is treated as a comment, but in this case the line could also be
|
||||||
|
a logical line number directive (@pxref{Comments}) or a preprocessor
|
||||||
|
control command (@pxref{Preprocessing}).
|
||||||
|
|
||||||
|
@cindex line separator, Epiphany
|
||||||
|
@cindex statement separator, Epiphany
|
||||||
|
@cindex Epiphany line separator
|
||||||
|
The @samp{`} character can be used to separate statements on the same
|
||||||
|
line.
|
||||||
@ -59,6 +59,8 @@ config/tc-d30v.c
|
|||||||
config/tc-d30v.h
|
config/tc-d30v.h
|
||||||
config/tc-dlx.c
|
config/tc-dlx.c
|
||||||
config/tc-dlx.h
|
config/tc-dlx.h
|
||||||
|
config/tc-epiphany.c
|
||||||
|
config/tc-epiphany.h
|
||||||
config/tc-fr30.c
|
config/tc-fr30.c
|
||||||
config/tc-fr30.h
|
config/tc-fr30.h
|
||||||
config/tc-frv.c
|
config/tc-frv.c
|
||||||
|
|||||||
3080
gas/po/gas.pot
3080
gas/po/gas.pot
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,21 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* gas/epiphany: New directory.
|
||||||
|
* gas/testsuite/gas/epiphany/addr-syntax.d: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/addr-syntax.s: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/allinsn.d: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/allinsn.exp: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/allinsn.s: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/badpostmod.s: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/badrelax.d: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/badrelax.s: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/branch_lit.d: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/branch_lit.s: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/regression.d: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/regression.s: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/sample.d: New file.
|
||||||
|
* gas/testsuite/gas/epiphany/sample.s: New file.
|
||||||
|
|
||||||
2011-10-24 Julian Brown <julian@codesourcery.com>
|
2011-10-24 Julian Brown <julian@codesourcery.com>
|
||||||
|
|
||||||
* gas/m68k/all.exp (movem-offset): Add test.
|
* gas/m68k/all.exp (movem-offset): Add test.
|
||||||
|
|||||||
15
gas/testsuite/gas/epiphany/addr-syntax.d
Normal file
15
gas/testsuite/gas/epiphany/addr-syntax.d
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
#as:
|
||||||
|
#objdump: -dr
|
||||||
|
#name: addr-syntax
|
||||||
|
|
||||||
|
.*.o: file format elf32-epiphany
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section \.text:
|
||||||
|
|
||||||
|
00000000 \<\.text\>:
|
||||||
|
0: 2bcc 01ff ldr.l r1,\[r2,-0x7ff\]
|
||||||
|
4: 4c4c 0301 ldr.l r2,\[r3\],-0x8
|
||||||
|
8: 107c 2201 strd.l r8,\[r4\],\+0x8
|
||||||
|
c: 506c 2400 ldrd sl,\[ip\]
|
||||||
|
10: 587c 2400 strd sl,\[lr\]
|
||||||
9
gas/testsuite/gas/epiphany/addr-syntax.s
Normal file
9
gas/testsuite/gas/epiphany/addr-syntax.s
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
; Check that we can do negative displacements
|
||||||
|
ldr r1,[r2,-2047]
|
||||||
|
; Check postmodified immediate with positive and negative displacements
|
||||||
|
ldr r2,[r3],-8
|
||||||
|
strd r8,[r4],8
|
||||||
|
|
||||||
|
; Check that zero displacements work
|
||||||
|
ldrd r10,[r12]
|
||||||
|
strd r10,[r14]
|
||||||
1400
gas/testsuite/gas/epiphany/allinsn.d
Normal file
1400
gas/testsuite/gas/epiphany/allinsn.d
Normal file
File diff suppressed because it is too large
Load Diff
11
gas/testsuite/gas/epiphany/allinsn.exp
Normal file
11
gas/testsuite/gas/epiphany/allinsn.exp
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
# EPIPHANY assembler testsuite. -*- Tcl -*-
|
||||||
|
|
||||||
|
if [istarget epiphany*-*-*] {
|
||||||
|
run_dump_test "allinsn"
|
||||||
|
run_dump_test "regression"
|
||||||
|
run_dump_test "sample"
|
||||||
|
run_dump_test "branch_lit"
|
||||||
|
run_dump_test "badrelax"
|
||||||
|
gas_test_error "badpostmod" "" "destination register modified by displacement-post-modified address"
|
||||||
|
run_dump_test "addr-syntax"
|
||||||
|
}
|
||||||
1563
gas/testsuite/gas/epiphany/allinsn.s
Normal file
1563
gas/testsuite/gas/epiphany/allinsn.s
Normal file
File diff suppressed because it is too large
Load Diff
14
gas/testsuite/gas/epiphany/badpostmod.s
Normal file
14
gas/testsuite/gas/epiphany/badpostmod.s
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
.text
|
||||||
|
.global postmod
|
||||||
|
postmod:
|
||||||
|
ldrd r0,[r1],r2 ; tricky because r1 is implied as destination
|
||||||
|
|
||||||
|
strb r12,[r12],r3 ; stores are okay
|
||||||
|
strd r12,[r13],r3
|
||||||
|
|
||||||
|
ldr r0,[r0],r0 ; ERROR
|
||||||
|
|
||||||
|
ldr r0,[r0,+128] ; ok
|
||||||
|
ldrd r12,[r13],-256 ; ERROR
|
||||||
|
ldrb r12,[r12],20 ; ERROR
|
||||||
|
strd r12,[r13],-256 ; ok
|
||||||
12
gas/testsuite/gas/epiphany/badrelax.d
Normal file
12
gas/testsuite/gas/epiphany/badrelax.d
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
#as:
|
||||||
|
#objdump: -dr
|
||||||
|
#name: badrelax
|
||||||
|
|
||||||
|
.*\.o: file format elf32-epiphany
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section \.text:
|
||||||
|
|
||||||
|
00000000 \<xxx\>:
|
||||||
|
0: 01f0 bl 2 \<xxx\+0x2\>
|
||||||
|
2: 013b 0000 sub r0,r0,2
|
||||||
5
gas/testsuite/gas/epiphany/badrelax.s
Normal file
5
gas/testsuite/gas/epiphany/badrelax.s
Normal file
@ -0,0 +1,5 @@
|
|||||||
|
.text
|
||||||
|
.global xxx
|
||||||
|
xxx:
|
||||||
|
bl 1f
|
||||||
|
1: sub r0,r0,1b-xxx
|
||||||
11
gas/testsuite/gas/epiphany/branch_lit.d
Normal file
11
gas/testsuite/gas/epiphany/branch_lit.d
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
#as:
|
||||||
|
#objdump: -dr
|
||||||
|
#name: branch_lit
|
||||||
|
|
||||||
|
.*.o: file format elf32-epiphany
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section \.text:
|
||||||
|
|
||||||
|
00000000 \<\.text\>:
|
||||||
|
0: 8008 0000 beq 0x100
|
||||||
1
gas/testsuite/gas/epiphany/branch_lit.s
Normal file
1
gas/testsuite/gas/epiphany/branch_lit.s
Normal file
@ -0,0 +1 @@
|
|||||||
|
beq 256
|
||||||
300
gas/testsuite/gas/epiphany/regression.d
Normal file
300
gas/testsuite/gas/epiphany/regression.d
Normal file
@ -0,0 +1,300 @@
|
|||||||
|
#as:
|
||||||
|
#objdump: -dr
|
||||||
|
#name: regression
|
||||||
|
|
||||||
|
.*\.o: file format elf32-epiphany
|
||||||
|
|
||||||
|
|
||||||
|
Disassembly of section \.text:
|
||||||
|
|
||||||
|
00000000 \<START\>:
|
||||||
|
0: 000b 0802 mov r0,0x8000
|
||||||
|
4: 0056 lsl r0,r0,0x2
|
||||||
|
6: c0c3 mov r6,0x6
|
||||||
|
8: 6063 mov r3,0x3
|
||||||
|
a: ff1f fc0a add.l r63,r63,r6
|
||||||
|
e: fd1f fc0a add.l r63,r63,r2
|
||||||
|
12: dc0b e072 mov r62,0x7e0
|
||||||
|
16: ff3f ff8a sub.l r63,r63,r62
|
||||||
|
1a: 0300 beq 20 \<BRANCH1\>
|
||||||
|
1c: 0023 mov r0,0x1
|
||||||
|
1e: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000020 \<BRANCH1\>:
|
||||||
|
20: 0900 beq 32 \<BRANCH2\>
|
||||||
|
22: 0023 mov r0,0x1
|
||||||
|
24: 0fe2 trap 0x3
|
||||||
|
26: 0023 mov r0,0x1
|
||||||
|
28: 0fe2 trap 0x3
|
||||||
|
2a: 0023 mov r0,0x1
|
||||||
|
2c: 0fe2 trap 0x3
|
||||||
|
2e: 0023 mov r0,0x1
|
||||||
|
30: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000032 \<BRANCH2\>:
|
||||||
|
32: 1c10 bne 6a \<FAIL_BRANCH\>
|
||||||
|
|
||||||
|
00000034 \<BRANCH3\>:
|
||||||
|
34: 1b60 bgt 6a \<FAIL_BRANCH\>
|
||||||
|
|
||||||
|
00000036 \<BRANCH4\>:
|
||||||
|
36: 0370 bgte 3c \<BRANCH5\>
|
||||||
|
38: 0023 mov r0,0x1
|
||||||
|
3a: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000003c \<BRANCH5\>:
|
||||||
|
3c: 0390 blte 42 \<BRANCH6\>
|
||||||
|
3e: 0023 mov r0,0x1
|
||||||
|
40: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000042 \<BRANCH6\>:
|
||||||
|
42: 1480 blt 6a \<FAIL_BRANCH\>
|
||||||
|
|
||||||
|
00000044 \<BRANCH8\>:
|
||||||
|
44: efe8 0000 b 222 \<LONGJUMP\>
|
||||||
|
48: 0023 mov r0,0x1
|
||||||
|
4a: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000004c \<RETURN\>:
|
||||||
|
4c: edf8 0000 bl 226 \<FUNCTION\>
|
||||||
|
50: e00b e002 mov r63,0x0
|
||||||
|
50: R_EPIPHANY_LOW \.text\+0x5c
|
||||||
|
54: 1d4f 1c02 jr r63
|
||||||
|
58: 0023 mov r0,0x1
|
||||||
|
5a: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000005c \<JARLAB\>:
|
||||||
|
5c: e00b e002 mov r63,0x0
|
||||||
|
5c: R_EPIPHANY_LOW \.text\+0x226
|
||||||
|
60: 1d5f 1c02 jalr r63
|
||||||
|
64: 05e0 b 6e \<NEXT\>
|
||||||
|
66: 0023 mov r0,0x1
|
||||||
|
68: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000006a \<FAIL_BRANCH\>:
|
||||||
|
6a: 0023 mov r0,0x1
|
||||||
|
6c: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000006e \<NEXT\>:
|
||||||
|
6e: 8014 strb r4,\[r0\]
|
||||||
|
70: e00c e000 ldrb r63,\[r0\]
|
||||||
|
74: fe3f fc0a sub.l r63,r63,r4
|
||||||
|
78: 0300 beq 7e \<STOREB\>
|
||||||
|
7a: 0023 mov r0,0x1
|
||||||
|
7c: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000007e \<STOREB\>:
|
||||||
|
7e: a39c 0001 strb.l r5,\[r0,\+0xf\]
|
||||||
|
82: e38c e001 ldrb.l r63,\[r0,\+0xf\]
|
||||||
|
86: febf fc0a sub.l r63,r63,r5
|
||||||
|
8a: 0300 beq 90 \<STORES\>
|
||||||
|
8c: 0023 mov r0,0x1
|
||||||
|
8e: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000090 \<STORES\>:
|
||||||
|
90: 8034 strh r4,\[r0\]
|
||||||
|
92: e02c e000 ldrh r63,\[r0\]
|
||||||
|
96: fe3f fc0a sub.l r63,r63,r4
|
||||||
|
9a: 0300 beq a0 \<STORES2\>
|
||||||
|
9c: 0023 mov r0,0x1
|
||||||
|
9e: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000000a0 \<STORES2\>:
|
||||||
|
a0: a33c 0001 strh.l r5,\[r0,\+0xe\]
|
||||||
|
a4: e32c e001 ldrh.l r63,\[r0,\+0xe\]
|
||||||
|
a8: febf fc0a sub.l r63,r63,r5
|
||||||
|
ac: 0300 beq b2 \<STORE\>
|
||||||
|
ae: 0023 mov r0,0x1
|
||||||
|
b0: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000000b2 \<STORE\>:
|
||||||
|
b2: 8054 str r4,\[r0\]
|
||||||
|
b4: e04c e000 ldr r63,\[r0\]
|
||||||
|
b8: fe3f fc0a sub.l r63,r63,r4
|
||||||
|
bc: 0300 beq c2 \<STORE2\>
|
||||||
|
be: 0023 mov r0,0x1
|
||||||
|
c0: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000000c2 \<STORE2\>:
|
||||||
|
c2: a25c 0001 str.l r5,\[r0,\+0xc\]
|
||||||
|
c6: e24c e001 ldr.l r63,\[r0,\+0xc\]
|
||||||
|
ca: febf fc0a sub.l r63,r63,r5
|
||||||
|
ce: 0300 beq d4 \<STOREBI\>
|
||||||
|
d0: 0023 mov r0,0x1
|
||||||
|
d2: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000000d4 \<STOREBI\>:
|
||||||
|
d4: 8211 strb r4,\[r0,r4\]
|
||||||
|
d6: e209 e000 ldrb.l r63,\[r0,\+r4\]
|
||||||
|
da: fe3f fc0a sub.l r63,r63,r4
|
||||||
|
de: 0300 beq e4 \<STORESI\>
|
||||||
|
e0: 0023 mov r0,0x1
|
||||||
|
e2: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000000e4 \<STORESI\>:
|
||||||
|
e4: a231 strh r5,\[r0,r4\]
|
||||||
|
e6: e229 e000 ldrh.l r63,\[r0,\+r4\]
|
||||||
|
ea: febf fc0a sub.l r63,r63,r5
|
||||||
|
ee: 0300 beq f4 \<STOREI\>
|
||||||
|
f0: 0023 mov r0,0x1
|
||||||
|
f2: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000000f4 \<STOREI\>:
|
||||||
|
f4: c251 str r6,\[r0,r4\]
|
||||||
|
f6: e249 e000 ldr.l r63,\[r0,\+r4\]
|
||||||
|
fa: ff3f fc0a sub.l r63,r63,r6
|
||||||
|
fe: 0300 beq 104 \<PMB\>
|
||||||
|
100: 0023 mov r0,0x1
|
||||||
|
102: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000104 \<PMB\>:
|
||||||
|
104: 8215 strb r4,\[r0\],r4
|
||||||
|
106: 023b 0000 sub r0,r0,4
|
||||||
|
10a: e20d e000 ldrb.l r63,\[r0\],\+r4
|
||||||
|
10e: 023b 0000 sub r0,r0,4
|
||||||
|
112: fe3f fc0a sub.l r63,r63,r4
|
||||||
|
116: 0300 beq 11c \<PMS\>
|
||||||
|
118: 0023 mov r0,0x1
|
||||||
|
11a: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000011c \<PMS\>:
|
||||||
|
11c: a235 strh r5,\[r0\],r4
|
||||||
|
11e: 023b 0000 sub r0,r0,4
|
||||||
|
122: e22d e000 ldrh.l r63,\[r0\],\+r4
|
||||||
|
126: febf fc0a sub.l r63,r63,r5
|
||||||
|
12a: 0300 beq 130 \<PM\>
|
||||||
|
12c: 0023 mov r0,0x1
|
||||||
|
12e: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000130 \<PM\>:
|
||||||
|
130: 023b 0000 sub r0,r0,4
|
||||||
|
134: c255 str r6,\[r0\],r4
|
||||||
|
136: 023b 0000 sub r0,r0,4
|
||||||
|
13a: e24d e000 ldr.l r63,\[r0\],\+r4
|
||||||
|
13e: 023b 0000 sub r0,r0,4
|
||||||
|
142: ff3f fc0a sub.l r63,r63,r6
|
||||||
|
146: 0300 beq 14c \<MOVLAB\>
|
||||||
|
148: 0023 mov r0,0x1
|
||||||
|
14a: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000014c \<MOVLAB\>:
|
||||||
|
14c: ffeb e002 mov r63,0xff
|
||||||
|
150: 3fe3 mov r1,0xff
|
||||||
|
152: fcbf fc0a sub.l r63,r63,r1
|
||||||
|
156: 0300 beq 15c \<ADDLAB\>
|
||||||
|
158: 0023 mov r0,0x1
|
||||||
|
15a: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000015c \<ADDLAB\>:
|
||||||
|
15c: e99b e000 add r63,r2,3
|
||||||
|
160: febb fc00 sub r63,r63,5
|
||||||
|
164: 0300 beq 16a \<SUBLAB\>
|
||||||
|
166: 0023 mov r0,0x1
|
||||||
|
168: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000016a \<SUBLAB\>:
|
||||||
|
16a: e8bb e000 sub r63,r2,1
|
||||||
|
16e: fcbb fc00 sub r63,r63,1
|
||||||
|
172: 0300 beq 178 \<LSRLAB\>
|
||||||
|
174: 0023 mov r0,0x1
|
||||||
|
176: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000178 \<LSRLAB\>:
|
||||||
|
178: f84f e006 lsr.l r63,r6,0x2
|
||||||
|
17c: fcbb fc00 sub r63,r63,1
|
||||||
|
180: 0300 beq 186 \<LSLLAB\>
|
||||||
|
182: 0023 mov r0,0x1
|
||||||
|
184: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000186 \<LSLLAB\>:
|
||||||
|
186: ec5f e006 lsl.l r63,r3,0x2
|
||||||
|
18a: fe3b fc01 sub r63,r63,12
|
||||||
|
18e: 0300 beq 194 \<LSRILAB\>
|
||||||
|
190: 0023 mov r0,0x1
|
||||||
|
192: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
00000194 \<LSRILAB\>:
|
||||||
|
194: f94f e00a lsr.l r63,r6,r2
|
||||||
|
198: fcbb fc00 sub r63,r63,1
|
||||||
|
19c: 0300 beq 1a2 \<LSLILAB\>
|
||||||
|
19e: 0023 mov r0,0x1
|
||||||
|
1a0: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001a2 \<LSLILAB\>:
|
||||||
|
1a2: ed2f e00a lsl.l r63,r3,r2
|
||||||
|
1a6: fe3b fc01 sub r63,r63,12
|
||||||
|
1aa: 0300 beq 1b0 \<ORRLAB\>
|
||||||
|
1ac: 0023 mov r0,0x1
|
||||||
|
1ae: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001b0 \<ORRLAB\>:
|
||||||
|
1b0: ae7a orr r5,r3,r4
|
||||||
|
1b2: f7bb e000 sub r63,r5,7
|
||||||
|
1b6: 0300 beq 1bc \<ANDLAB\>
|
||||||
|
1b8: 0023 mov r0,0x1
|
||||||
|
1ba: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001bc \<ANDLAB\>:
|
||||||
|
1bc: ae5a and r5,r3,r4
|
||||||
|
1be: f43b e000 sub r63,r5,0
|
||||||
|
1c2: 0300 beq 1c8 \<EORLAB\>
|
||||||
|
1c4: 0023 mov r0,0x1
|
||||||
|
1c6: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001c8 \<EORLAB\>:
|
||||||
|
1c8: ad0a eor r5,r3,r2
|
||||||
|
1ca: f4bb e000 sub r63,r5,1
|
||||||
|
1ce: 0300 beq 1d4 \<ADD3LAB\>
|
||||||
|
1d0: 0023 mov r0,0x1
|
||||||
|
1d2: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001d4 \<ADD3LAB\>:
|
||||||
|
1d4: e99f e00a add.l r63,r2,r3
|
||||||
|
1d8: febb fc00 sub r63,r63,5
|
||||||
|
1dc: 0300 beq 1e2 \<SUB3LAB\>
|
||||||
|
1de: 0023 mov r0,0x1
|
||||||
|
1e0: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001e2 \<SUB3LAB\>:
|
||||||
|
1e2: fa3f e00a sub.l r63,r6,r4
|
||||||
|
1e6: fd3b fc00 sub r63,r63,2
|
||||||
|
1ea: 0300 beq 1f0 \<MOVRLAB\>
|
||||||
|
1ec: 0023 mov r0,0x1
|
||||||
|
1ee: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001f0 \<MOVRLAB\>:
|
||||||
|
1f0: e8ef e002 mov.l r63,r2
|
||||||
|
1f4: fd3b fc00 sub r63,r63,2
|
||||||
|
1f8: 0b00 beq 20e \<NOPLAB\>
|
||||||
|
1fa: 0023 mov r0,0x1
|
||||||
|
1fc: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
000001fe \<MOVTFLAB\>:
|
||||||
|
1fe: 0502 movts status,r0
|
||||||
|
200: e51f e002 movfs.l r63,status
|
||||||
|
204: fc3f fc0a sub.l r63,r63,r0
|
||||||
|
208: fb00 beq 1fe \<MOVTFLAB\>
|
||||||
|
20a: 0023 mov r0,0x1
|
||||||
|
20c: 0fe2 trap 0x3
|
||||||
|
|
||||||
|
0000020e \<NOPLAB\>:
|
||||||
|
20e: 01a2 nop
|
||||||
|
210: 01a2 nop
|
||||||
|
212: 01a2 nop
|
||||||
|
214: 01a2 nop
|
||||||
|
|
||||||
|
00000216 \<PASSED\>:
|
||||||
|
216: 0003 mov r0,0x0
|
||||||
|
218: 0fe2 trap 0x3
|
||||||
|
21a: 01b2 idle
|
||||||
|
|
||||||
|
0000021c \<FAILED\>:
|
||||||
|
21c: 0023 mov r0,0x1
|
||||||
|
21e: 0fe2 trap 0x3
|
||||||
|
220: 01b2 idle
|
||||||
|
|
||||||
|
00000222 \<LONGJUMP\>:
|
||||||
|
222: 15e8 ffff b 4c \<RETURN\>
|
||||||
|
|
||||||
|
00000226 \<FUNCTION\>:
|
||||||
|
226: 194f 0402 rts
|
||||||
240
gas/testsuite/gas/epiphany/regression.s
Normal file
240
gas/testsuite/gas/epiphany/regression.s
Normal file
@ -0,0 +1,240 @@
|
|||||||
|
;; -*-asm-*-
|
||||||
|
|
||||||
|
TABLE=0x8000
|
||||||
|
RZ=r63
|
||||||
|
|
||||||
|
.macro FAIL
|
||||||
|
mov r0,#1
|
||||||
|
trap 3
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro PASS
|
||||||
|
mov r0,#0
|
||||||
|
trap 3
|
||||||
|
.endm
|
||||||
|
|
||||||
|
|
||||||
|
.macro VERIFY ra,rb,ref,label
|
||||||
|
sub \ra,\rb,\ref
|
||||||
|
beq \label
|
||||||
|
FAIL
|
||||||
|
.endm
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*INITIALIZING REGISTERS */
|
||||||
|
/*****************************************/
|
||||||
|
/*Check that sum is correct*/
|
||||||
|
START: MOV R0, #TABLE ; //Setting R0 to TABLE
|
||||||
|
LSL R0,R0,#2 ; //Create 00020000
|
||||||
|
|
||||||
|
;; Load r1.63 with 1..63
|
||||||
|
.irpc num,63
|
||||||
|
mov r\num,#\num
|
||||||
|
.endr
|
||||||
|
|
||||||
|
|
||||||
|
;; Sum the registers
|
||||||
|
.irpc num,62
|
||||||
|
add r63,r63,r\num
|
||||||
|
.endr
|
||||||
|
|
||||||
|
mov r62,#2016 ;//Correct sum of 1..63 = 63*32 + 63
|
||||||
|
VERIFY r63,r63,R62,BRANCH1;//CHECK SUM
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*BRANCHING */
|
||||||
|
/*****************************************/
|
||||||
|
//Check that all condition codes work
|
||||||
|
BRANCH1: BEQ BRANCH2 ; //taken
|
||||||
|
FAIL ;
|
||||||
|
FAIL ;
|
||||||
|
FAIL ;
|
||||||
|
FAIL ;
|
||||||
|
BRANCH2: BNE FAIL_BRANCH ; //not taken
|
||||||
|
BRANCH3: BGT FAIL_BRANCH ; //not taken
|
||||||
|
BRANCH4: BGTE BRANCH5 ; //taken
|
||||||
|
FAIL ;
|
||||||
|
BRANCH5: BLTE BRANCH6 ; //taken
|
||||||
|
FAIL ;
|
||||||
|
BRANCH6: BLT FAIL_BRANCH ; //not taken
|
||||||
|
BRANCH8: B LONGJUMP ; //taken
|
||||||
|
FAIL ;
|
||||||
|
RETURN: bl FUNCTION ; //jump to subroutine
|
||||||
|
MOV R63,JARLAB ;//REGISTER JUMP
|
||||||
|
JR R63 ;
|
||||||
|
FAIL ;
|
||||||
|
JARLAB: MOV R63,FUNCTION ; //REGISTER CALL
|
||||||
|
JALR R63 ; //16 bit
|
||||||
|
B NEXT ; //jump over fail
|
||||||
|
FAIL ;
|
||||||
|
|
||||||
|
FAIL_BRANCH: FAIL ; //fail branch
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*LOAD-STORE DISPLACEMENT */
|
||||||
|
/*****************************************/
|
||||||
|
//Check max displacement value(0xf)
|
||||||
|
//Check that offset is correct
|
||||||
|
//all load/stores are aligned
|
||||||
|
//this gives greater range(2 more bits)
|
||||||
|
//offset is shifted by 2x bits
|
||||||
|
|
||||||
|
NEXT: STRB R4,[R0,#0x0] ;//Store Byte
|
||||||
|
LDRB R63,[R0,#0x0] ;//Load Byte
|
||||||
|
VERIFY R63,R63,R4,STOREB ;
|
||||||
|
|
||||||
|
STOREB: STRB R5,[R0,#0xf] ;//Store Byte
|
||||||
|
LDRB R63,[R0,#0xf] ;//Load Byte
|
||||||
|
VERIFY R63,R63,R5,STORES ;
|
||||||
|
|
||||||
|
STORES: STRH R4,[R0,#0x0] ;//Store Short
|
||||||
|
LDRH R63,[R0,#0x0] ;//Load Short
|
||||||
|
VERIFY R63,R63,R4,STORES2 ;
|
||||||
|
|
||||||
|
STORES2: STRH R5,[R0,#0xe] ;//Store Short
|
||||||
|
LDRH R63,[R0,#0xe] ;//Load Short
|
||||||
|
VERIFY R63,R63,R5,STORE ;
|
||||||
|
|
||||||
|
STORE: STR R4,[R0,#0x0] ;//Store Word
|
||||||
|
LDR R63,[R0,#0x0] ;//Load Word
|
||||||
|
VERIFY R63,R63,R4,STORE2 ;
|
||||||
|
|
||||||
|
STORE2: STR R5,[R0,#0xc] ;//Store Word
|
||||||
|
LDR R63,[R0,#0xc] ;//Load Word
|
||||||
|
VERIFY R63,R63,R5,STOREBI ;
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*LOAD-STORE INDEX */
|
||||||
|
/*****************************************/
|
||||||
|
|
||||||
|
STOREBI: STRB R4,[R0,R4] ;//Store Word
|
||||||
|
LDRB R63,[R0,R4] ;//Load Word
|
||||||
|
VERIFY R63,R63,R4,STORESI ;
|
||||||
|
|
||||||
|
STORESI: STRH R5,[R0,R4] ;//Store Word
|
||||||
|
LDRH R63,[R0,R4] ;//Load Word
|
||||||
|
VERIFY R63,R63,R5,STOREI ;
|
||||||
|
|
||||||
|
STOREI: STR R6,[R0,R4] ;//Store Word
|
||||||
|
LDR R63,[R0,R4] ;//Load Word
|
||||||
|
VERIFY R63,R63,R6,PMB ;
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*LOAD-STORE POSTMODIFY */
|
||||||
|
/*****************************************/
|
||||||
|
|
||||||
|
PMB: STRB R4,[R0],R4 ;//Store Word
|
||||||
|
SUB R0,R0,#0x4 ;//restoring R0
|
||||||
|
LDRB R63,[R0],R4 ;//Load Word
|
||||||
|
SUB R0,R0,#0x4 ;//restoring R0
|
||||||
|
VERIFY R63,R63,R4,PMS ;
|
||||||
|
|
||||||
|
PMS: STRH R5,[R0],R4 ;//Store Word
|
||||||
|
SUB R0,R0,#0x4 ;//restoring R0
|
||||||
|
LDRH R63,[R0],R4 ;//Load Word
|
||||||
|
VERIFY R63,R63,R5,PM ;
|
||||||
|
|
||||||
|
PM: SUB R0,R0,#0x4 ;//restoring R0
|
||||||
|
STR R6,[R0],R4 ;//Store Word
|
||||||
|
SUB R0,R0,#0x4 ;//restoring R0
|
||||||
|
LDR R63,[R0],R4 ;//Load Word
|
||||||
|
SUB R0,R0,#0x4 ;//restoring R0
|
||||||
|
VERIFY R63,R63,R6,MOVLAB ;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*IMMEDIATE LOAD */
|
||||||
|
/*****************************************/
|
||||||
|
MOVLAB: MOV R63,#0xFF;
|
||||||
|
MOV R1,#0xFF;
|
||||||
|
VERIFY R63,R63,R1,ADDLAB ;
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*2 REG ADD/SUB PROCESSING */
|
||||||
|
/*****************************************/
|
||||||
|
ADDLAB: ADD R63,R2,#3; //2+3=5
|
||||||
|
VERIFY R63,R63,#5,SUBLAB ;
|
||||||
|
SUBLAB: SUB R63,R2,#1; //2+1=1
|
||||||
|
VERIFY R63,R63,#1,LSRLAB ;
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*SHIFTS */
|
||||||
|
/*****************************************/
|
||||||
|
//Note ASR does not work
|
||||||
|
|
||||||
|
//Immediates
|
||||||
|
LSRLAB: LSR R63,R6,#0x2 ; //6>>2=1
|
||||||
|
VERIFY R63,R63,#1,LSLLAB ;
|
||||||
|
LSLLAB: LSL R63,R3,#0x2 ; //3<<2=12
|
||||||
|
VERIFY R63,R63,#12,LSRILAB ;
|
||||||
|
//Registers
|
||||||
|
LSRILAB: LSR R63,R6,R2 ; //6>>2=1
|
||||||
|
VERIFY R63,R63,#1,LSLILAB ;
|
||||||
|
LSLILAB: LSL R63,R3,R2 ; //3<<2=12
|
||||||
|
VERIFY R63,R63,#12,ORRLAB ;
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*LOGICAL */
|
||||||
|
/*****************************************/
|
||||||
|
ORRLAB: ORR R5,R3,R4 ; //0x3 | 0x4 -->0x7
|
||||||
|
VERIFY R63,R5,#7,ANDLAB ;
|
||||||
|
ANDLAB: AND R5,R3,R4 ; //0x3 & 0x4 -->0
|
||||||
|
VERIFY R63,R5,#0,EORLAB ;
|
||||||
|
EORLAB: EOR R5,R3,R2 ; //0x3 ^ 0x2 -->1
|
||||||
|
VERIFY R63,R5,#1,ADD3LAB ;
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************/
|
||||||
|
/*3-REGISTER ADD/SUB */
|
||||||
|
/*****************************************/
|
||||||
|
ADD3LAB: ADD R63,R2,R3 ; //3+2=5
|
||||||
|
VERIFY R63,R63,#5,SUB3LAB ;
|
||||||
|
SUB3LAB: SUB R63,R6,R4 ; //6-4=2
|
||||||
|
VERIFY R63,R63,#2,MOVRLAB ;
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*MOVE REGISTER */
|
||||||
|
/*****************************************/
|
||||||
|
MOVRLAB: MOV R63,R2 ;
|
||||||
|
VERIFY R63,R63,#2,NOPLAB ;
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*MOVE TO/FROM SPECIAL REGISTER */
|
||||||
|
/*****************************************/
|
||||||
|
MOVTFLAB: MOVTS status,R0 ;
|
||||||
|
MOVFS R63,status ;
|
||||||
|
VERIFY R63,R63,R0,MOVTFLAB ;
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*NOP */
|
||||||
|
/*****************************************/
|
||||||
|
NOPLAB: NOP ;
|
||||||
|
NOP ;
|
||||||
|
NOP ;
|
||||||
|
NOP ;
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*PASS INDICATOR */
|
||||||
|
/*****************************************/
|
||||||
|
PASSED: PASS;
|
||||||
|
IDLE;
|
||||||
|
/*****************************************/
|
||||||
|
/*FAIL INDICATOR */
|
||||||
|
/*****************************************/
|
||||||
|
FAILED: FAIL;
|
||||||
|
IDLE;
|
||||||
|
|
||||||
|
/*****************************************/
|
||||||
|
/*LONG JUMP INDICATOR */
|
||||||
|
/*****************************************/
|
||||||
|
LONGJUMP: B RETURN; //jump back to next
|
||||||
|
/*****************************************/
|
||||||
|
/*SUBROUTINE */
|
||||||
|
/*****************************************/
|
||||||
|
FUNCTION: RTS; //return from subroutine
|
||||||
221
gas/testsuite/gas/epiphany/sample.d
Normal file
221
gas/testsuite/gas/epiphany/sample.d
Normal file
@ -0,0 +1,221 @@
|
|||||||
|
#as:
|
||||||
|
#objdump: -dr
|
||||||
|
#name: sample
|
||||||
|
.*\.o: file format elf32-epiphany
|
||||||
|
|
||||||
|
Disassembly of section \.text:
|
||||||
|
|
||||||
|
00000000 \<beq\>:
|
||||||
|
\.\.\.
|
||||||
|
|
||||||
|
00000002 \<bne\>:
|
||||||
|
2: ff10 bne 0 \<beq\>
|
||||||
|
|
||||||
|
00000004 \<bgtu\>:
|
||||||
|
4: fe20 bgtu 0 \<beq\>
|
||||||
|
|
||||||
|
00000006 \<bgteu\>:
|
||||||
|
6: fd30 bgteu 0 \<beq\>
|
||||||
|
|
||||||
|
00000008 \<blteu\>:
|
||||||
|
8: fc40 blteu 0 \<beq\>
|
||||||
|
|
||||||
|
0000000a \<bltu\>:
|
||||||
|
a: fb50 bltu 0 \<beq\>
|
||||||
|
|
||||||
|
0000000c \<bgt\>:
|
||||||
|
c: fa60 bgt 0 \<beq\>
|
||||||
|
|
||||||
|
0000000e \<bgte\>:
|
||||||
|
e: f970 bgte 0 \<beq\>
|
||||||
|
|
||||||
|
00000010 \<blt\>:
|
||||||
|
10: f880 blt 0 \<beq\>
|
||||||
|
|
||||||
|
00000012 \<blte\>:
|
||||||
|
12: f790 blte 0 \<beq\>
|
||||||
|
|
||||||
|
00000014 \<bbeq\>:
|
||||||
|
14: f6a0 bbeq 0 \<beq\>
|
||||||
|
|
||||||
|
00000016 \<bbne\>:
|
||||||
|
16: f5b0 bbne 0 \<beq\>
|
||||||
|
|
||||||
|
00000018 \<bblt\>:
|
||||||
|
18: f4c0 bblt 0 \<beq\>
|
||||||
|
|
||||||
|
0000001a \<b\>:
|
||||||
|
1a: f3e0 b 0 \<beq\>
|
||||||
|
|
||||||
|
0000001c \<bl\>:
|
||||||
|
1c: f2f0 bl 0 \<beq\>
|
||||||
|
|
||||||
|
0000001e \<jr\>:
|
||||||
|
1e: 0542 jr r1
|
||||||
|
20: 1d4f 0c02 jr r31
|
||||||
|
|
||||||
|
00000024 \<jalr\>:
|
||||||
|
24: 0552 jalr r1
|
||||||
|
26: 1d5f 0c02 jalr r31
|
||||||
|
|
||||||
|
0000002a \<add\>:
|
||||||
|
2a: 299a add r1,r2,r3
|
||||||
|
2c: 051f 920a add.l r32,r33,r34
|
||||||
|
30: 2993 add r1,r2,3
|
||||||
|
32: 681b 2002 add fp,r2,16
|
||||||
|
|
||||||
|
00000036 \<sub\>:
|
||||||
|
36: 29ba sub r1,r2,r3
|
||||||
|
38: 053f 920a sub.l r32,r33,r34
|
||||||
|
3c: 29b3 sub r1,r2,3
|
||||||
|
3e: 683b 2002 sub fp,r2,16
|
||||||
|
|
||||||
|
00000042 \<asr\>:
|
||||||
|
42: 29ea asr r1,r2,r3
|
||||||
|
44: 056f 920a asr.l r32,r33,r34
|
||||||
|
48: 286e asr r1,r2,0x3
|
||||||
|
4a: 6a0f 200e asr.l fp,r2,0x10
|
||||||
|
|
||||||
|
0000004e \<lsr\>:
|
||||||
|
4e: 29ca lsr r1,r2,r3
|
||||||
|
50: 054f 920a lsr.l r32,r33,r34
|
||||||
|
54: 2866 lsr r1,r2,0x3
|
||||||
|
56: 6a0f 2006 lsr.l fp,r2,0x10
|
||||||
|
|
||||||
|
0000005a \<lsl\>:
|
||||||
|
5a: 29aa lsl r1,r2,r3
|
||||||
|
5c: 052f 920a lsl.l r32,r33,r34
|
||||||
|
60: 2876 lsl r1,r2,0x3
|
||||||
|
62: 6a1f 2006 lsl.l fp,r2,0x10
|
||||||
|
|
||||||
|
00000066 \<orr\>:
|
||||||
|
66: 29fa orr r1,r2,r3
|
||||||
|
68: 72ff 248a orr.l fp,ip,sp
|
||||||
|
|
||||||
|
0000006c \<and\>:
|
||||||
|
6c: 29da and r1,r2,r3
|
||||||
|
6e: 72df 248a and.l fp,ip,sp
|
||||||
|
|
||||||
|
00000072 \<eor\>:
|
||||||
|
72: 298a eor r1,r2,r3
|
||||||
|
74: 728f 248a eor.l fp,ip,sp
|
||||||
|
78: 0584 ldrb r0,\[r1,0x3\]
|
||||||
|
7a: 478c 201f ldrb.l sl,\[r1,\+0xff\]
|
||||||
|
7e: 0501 ldrb r0,\[r1,r2\]
|
||||||
|
80: 0589 0080 ldrb.l r0,\[r1,\+fp\]
|
||||||
|
84: 0d05 ldrb r0,\[r3\],r2
|
||||||
|
86: 528d 2480 ldrb.l sl,\[ip\],\+sp
|
||||||
|
8a: 05a4 ldrh r0,\[r1,0x3\]
|
||||||
|
8c: 47ac 201f ldrh.l sl,\[r1,\+0xff\]
|
||||||
|
90: 0521 ldrh r0,\[r1,r2\]
|
||||||
|
92: 05a9 0080 ldrh.l r0,\[r1,\+fp\]
|
||||||
|
96: 0d25 ldrh r0,\[r3\],r2
|
||||||
|
98: 52ad 2480 ldrh.l sl,\[ip\],\+sp
|
||||||
|
9c: 05c4 ldr r0,\[r1,0x3\]
|
||||||
|
9e: 47cc 201f ldr.l sl,\[r1,\+0xff\]
|
||||||
|
a2: 0541 ldr r0,\[r1,r2\]
|
||||||
|
a4: 05c9 0080 ldr.l r0,\[r1,\+fp\]
|
||||||
|
a8: 0d45 ldr r0,\[r3\],r2
|
||||||
|
aa: 52cd 2480 ldr.l sl,\[ip\],\+sp
|
||||||
|
ae: 05e4 ldrd r0,\[r1,0x3\]
|
||||||
|
b0: 47ec 201f ldrd.l sl,\[r1,\+0xff\]
|
||||||
|
b4: 0561 ldrd r0,\[r1,r2\]
|
||||||
|
b6: 05e9 0080 ldrd.l r0,\[r1,\+fp\]
|
||||||
|
ba: 0d65 ldrd r0,\[r3\],r2
|
||||||
|
bc: 52ed 2480 ldrd.l sl,\[ip\],\+sp
|
||||||
|
c0: 0594 strb r0,\[r1,0x3\]
|
||||||
|
c2: 479c 201f strb.l sl,\[r1,\+0xff\]
|
||||||
|
c6: 0511 strb r0,\[r1,r2\]
|
||||||
|
c8: 0599 0080 strb.l r0,\[r1,\+fp\]
|
||||||
|
cc: 0d15 strb r0,\[r3\],r2
|
||||||
|
ce: 529d 2480 strb.l sl,\[ip\],\+sp
|
||||||
|
d2: 05b4 strh r0,\[r1,0x3\]
|
||||||
|
d4: 47bc 201f strh.l sl,\[r1,\+0xff\]
|
||||||
|
d8: 0531 strh r0,\[r1,r2\]
|
||||||
|
da: 05b9 0080 strh.l r0,\[r1,\+fp\]
|
||||||
|
de: 0d35 strh r0,\[r3\],r2
|
||||||
|
e0: 52bd 2480 strh.l sl,\[ip\],\+sp
|
||||||
|
e4: 05d4 str r0,\[r1,0x3\]
|
||||||
|
e6: 47dc 201f str.l sl,\[r1,\+0xff\]
|
||||||
|
ea: 0551 str r0,\[r1,r2\]
|
||||||
|
ec: 05d9 0080 str.l r0,\[r1,\+fp\]
|
||||||
|
f0: 0d55 str r0,\[r3\],r2
|
||||||
|
f2: 52dd 2480 str.l sl,\[ip\],\+sp
|
||||||
|
f6: 05f4 strd r0,\[r1,0x3\]
|
||||||
|
f8: 47fc 201f strd.l sl,\[r1,\+0xff\]
|
||||||
|
fc: 0571 strd r0,\[r1,r2\]
|
||||||
|
fe: 05f9 0080 strd.l r0,\[r1,\+fp\]
|
||||||
|
102: 0d75 strd r0,\[r3\],r2
|
||||||
|
104: 52fd 2480 strd.l sl,\[ip\],\+sp
|
||||||
|
|
||||||
|
00000108 \<mov\>:
|
||||||
|
108: dfe3 mov r6,0xff
|
||||||
|
10a: ffeb 6ff2 mov r31,0xffff
|
||||||
|
10e: 004b 0102 mov r0,0x1002
|
||||||
|
112: 2802 moveq r1,r2
|
||||||
|
114: 700f 2402 moveq.l fp,ip
|
||||||
|
118: 2812 movne r1,r2
|
||||||
|
11a: 701f 2402 movne.l fp,ip
|
||||||
|
11e: 2822 movgtu r1,r2
|
||||||
|
120: 702f 2402 movgtu.l fp,ip
|
||||||
|
124: 2832 movgteu r1,r2
|
||||||
|
126: 703f 2402 movgteu.l fp,ip
|
||||||
|
12a: 2842 movlteu r1,r2
|
||||||
|
12c: 704f 2402 movlteu.l fp,ip
|
||||||
|
130: 2852 movltu r1,r2
|
||||||
|
132: 705f 2402 movltu.l fp,ip
|
||||||
|
136: 2862 movgt r1,r2
|
||||||
|
138: 706f 2402 movgt.l fp,ip
|
||||||
|
13c: 2872 movgte r1,r2
|
||||||
|
13e: 707f 2402 movgte.l fp,ip
|
||||||
|
142: 2882 movlt r1,r2
|
||||||
|
144: 708f 2402 movlt.l fp,ip
|
||||||
|
148: 2892 movlte r1,r2
|
||||||
|
14a: 709f 2402 movlte.l fp,ip
|
||||||
|
14e: 28a2 movbeq r1,r2
|
||||||
|
150: 70af 2402 movbeq.l fp,ip
|
||||||
|
154: 28b2 movbne r1,r2
|
||||||
|
156: 70bf 2402 movbne.l fp,ip
|
||||||
|
15a: 28c2 movblt r1,r2
|
||||||
|
15c: 70cf 2402 movblt.l fp,ip
|
||||||
|
160: 28d2 movblte r1,r2
|
||||||
|
162: 70df 2402 movblte.l fp,ip
|
||||||
|
166: 28e2 mov r1,r2
|
||||||
|
168: 70ef 2402 mov.l fp,ip
|
||||||
|
|
||||||
|
0000016c \<nop\>:
|
||||||
|
16c: 01a2 nop
|
||||||
|
|
||||||
|
0000016e \<idle\>:
|
||||||
|
16e: 01b2 idle
|
||||||
|
|
||||||
|
00000170 \<bkpt\>:
|
||||||
|
170: 01c2 bkpt
|
||||||
|
|
||||||
|
00000172 \<fadd\>:
|
||||||
|
172: 2987 fadd r1,r2,r3
|
||||||
|
174: 728f 2487 fadd.l fp,ip,sp
|
||||||
|
|
||||||
|
00000178 \<fsub\>:
|
||||||
|
178: 2997 fsub r1,r2,r3
|
||||||
|
17a: 729f 2487 fsub.l fp,ip,sp
|
||||||
|
|
||||||
|
0000017e \<fmul\>:
|
||||||
|
17e: 29a7 fmul r1,r2,r3
|
||||||
|
180: 72af 2487 fmul.l fp,ip,sp
|
||||||
|
|
||||||
|
00000184 \<fmadd\>:
|
||||||
|
184: 29b7 fmadd r1,r2,r3
|
||||||
|
186: 72bf 2487 fmadd.l fp,ip,sp
|
||||||
|
|
||||||
|
0000018a \<fmsub\>:
|
||||||
|
18a: 29c7 fmsub r1,r2,r3
|
||||||
|
18c: 72cf 2487 fmsub.l fp,ip,sp
|
||||||
|
190: 2102 movts config,r1
|
||||||
|
192: e50f 6002 movts.l status,r31
|
||||||
|
196: 251f 0402 movfs.l r1,imask
|
||||||
|
19a: e91f 6002 movfs.l r31,pc
|
||||||
|
|
||||||
|
0000019e \<trap\>:
|
||||||
|
19e: 03e2 trap 0x0
|
||||||
|
1a0: 01d2 rti
|
||||||
123
gas/testsuite/gas/epiphany/sample.s
Executable file
123
gas/testsuite/gas/epiphany/sample.s
Executable file
@ -0,0 +1,123 @@
|
|||||||
|
.data
|
||||||
|
foodata: .hword 42
|
||||||
|
.text
|
||||||
|
footext:
|
||||||
|
.text
|
||||||
|
|
||||||
|
.macro test nm:req, args:vararg
|
||||||
|
\nm: \nm \args
|
||||||
|
.global \nm
|
||||||
|
.endm
|
||||||
|
|
||||||
|
;;; Basic Instruction Tests
|
||||||
|
1: ; All branches
|
||||||
|
test beq,1b
|
||||||
|
test bne,1b
|
||||||
|
test bgtu,1b
|
||||||
|
test bgteu,1b
|
||||||
|
test blteu,1b
|
||||||
|
test bltu,1b
|
||||||
|
test bgt,1b
|
||||||
|
test bgte,1b
|
||||||
|
test blt,1b
|
||||||
|
test blte,1b
|
||||||
|
|
||||||
|
test bbeq,1b
|
||||||
|
test bbne,1b
|
||||||
|
test bblt,1b
|
||||||
|
test b,1b
|
||||||
|
test bl,1b
|
||||||
|
|
||||||
|
;;; jumps
|
||||||
|
test jr,r1
|
||||||
|
jr r31
|
||||||
|
|
||||||
|
test jalr,r1
|
||||||
|
jalr r31
|
||||||
|
|
||||||
|
|
||||||
|
.macro test3i nm:req
|
||||||
|
test \nm,r1,r2,r3
|
||||||
|
\nm r32,r33,r34
|
||||||
|
\nm r1,r2,#3
|
||||||
|
\nm r11,r2,#16
|
||||||
|
.endm
|
||||||
|
test3i add
|
||||||
|
test3i sub
|
||||||
|
test3i asr
|
||||||
|
test3i lsr
|
||||||
|
test3i lsl
|
||||||
|
|
||||||
|
.macro test3 nm:req
|
||||||
|
test \nm,r1,r2,r3
|
||||||
|
\nm r11,r12,r13
|
||||||
|
.endm
|
||||||
|
|
||||||
|
test3 orr
|
||||||
|
test3 and
|
||||||
|
test3 eor
|
||||||
|
|
||||||
|
.macro testmem nm:req
|
||||||
|
\nm r0,[r1,#3]
|
||||||
|
\nm r10,[r1,#255]
|
||||||
|
\nm r0,[r1,r2]
|
||||||
|
\nm r0,[r1,r11]
|
||||||
|
\nm r0,[r3],r2
|
||||||
|
\nm r10,[r12],r13
|
||||||
|
.endm
|
||||||
|
|
||||||
|
testmem ldrb
|
||||||
|
testmem ldrh
|
||||||
|
testmem ldr
|
||||||
|
testmem ldrd
|
||||||
|
|
||||||
|
|
||||||
|
testmem strb
|
||||||
|
testmem strh
|
||||||
|
testmem str
|
||||||
|
testmem strd
|
||||||
|
|
||||||
|
test mov,r6,#255
|
||||||
|
mov r31,#65535
|
||||||
|
mov r0,#4098
|
||||||
|
|
||||||
|
.macro testmov cond:req
|
||||||
|
mov\cond r1,r2
|
||||||
|
mov\cond r11,r12
|
||||||
|
.endm
|
||||||
|
|
||||||
|
testmov eq
|
||||||
|
testmov ne
|
||||||
|
testmov gtu
|
||||||
|
testmov gteu
|
||||||
|
testmov lteu
|
||||||
|
testmov ltu
|
||||||
|
testmov gt
|
||||||
|
testmov gte
|
||||||
|
testmov lt
|
||||||
|
testmov lte
|
||||||
|
testmov beq
|
||||||
|
testmov bne
|
||||||
|
testmov blt
|
||||||
|
testmov blte
|
||||||
|
mov r1,r2
|
||||||
|
mov r11,r12
|
||||||
|
|
||||||
|
test nop
|
||||||
|
test idle
|
||||||
|
test bkpt
|
||||||
|
|
||||||
|
test3 fadd
|
||||||
|
test3 fsub
|
||||||
|
test3 fmul
|
||||||
|
test3 fmadd
|
||||||
|
test3 fmsub
|
||||||
|
|
||||||
|
movts config,r1
|
||||||
|
movts status,r31
|
||||||
|
|
||||||
|
movfs r1,imask
|
||||||
|
movfs r31,pc
|
||||||
|
|
||||||
|
test trap,#0 ; write syscall for simulator.
|
||||||
|
rti ; dummy instruction
|
||||||
@ -1,3 +1,7 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* dis-asm.h (print_insn_epiphany): Declare.
|
||||||
|
|
||||||
2011-10-21 Ulrich Drepper <drepper@gmail.com>
|
2011-10-21 Ulrich Drepper <drepper@gmail.com>
|
||||||
|
|
||||||
* obstack.h [!GNUC] (obstack_free): Avoid cast to int.
|
* obstack.h [!GNUC] (obstack_free): Avoid cast to int.
|
||||||
|
|||||||
@ -233,6 +233,7 @@ extern int print_insn_crx (bfd_vma, disassemble_info *);
|
|||||||
extern int print_insn_d10v (bfd_vma, disassemble_info *);
|
extern int print_insn_d10v (bfd_vma, disassemble_info *);
|
||||||
extern int print_insn_d30v (bfd_vma, disassemble_info *);
|
extern int print_insn_d30v (bfd_vma, disassemble_info *);
|
||||||
extern int print_insn_dlx (bfd_vma, disassemble_info *);
|
extern int print_insn_dlx (bfd_vma, disassemble_info *);
|
||||||
|
extern int print_insn_epiphany (bfd_vma, disassemble_info *);
|
||||||
extern int print_insn_fr30 (bfd_vma, disassemble_info *);
|
extern int print_insn_fr30 (bfd_vma, disassemble_info *);
|
||||||
extern int print_insn_frv (bfd_vma, disassemble_info *);
|
extern int print_insn_frv (bfd_vma, disassemble_info *);
|
||||||
extern int print_insn_h8300 (bfd_vma, disassemble_info *);
|
extern int print_insn_h8300 (bfd_vma, disassemble_info *);
|
||||||
|
|||||||
@ -1,3 +1,8 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* epiphany.h: New file.
|
||||||
|
* common.h (EM_ADAPTEVA_EPIPHANY): Define.
|
||||||
|
|
||||||
2011-10-10 Alan Modra <amodra@gmail.com>
|
2011-10-10 Alan Modra <amodra@gmail.com>
|
||||||
|
|
||||||
* ppc64.h (R_PPC64_TOCSAVE): Add.
|
* ppc64.h (R_PPC64_TOCSAVE): Add.
|
||||||
|
|||||||
@ -401,6 +401,8 @@
|
|||||||
|
|
||||||
#define EM_MICROBLAZE_OLD 0xbaab /* Old MicroBlaze */
|
#define EM_MICROBLAZE_OLD 0xbaab /* Old MicroBlaze */
|
||||||
|
|
||||||
|
#define EM_ADAPTEVA_EPIPHANY 0x1223 /* Adapteva's Epiphany architecture. */
|
||||||
|
|
||||||
/* See the above comment before you add a new EM_* value here. */
|
/* See the above comment before you add a new EM_* value here. */
|
||||||
|
|
||||||
/* Values for e_version. */
|
/* Values for e_version. */
|
||||||
|
|||||||
59
include/elf/epiphany.h
Executable file
59
include/elf/epiphany.h
Executable file
@ -0,0 +1,59 @@
|
|||||||
|
/* Adapteva EPIPHANY ELF support for BFD.
|
||||||
|
Copyright (C) 2011 Free Software Foundation, Inc.
|
||||||
|
Contributed by Embecosm on behalf of Adapteva, Inc.
|
||||||
|
|
||||||
|
This file is part of BFD, the Binary File Descriptor library.
|
||||||
|
|
||||||
|
This program is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
This program is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program; if not, write to the Free Software Foundation,
|
||||||
|
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||||
|
|
||||||
|
#ifndef _ELF_EPIPHANY_H
|
||||||
|
#define _ELF_EPIPHANY_H
|
||||||
|
|
||||||
|
#include "elf/reloc-macros.h"
|
||||||
|
|
||||||
|
/* Relocations. */
|
||||||
|
START_RELOC_NUMBERS (elf_epiphany_reloc_type)
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_NONE, 0)
|
||||||
|
|
||||||
|
/* Absolute address relocations. */
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_8, 1)
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_16, 2)
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_32, 3)
|
||||||
|
|
||||||
|
/* PC-relative relocations. */
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_8_PCREL, 4)
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_16_PCREL,5)
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_32_PCREL,6)
|
||||||
|
|
||||||
|
/* special forms for 8/24 bit branch displacements. */
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_SIMM8, 7)
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_SIMM24, 8)
|
||||||
|
|
||||||
|
/* HIGH and LOW relocations taking part of a 32 bit address and
|
||||||
|
depositing it into the IMM16 field of a destination. */
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_HIGH, 9)
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_LOW,10)
|
||||||
|
|
||||||
|
/* 11 bit signed immediate value. */
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_SIMM11, 11)
|
||||||
|
/* 11 bit magnitude addressing displacement. */
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_IMM11, 12)
|
||||||
|
|
||||||
|
/* 8 bit immediate for MOV.S R,IMM8. */
|
||||||
|
RELOC_NUMBER (R_EPIPHANY_IMM8, 13)
|
||||||
|
|
||||||
|
END_RELOC_NUMBERS(R_EPIPHANY_max)
|
||||||
|
|
||||||
|
#endif /* _ELF_EPIPHANY_H */
|
||||||
10
ld/ChangeLog
10
ld/ChangeLog
@ -1,3 +1,13 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* NEWS: Mention addition of Adapteva Epiphany support.
|
||||||
|
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
|
||||||
|
(eelf32epiphany.c): New rule.
|
||||||
|
* configure.tgt: Handle epiphany-*-elf.
|
||||||
|
* emulparams/elf32epiphany.sh: New file.
|
||||||
|
* Makefile.in: Regenerate.
|
||||||
|
* po/ld.pot: Regenerate.
|
||||||
|
|
||||||
2011-10-24 Nick Clifton <nickc@redhat.com>
|
2011-10-24 Nick Clifton <nickc@redhat.com>
|
||||||
|
|
||||||
* po/ja.po: Updated Japanese translation.
|
* po/ja.po: Updated Japanese translation.
|
||||||
|
|||||||
@ -211,6 +211,7 @@ ALL_EMULATION_SOURCES = \
|
|||||||
eelf32ebmipvxworks.c \
|
eelf32ebmipvxworks.c \
|
||||||
eelf32elmip.c \
|
eelf32elmip.c \
|
||||||
eelf32elmipvxworks.c \
|
eelf32elmipvxworks.c \
|
||||||
|
eelf32epiphany.c \
|
||||||
eelf32fr30.c \
|
eelf32fr30.c \
|
||||||
eelf32frv.c \
|
eelf32frv.c \
|
||||||
eelf32frvfd.c \
|
eelf32frvfd.c \
|
||||||
@ -990,6 +991,9 @@ eelf32elmipvxworks.c: $(srcdir)/emulparams/elf32elmipvxworks.sh \
|
|||||||
$(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
|
$(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
|
||||||
$(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
$(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||||
${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
|
${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
|
||||||
|
eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \
|
||||||
|
$(ELF_DEPS) ${GEN_DEPENDS}
|
||||||
|
${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)"
|
||||||
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
|
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
|
||||||
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||||
${GENSCRIPTS} elf32fr30 "$(tdir_fr30)"
|
${GENSCRIPTS} elf32fr30 "$(tdir_fr30)"
|
||||||
|
|||||||
@ -517,6 +517,7 @@ ALL_EMULATION_SOURCES = \
|
|||||||
eelf32ebmipvxworks.c \
|
eelf32ebmipvxworks.c \
|
||||||
eelf32elmip.c \
|
eelf32elmip.c \
|
||||||
eelf32elmipvxworks.c \
|
eelf32elmipvxworks.c \
|
||||||
|
eelf32epiphany.c \
|
||||||
eelf32fr30.c \
|
eelf32fr30.c \
|
||||||
eelf32frv.c \
|
eelf32frv.c \
|
||||||
eelf32frvfd.c \
|
eelf32frvfd.c \
|
||||||
@ -1117,6 +1118,7 @@ distclean-compile:
|
|||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ebmipvxworks.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ebmipvxworks.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmip.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmip.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmipvxworks.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32elmipvxworks.Po@am__quote@
|
||||||
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32epiphany.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32fr30.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32fr30.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frv.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frv.Po@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frvfd.Po@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frvfd.Po@am__quote@
|
||||||
@ -2443,6 +2445,9 @@ eelf32elmipvxworks.c: $(srcdir)/emulparams/elf32elmipvxworks.sh \
|
|||||||
$(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
|
$(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \
|
||||||
$(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
$(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||||
${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
|
${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)"
|
||||||
|
eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \
|
||||||
|
$(ELF_DEPS) ${GEN_DEPENDS}
|
||||||
|
${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)"
|
||||||
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
|
eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \
|
||||||
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
||||||
${GENSCRIPTS} elf32fr30 "$(tdir_fr30)"
|
${GENSCRIPTS} elf32fr30 "$(tdir_fr30)"
|
||||||
|
|||||||
8
ld/NEWS
8
ld/NEWS
@ -1,18 +1,20 @@
|
|||||||
-*- text -*-
|
-*- text -*-
|
||||||
|
|
||||||
|
* Add support for the Adapteva EPIPHANY architecture.
|
||||||
|
|
||||||
Changes in 2.22:
|
Changes in 2.22:
|
||||||
|
|
||||||
* --copy-dt-needed-entries is no longer enabled by default. Instead
|
* --copy-dt-needed-entries is no longer enabled by default. Instead
|
||||||
--no-copy-dt-needed-entries is the default.
|
--no-copy-dt-needed-entries is the default.
|
||||||
|
|
||||||
* INPUT_SECTION_FLAGS has been added to the linker script language
|
* INPUT_SECTION_FLAGS has been added to the linker script language
|
||||||
to allow selection of input sections by section header section flags.
|
to allow selection of input sections by section header section flags.
|
||||||
|
|
||||||
* Add support for the Tilera TILEPRO and TILE-Gx architectures.
|
* Add support for the Tilera TILEPRO and TILE-Gx architectures.
|
||||||
|
|
||||||
* Added SORT_BY_INIT_PRIORITY to the linker script language to permit
|
* Added SORT_BY_INIT_PRIORITY to the linker script language to permit
|
||||||
sorting sections by numerical value of the GCC init_priority attribute
|
sorting sections by numerical value of the GCC init_priority attribute
|
||||||
encoded in the section name.
|
encoded in the section name.
|
||||||
|
|
||||||
Changes in 2.21:
|
Changes in 2.21:
|
||||||
|
|
||||||
|
|||||||
@ -137,6 +137,8 @@ d30v-*-*) targ_emul=d30velf; targ_extra_emuls="d30v_e d30v_o"
|
|||||||
;;
|
;;
|
||||||
dlx-*-elf*) targ_emul=elf32_dlx
|
dlx-*-elf*) targ_emul=elf32_dlx
|
||||||
;;
|
;;
|
||||||
|
epiphany-*-elf) targ_emul=elf32epiphany
|
||||||
|
;;
|
||||||
fido*-*-elf*) targ_emul=m68kelf ;;
|
fido*-*-elf*) targ_emul=m68kelf ;;
|
||||||
fr30-*-*) targ_emul=elf32fr30
|
fr30-*-*) targ_emul=elf32fr30
|
||||||
;;
|
;;
|
||||||
|
|||||||
42
ld/emulparams/elf32epiphany.sh
Normal file
42
ld/emulparams/elf32epiphany.sh
Normal file
@ -0,0 +1,42 @@
|
|||||||
|
TEMPLATE_NAME=elf32
|
||||||
|
MACHINE=
|
||||||
|
SCRIPT_NAME=elf
|
||||||
|
OUTPUT_FORMAT="elf32-epiphany"
|
||||||
|
NO_REL_RELOCS=yes
|
||||||
|
# See also `include/elf/epiphany.h'
|
||||||
|
|
||||||
|
MMR_ADDR=0x00000000
|
||||||
|
MMR_LEN=0x100
|
||||||
|
|
||||||
|
#RESERVED_ADDR=0x00000100
|
||||||
|
#RESERVED_LEN=8128
|
||||||
|
|
||||||
|
IVT_ADDR=0x00000000
|
||||||
|
IVT_LEN=0x040
|
||||||
|
|
||||||
|
# ??? This fails: 'Not enough room for program headers, try linking with -N'
|
||||||
|
#TEXT_START_ADDR=0x00000040
|
||||||
|
|
||||||
|
#The following two lines would allow small to medium sized programs
|
||||||
|
#to run in the first 1 MB.
|
||||||
|
#TEXT_START_ADDR=0x00000060
|
||||||
|
#EXECUTABLE_SYMBOLS='PROVIDE (___bss_start = __bss_start); PROVIDE (___heap_start = end); PROVIDE (___heap_end = (0x0c0000)); PROVIDE (___stack = (0x0ffff0));'
|
||||||
|
|
||||||
|
TEXT_START_ADDR='DEFINED (___text_start) ? ___text_start : 0x80000000'
|
||||||
|
EXECUTABLE_SYMBOLS='PROVIDE (___bss_start = __bss_start); PROVIDE (___heap_start = end); PROVIDE (___heap_end = (0x81800000)); PROVIDE (___stack = (0x81fffff0));'
|
||||||
|
|
||||||
|
#Smuggle an alignemnt directive in here so that .bss is aligned.
|
||||||
|
OTHER_SDATA_SECTIONS='. = ALIGN(8);'
|
||||||
|
|
||||||
|
|
||||||
|
ARCH=epiphany
|
||||||
|
ENTRY=_start
|
||||||
|
EMBEDDED=yes
|
||||||
|
ELFSIZE=32
|
||||||
|
ALIGNMENT=8
|
||||||
|
#MAXPAGESIZE=8192
|
||||||
|
MAXPAGESIZE=1
|
||||||
|
WRITABLE_RODATA=
|
||||||
|
#OTHER_RELOCATING_SECTIONS=
|
||||||
|
#OTHER_READONLY_SECTIONS=
|
||||||
|
#OTHER_READWRITE_SECTIONS=
|
||||||
750
ld/po/ld.pot
750
ld/po/ld.pot
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,9 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* ld-srec/srec.exp: xfail epiphany.
|
||||||
|
* lib/ld-lib.exp (check_shared_lib_support): Add Epiphany to list
|
||||||
|
of targets not supporting shared libraries.
|
||||||
|
|
||||||
2011-10-21 H.J. Lu <hongjiu.lu@intel.com>
|
2011-10-21 H.J. Lu <hongjiu.lu@intel.com>
|
||||||
|
|
||||||
PR ld/13302
|
PR ld/13302
|
||||||
|
|||||||
@ -270,6 +270,12 @@ proc run_srec_test { test objs } {
|
|||||||
set flags "$flags --no-toc-optimize"
|
set flags "$flags --no-toc-optimize"
|
||||||
}
|
}
|
||||||
|
|
||||||
|
# Epiphany needs some help too
|
||||||
|
if [istarget epiphany*-*-*] {
|
||||||
|
set flags "$flags --defsym _start=00000060"
|
||||||
|
setup_xfail "epiphany*-*-*"
|
||||||
|
}
|
||||||
|
|
||||||
if { ![ld_simple_link $ld tmpdir/sr1 "$flags $objs"] \
|
if { ![ld_simple_link $ld tmpdir/sr1 "$flags $objs"] \
|
||||||
|| ![ld_simple_link $ld tmpdir/sr2.sr "$flags --oformat srec $objs"] } {
|
|| ![ld_simple_link $ld tmpdir/sr2.sr "$flags --oformat srec $objs"] } {
|
||||||
fail $test
|
fail $test
|
||||||
|
|||||||
@ -1463,6 +1463,7 @@ proc check_shared_lib_support { } {
|
|||||||
&& ![istarget d10v-*-*]
|
&& ![istarget d10v-*-*]
|
||||||
&& ![istarget d30v-*-*]
|
&& ![istarget d30v-*-*]
|
||||||
&& ![istarget dlx-*-*]
|
&& ![istarget dlx-*-*]
|
||||||
|
&& ![istarget epiphany-*-*]
|
||||||
&& ![istarget fr30-*-*]
|
&& ![istarget fr30-*-*]
|
||||||
&& ![istarget frv-*-*]
|
&& ![istarget frv-*-*]
|
||||||
&& ![istarget h8300-*-*]
|
&& ![istarget h8300-*-*]
|
||||||
|
|||||||
@ -1,3 +1,26 @@
|
|||||||
|
2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
|
||||||
|
|
||||||
|
* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
|
||||||
|
(TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
|
||||||
|
epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
|
||||||
|
(CLEANFILES): Add stamp-epiphany.
|
||||||
|
(EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
|
||||||
|
(stamp-epiphany): New rule.
|
||||||
|
* configure.in: Handle bfd_epiphany_arch.
|
||||||
|
* disassemble.c (ARCH_epiphany): Define.
|
||||||
|
(disassembler): Handle bfd_arch_epiphany.
|
||||||
|
* epiphany-asm.c: New file.
|
||||||
|
* epiphany-desc.c: New file.
|
||||||
|
* epiphany-desc.h: New file.
|
||||||
|
* epiphany-dis.c: New file.
|
||||||
|
* epiphany-ibld.c: New file.
|
||||||
|
* epiphany-opc.c: New file.
|
||||||
|
* epiphany-opc.h: New file.
|
||||||
|
* Makefile.in: Regenerate.
|
||||||
|
* configure: Regenerate.
|
||||||
|
* po/POTFILES.in: Regenerate.
|
||||||
|
* po/opcodes.pot: Regenerate.
|
||||||
|
|
||||||
2011-10-24 Julian Brown <julian@codesourcery.com>
|
2011-10-24 Julian Brown <julian@codesourcery.com>
|
||||||
|
|
||||||
* m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
|
* m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
|
||||||
|
|||||||
@ -41,6 +41,7 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@
|
|||||||
|
|
||||||
# Header files.
|
# Header files.
|
||||||
HFILES = \
|
HFILES = \
|
||||||
|
epiphany-desc.h epiphany-opc.h \
|
||||||
fr30-desc.h fr30-opc.h \
|
fr30-desc.h fr30-opc.h \
|
||||||
frv-desc.h frv-opc.h \
|
frv-desc.h frv-opc.h \
|
||||||
h8500-opc.h \
|
h8500-opc.h \
|
||||||
@ -95,6 +96,11 @@ TARGET_LIBOPCODES_CFILES = \
|
|||||||
d30v-dis.c \
|
d30v-dis.c \
|
||||||
d30v-opc.c \
|
d30v-opc.c \
|
||||||
dlx-dis.c \
|
dlx-dis.c \
|
||||||
|
epiphany-asm.c \
|
||||||
|
epiphany-desc.c \
|
||||||
|
epiphany-dis.c \
|
||||||
|
epiphany-ibld.c \
|
||||||
|
epiphany-opc.c \
|
||||||
fr30-asm.c \
|
fr30-asm.c \
|
||||||
fr30-desc.c \
|
fr30-desc.c \
|
||||||
fr30-dis.c \
|
fr30-dis.c \
|
||||||
@ -311,7 +317,7 @@ po/POTFILES.in: @MAINT@ Makefile
|
|||||||
&& mv tmp $(srcdir)/po/POTFILES.in
|
&& mv tmp $(srcdir)/po/POTFILES.in
|
||||||
|
|
||||||
CLEANFILES = \
|
CLEANFILES = \
|
||||||
stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
|
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
|
||||||
stamp-m32c stamp-m32r stamp-mep stamp-mt \
|
stamp-m32c stamp-m32r stamp-mep stamp-mt \
|
||||||
stamp-openrisc stamp-xc16x stamp-xstormy16 \
|
stamp-openrisc stamp-xc16x stamp-xstormy16 \
|
||||||
libopcodes.a stamp-lib
|
libopcodes.a stamp-lib
|
||||||
@ -329,9 +335,10 @@ CGENDEPS = \
|
|||||||
$(CGENDIR)/opc-opinst.scm \
|
$(CGENDIR)/opc-opinst.scm \
|
||||||
cgen-asm.in cgen-dis.in cgen-ibld.in
|
cgen-asm.in cgen-dis.in cgen-ibld.in
|
||||||
|
|
||||||
CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
|
CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
|
||||||
|
|
||||||
if CGEN_MAINT
|
if CGEN_MAINT
|
||||||
|
EPIPHANY_DEPS = stamp-epiphany
|
||||||
FR30_DEPS = stamp-fr30
|
FR30_DEPS = stamp-fr30
|
||||||
FRV_DEPS = stamp-frv
|
FRV_DEPS = stamp-frv
|
||||||
IP2K_DEPS = stamp-ip2k
|
IP2K_DEPS = stamp-ip2k
|
||||||
@ -345,6 +352,7 @@ OPENRISC_DEPS = stamp-openrisc
|
|||||||
XC16X_DEPS = stamp-xc16x
|
XC16X_DEPS = stamp-xc16x
|
||||||
XSTORMY16_DEPS = stamp-xstormy16
|
XSTORMY16_DEPS = stamp-xstormy16
|
||||||
else
|
else
|
||||||
|
EPIPHANY_DEPS =
|
||||||
FR30_DEPS =
|
FR30_DEPS =
|
||||||
FRV_DEPS =
|
FRV_DEPS =
|
||||||
IP2K_DEPS =
|
IP2K_DEPS =
|
||||||
@ -376,6 +384,16 @@ run-cgen-all:
|
|||||||
|
|
||||||
# For now, require developers to configure with --enable-cgen-maint.
|
# For now, require developers to configure with --enable-cgen-maint.
|
||||||
|
|
||||||
|
$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
|
||||||
|
$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
|
||||||
|
$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
|
||||||
|
$(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS)
|
||||||
|
@true
|
||||||
|
|
||||||
|
stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc
|
||||||
|
$(MAKE) run-cgen arch=epiphany prefix=epiphany options= \
|
||||||
|
archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles=
|
||||||
|
|
||||||
$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
|
$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
|
||||||
@true
|
@true
|
||||||
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
|
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
|
||||||
|
|||||||
@ -310,6 +310,7 @@ BFD_H = ../bfd/bfd.h
|
|||||||
|
|
||||||
# Header files.
|
# Header files.
|
||||||
HFILES = \
|
HFILES = \
|
||||||
|
epiphany-desc.h epiphany-opc.h \
|
||||||
fr30-desc.h fr30-opc.h \
|
fr30-desc.h fr30-opc.h \
|
||||||
frv-desc.h frv-opc.h \
|
frv-desc.h frv-opc.h \
|
||||||
h8500-opc.h \
|
h8500-opc.h \
|
||||||
@ -365,6 +366,11 @@ TARGET_LIBOPCODES_CFILES = \
|
|||||||
d30v-dis.c \
|
d30v-dis.c \
|
||||||
d30v-opc.c \
|
d30v-opc.c \
|
||||||
dlx-dis.c \
|
dlx-dis.c \
|
||||||
|
epiphany-asm.c \
|
||||||
|
epiphany-desc.c \
|
||||||
|
epiphany-dis.c \
|
||||||
|
epiphany-ibld.c \
|
||||||
|
epiphany-opc.c \
|
||||||
fr30-asm.c \
|
fr30-asm.c \
|
||||||
fr30-desc.c \
|
fr30-desc.c \
|
||||||
fr30-dis.c \
|
fr30-dis.c \
|
||||||
@ -550,7 +556,7 @@ noinst_LIBRARIES = libopcodes.a
|
|||||||
libopcodes_a_SOURCES =
|
libopcodes_a_SOURCES =
|
||||||
POTFILES = $(HFILES) $(CFILES)
|
POTFILES = $(HFILES) $(CFILES)
|
||||||
CLEANFILES = \
|
CLEANFILES = \
|
||||||
stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
|
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
|
||||||
stamp-m32c stamp-m32r stamp-mep stamp-mt \
|
stamp-m32c stamp-m32r stamp-mep stamp-mt \
|
||||||
stamp-openrisc stamp-xc16x stamp-xstormy16 \
|
stamp-openrisc stamp-xc16x stamp-xstormy16 \
|
||||||
libopcodes.a stamp-lib
|
libopcodes.a stamp-lib
|
||||||
@ -566,7 +572,9 @@ CGENDEPS = \
|
|||||||
$(CGENDIR)/opc-opinst.scm \
|
$(CGENDIR)/opc-opinst.scm \
|
||||||
cgen-asm.in cgen-dis.in cgen-ibld.in
|
cgen-asm.in cgen-dis.in cgen-ibld.in
|
||||||
|
|
||||||
CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
|
CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
|
||||||
|
@CGEN_MAINT_FALSE@EPIPHANY_DEPS =
|
||||||
|
@CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany
|
||||||
@CGEN_MAINT_FALSE@FR30_DEPS =
|
@CGEN_MAINT_FALSE@FR30_DEPS =
|
||||||
@CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30
|
@CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30
|
||||||
@CGEN_MAINT_FALSE@FRV_DEPS =
|
@CGEN_MAINT_FALSE@FRV_DEPS =
|
||||||
@ -741,6 +749,11 @@ distclean-compile:
|
|||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dis-init.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dis-init.Plo@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/disassemble.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/disassemble.Plo@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlx-dis.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlx-dis.Plo@am__quote@
|
||||||
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-asm.Plo@am__quote@
|
||||||
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-desc.Plo@am__quote@
|
||||||
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-dis.Plo@am__quote@
|
||||||
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-ibld.Plo@am__quote@
|
||||||
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-opc.Plo@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-asm.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-asm.Plo@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-desc.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-desc.Plo@am__quote@
|
||||||
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-dis.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-dis.Plo@am__quote@
|
||||||
@ -1229,6 +1242,16 @@ run-cgen-all:
|
|||||||
|
|
||||||
# For now, require developers to configure with --enable-cgen-maint.
|
# For now, require developers to configure with --enable-cgen-maint.
|
||||||
|
|
||||||
|
$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \
|
||||||
|
$(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \
|
||||||
|
$(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \
|
||||||
|
$(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS)
|
||||||
|
@true
|
||||||
|
|
||||||
|
stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc
|
||||||
|
$(MAKE) run-cgen arch=epiphany prefix=epiphany options= \
|
||||||
|
archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles=
|
||||||
|
|
||||||
$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
|
$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS)
|
||||||
@true
|
@true
|
||||||
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
|
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
|
||||||
|
|||||||
1
opcodes/configure
vendored
1
opcodes/configure
vendored
@ -12429,6 +12429,7 @@ if test x${all_targets} = xfalse ; then
|
|||||||
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
||||||
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
||||||
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
|
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
|
||||||
|
bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
|
||||||
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
|
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
|
||||||
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
|
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
|
||||||
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
|
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
|
||||||
|
|||||||
@ -243,6 +243,7 @@ if test x${all_targets} = xfalse ; then
|
|||||||
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
|
||||||
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
|
||||||
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
|
bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;;
|
||||||
|
bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;;
|
||||||
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
|
bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;;
|
||||||
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
|
bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;;
|
||||||
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
|
bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;;
|
||||||
|
|||||||
@ -26,6 +26,7 @@
|
|||||||
#define ARCH_alpha
|
#define ARCH_alpha
|
||||||
#define ARCH_arc
|
#define ARCH_arc
|
||||||
#define ARCH_arm
|
#define ARCH_arm
|
||||||
|
#define ARCH_epiphany
|
||||||
#define ARCH_avr
|
#define ARCH_avr
|
||||||
#define ARCH_bfin
|
#define ARCH_bfin
|
||||||
#define ARCH_cr16
|
#define ARCH_cr16
|
||||||
@ -224,6 +225,11 @@ disassembler (abfd)
|
|||||||
disassemble = print_insn_ip2k;
|
disassemble = print_insn_ip2k;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
#ifdef ARCH_epiphany
|
||||||
|
case bfd_arch_epiphany:
|
||||||
|
disassemble = print_insn_epiphany;
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
#ifdef ARCH_fr30
|
#ifdef ARCH_fr30
|
||||||
case bfd_arch_fr30:
|
case bfd_arch_fr30:
|
||||||
disassemble = print_insn_fr30;
|
disassemble = print_insn_fr30;
|
||||||
|
|||||||
863
opcodes/epiphany-asm.c
Normal file
863
opcodes/epiphany-asm.c
Normal file
@ -0,0 +1,863 @@
|
|||||||
|
/* Assembler interface for targets using CGEN. -*- C -*-
|
||||||
|
CGEN: Cpu tools GENerator
|
||||||
|
|
||||||
|
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||||
|
- the resultant file is machine generated, cgen-asm.in isn't
|
||||||
|
|
||||||
|
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010
|
||||||
|
Free Software Foundation, Inc.
|
||||||
|
|
||||||
|
This file is part of libopcodes.
|
||||||
|
|
||||||
|
This library is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3, or (at your option)
|
||||||
|
any later version.
|
||||||
|
|
||||||
|
It is distributed in the hope that it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||||
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||||
|
License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||||
|
|
||||||
|
|
||||||
|
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
|
||||||
|
Keep that in mind. */
|
||||||
|
|
||||||
|
#include "sysdep.h"
|
||||||
|
#include <stdio.h>
|
||||||
|
#include "ansidecl.h"
|
||||||
|
#include "bfd.h"
|
||||||
|
#include "symcat.h"
|
||||||
|
#include "epiphany-desc.h"
|
||||||
|
#include "epiphany-opc.h"
|
||||||
|
#include "opintl.h"
|
||||||
|
#include "xregex.h"
|
||||||
|
#include "libiberty.h"
|
||||||
|
#include "safe-ctype.h"
|
||||||
|
|
||||||
|
#undef min
|
||||||
|
#define min(a,b) ((a) < (b) ? (a) : (b))
|
||||||
|
#undef max
|
||||||
|
#define max(a,b) ((a) > (b) ? (a) : (b))
|
||||||
|
|
||||||
|
static const char * parse_insn_normal
|
||||||
|
(CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
|
||||||
|
|
||||||
|
/* -- assembler routines inserted here. */
|
||||||
|
|
||||||
|
/* -- asm.c */
|
||||||
|
const char *
|
||||||
|
parse_shortregs (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
CGEN_KEYWORD * keywords,
|
||||||
|
long * regno)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
|
||||||
|
/* Parse register. */
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, keywords, regno);
|
||||||
|
|
||||||
|
if (errmsg)
|
||||||
|
return errmsg;
|
||||||
|
|
||||||
|
if (*regno > 7)
|
||||||
|
errmsg = _("register unavailable for short instructions");
|
||||||
|
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int,
|
||||||
|
long *);
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_uimm_not_reg (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
unsigned long * valuep)
|
||||||
|
{
|
||||||
|
long * svalp = (void *) valuep;
|
||||||
|
return parse_simm_not_reg (cd, strp, opindex, svalp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Handle simm3/simm11/imm3/imm12. */
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_simm_not_reg (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
long * valuep)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
|
||||||
|
int sign = 0;
|
||||||
|
int bits = 0;
|
||||||
|
|
||||||
|
switch (opindex)
|
||||||
|
{
|
||||||
|
case EPIPHANY_OPERAND_SIMM3:
|
||||||
|
sign = 1; bits = 3; break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM11:
|
||||||
|
sign = 1; bits = 11; break;
|
||||||
|
case EPIPHANY_OPERAND_DISP3:
|
||||||
|
sign = 0; bits = 3; break;
|
||||||
|
case EPIPHANY_OPERAND_DISP11:
|
||||||
|
/* Load/store displacement is a sign-magnitude 12 bit value. */
|
||||||
|
sign = 0; bits = 11; break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* First try to parse as a register name and reject the operand. */
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep);
|
||||||
|
if (!errmsg)
|
||||||
|
return _("register name used as immediate value");
|
||||||
|
|
||||||
|
errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep)
|
||||||
|
: cgen_parse_unsigned_integer (cd, strp, opindex,
|
||||||
|
(unsigned long *) valuep));
|
||||||
|
if (errmsg)
|
||||||
|
return errmsg;
|
||||||
|
|
||||||
|
if (sign)
|
||||||
|
errmsg = cgen_validate_signed_integer (*valuep,
|
||||||
|
-((1L << bits) - 1), (1 << (bits - 1)) - 1);
|
||||||
|
else
|
||||||
|
errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1);
|
||||||
|
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma * valuep)
|
||||||
|
{
|
||||||
|
if (**strp == '#')
|
||||||
|
++*strp; /* Skip leading hashes. */
|
||||||
|
|
||||||
|
if (**strp == '-')
|
||||||
|
{
|
||||||
|
*valuep = 1;
|
||||||
|
++*strp;
|
||||||
|
}
|
||||||
|
else if (**strp == '+')
|
||||||
|
{
|
||||||
|
*valuep = 0;
|
||||||
|
++*strp;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
*valuep = 0;
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_imm8 (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
bfd_reloc_code_real_type code,
|
||||||
|
enum cgen_parse_operand_result * result_type,
|
||||||
|
bfd_vma * valuep)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
enum cgen_parse_operand_result rt;
|
||||||
|
long dummyval;
|
||||||
|
|
||||||
|
if (!result_type)
|
||||||
|
result_type = &rt;
|
||||||
|
|
||||||
|
code = BFD_RELOC_NONE;
|
||||||
|
|
||||||
|
if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval)
|
||||||
|
|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
|
||||||
|
&dummyval))
|
||||||
|
/* Don't treat "mov ip,ip" as a move-immediate. */
|
||||||
|
return _("register source in immediate move");
|
||||||
|
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep);
|
||||||
|
if (errmsg)
|
||||||
|
return errmsg;
|
||||||
|
|
||||||
|
if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||||
|
errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff);
|
||||||
|
else
|
||||||
|
errmsg = _("byte relocation unsupported");
|
||||||
|
|
||||||
|
*valuep &= 0xff;
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'");
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_imm16 (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
bfd_reloc_code_real_type code ATTRIBUTE_UNUSED,
|
||||||
|
enum cgen_parse_operand_result * result_type,
|
||||||
|
bfd_vma * valuep)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
enum cgen_parse_operand_result rt;
|
||||||
|
long dummyval;
|
||||||
|
|
||||||
|
if (!result_type)
|
||||||
|
result_type = &rt;
|
||||||
|
|
||||||
|
if (strncasecmp (*strp, "%high(", 6) == 0)
|
||||||
|
{
|
||||||
|
*strp += 6;
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH,
|
||||||
|
result_type, valuep);
|
||||||
|
if (**strp != ')')
|
||||||
|
return MISSING_CLOSE_PARENTHESIS;
|
||||||
|
++*strp;
|
||||||
|
*valuep >>= 16;
|
||||||
|
}
|
||||||
|
else if (strncasecmp (*strp, "%low(", 5) == 0)
|
||||||
|
{
|
||||||
|
*strp += 5;
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW,
|
||||||
|
result_type, valuep);
|
||||||
|
if (**strp != ')')
|
||||||
|
return MISSING_CLOSE_PARENTHESIS;
|
||||||
|
++*strp;
|
||||||
|
}
|
||||||
|
else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names,
|
||||||
|
&dummyval)
|
||||||
|
|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
|
||||||
|
&dummyval))
|
||||||
|
/* Don't treat "mov ip,ip" as a move-immediate. */
|
||||||
|
return _("register source in immediate move");
|
||||||
|
else
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
|
||||||
|
result_type, valuep);
|
||||||
|
|
||||||
|
if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||||
|
errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff);
|
||||||
|
|
||||||
|
*valuep &= 0xffff;
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
const char *
|
||||||
|
parse_branch_addr (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
int opinfo ATTRIBUTE_UNUSED,
|
||||||
|
enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED,
|
||||||
|
unsigned long * valuep ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
const char * errmsg;
|
||||||
|
enum cgen_parse_operand_result result_type;
|
||||||
|
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
|
||||||
|
bfd_vma value;
|
||||||
|
|
||||||
|
switch (opindex)
|
||||||
|
{
|
||||||
|
case EPIPHANY_OPERAND_SIMM24:
|
||||||
|
code = BFD_RELOC_EPIPHANY_SIMM24;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EPIPHANY_OPERAND_SIMM8:
|
||||||
|
code = BFD_RELOC_EPIPHANY_SIMM8;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
errmsg = _("ABORT: unknown operand");
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
errmsg = cgen_parse_address (cd, strp, opindex, code,
|
||||||
|
&result_type, &value);
|
||||||
|
if (errmsg == NULL)
|
||||||
|
{
|
||||||
|
if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||||
|
{
|
||||||
|
/* Act as if we had done a PC-relative branch, ala .+num. */
|
||||||
|
char buf[20];
|
||||||
|
const char * bufp = (const char *) buf;
|
||||||
|
|
||||||
|
sprintf (buf, ".+%ld", value);
|
||||||
|
errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type,
|
||||||
|
&value);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
|
||||||
|
{
|
||||||
|
/* This will happen for things like (s2-s1) where s2 and s1
|
||||||
|
are labels. */
|
||||||
|
/* Nothing further to be done. */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
errmsg = _("Not a pc-relative address.");
|
||||||
|
}
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* -- dis.c */
|
||||||
|
|
||||||
|
const char * epiphany_cgen_parse_operand
|
||||||
|
(CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
|
||||||
|
|
||||||
|
/* Main entry point for operand parsing.
|
||||||
|
|
||||||
|
This function is basically just a big switch statement. Earlier versions
|
||||||
|
used tables to look up the function to use, but
|
||||||
|
- if the table contains both assembler and disassembler functions then
|
||||||
|
the disassembler contains much of the assembler and vice-versa,
|
||||||
|
- there's a lot of inlining possibilities as things grow,
|
||||||
|
- using a switch statement avoids the function call overhead.
|
||||||
|
|
||||||
|
This function could be moved into `parse_insn_normal', but keeping it
|
||||||
|
separate makes clear the interface between `parse_insn_normal' and each of
|
||||||
|
the handlers. */
|
||||||
|
|
||||||
|
const char *
|
||||||
|
epiphany_cgen_parse_operand (CGEN_CPU_DESC cd,
|
||||||
|
int opindex,
|
||||||
|
const char ** strp,
|
||||||
|
CGEN_FIELDS * fields)
|
||||||
|
{
|
||||||
|
const char * errmsg = NULL;
|
||||||
|
/* Used by scalar operands that still need to be parsed. */
|
||||||
|
long junk ATTRIBUTE_UNUSED;
|
||||||
|
|
||||||
|
switch (opindex)
|
||||||
|
{
|
||||||
|
case EPIPHANY_OPERAND_DIRECTION :
|
||||||
|
errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DIRECTION, (unsigned long *) (& fields->f_addsubx));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_DISP11 :
|
||||||
|
errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_DISP11, (unsigned long *) (& fields->f_disp11));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_DISP3 :
|
||||||
|
errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_DISP3, (unsigned long *) (& fields->f_disp3));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_DPMI :
|
||||||
|
errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DPMI, (unsigned long *) (& fields->f_subd));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRD :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRD6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRM :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRM6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRN :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRN6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_IMM16 :
|
||||||
|
{
|
||||||
|
bfd_vma value = 0;
|
||||||
|
errmsg = parse_imm16 (cd, strp, EPIPHANY_OPERAND_IMM16, 0, NULL, & value);
|
||||||
|
fields->f_imm16 = value;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_IMM8 :
|
||||||
|
{
|
||||||
|
bfd_vma value = 0;
|
||||||
|
errmsg = parse_imm8 (cd, strp, EPIPHANY_OPERAND_IMM8, 0, NULL, & value);
|
||||||
|
fields->f_imm8 = value;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RD :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RD6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RM :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RM6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RN :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RN6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SD :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SD6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SDDMA :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sd6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SDMEM :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sd6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SDMESH :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sd6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SHIFT :
|
||||||
|
errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_SHIFT, (unsigned long *) (& fields->f_shift));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM11 :
|
||||||
|
errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM11, (long *) (& fields->f_sdisp11));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM24 :
|
||||||
|
{
|
||||||
|
bfd_vma value = 0;
|
||||||
|
errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM24, 0, NULL, & value);
|
||||||
|
fields->f_simm24 = value;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM3 :
|
||||||
|
errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM3, (long *) (& fields->f_sdisp3));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM8 :
|
||||||
|
{
|
||||||
|
bfd_vma value = 0;
|
||||||
|
errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM8, 0, NULL, & value);
|
||||||
|
fields->f_simm8 = value;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SN :
|
||||||
|
errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SN6 :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SNDMA :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sn6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SNMEM :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sn6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SNMESH :
|
||||||
|
errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sn6);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SWI_NUM :
|
||||||
|
errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_SWI_NUM, (unsigned long *) (& fields->f_trap_num));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_TRAPNUM6 :
|
||||||
|
errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_TRAPNUM6, (unsigned long *) (& fields->f_trap_num));
|
||||||
|
break;
|
||||||
|
|
||||||
|
default :
|
||||||
|
/* xgettext:c-format */
|
||||||
|
fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
|
||||||
|
abort ();
|
||||||
|
}
|
||||||
|
|
||||||
|
return errmsg;
|
||||||
|
}
|
||||||
|
|
||||||
|
cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
|
||||||
|
{
|
||||||
|
parse_insn_normal,
|
||||||
|
};
|
||||||
|
|
||||||
|
void
|
||||||
|
epiphany_cgen_init_asm (CGEN_CPU_DESC cd)
|
||||||
|
{
|
||||||
|
epiphany_cgen_init_opcode_table (cd);
|
||||||
|
epiphany_cgen_init_ibld_table (cd);
|
||||||
|
cd->parse_handlers = & epiphany_cgen_parse_handlers[0];
|
||||||
|
cd->parse_operand = epiphany_cgen_parse_operand;
|
||||||
|
#ifdef CGEN_ASM_INIT_HOOK
|
||||||
|
CGEN_ASM_INIT_HOOK
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Regex construction routine.
|
||||||
|
|
||||||
|
This translates an opcode syntax string into a regex string,
|
||||||
|
by replacing any non-character syntax element (such as an
|
||||||
|
opcode) with the pattern '.*'
|
||||||
|
|
||||||
|
It then compiles the regex and stores it in the opcode, for
|
||||||
|
later use by epiphany_cgen_assemble_insn
|
||||||
|
|
||||||
|
Returns NULL for success, an error message for failure. */
|
||||||
|
|
||||||
|
char *
|
||||||
|
epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
|
||||||
|
{
|
||||||
|
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
|
||||||
|
const char *mnem = CGEN_INSN_MNEMONIC (insn);
|
||||||
|
char rxbuf[CGEN_MAX_RX_ELEMENTS];
|
||||||
|
char *rx = rxbuf;
|
||||||
|
const CGEN_SYNTAX_CHAR_TYPE *syn;
|
||||||
|
int reg_err;
|
||||||
|
|
||||||
|
syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
|
||||||
|
|
||||||
|
/* Mnemonics come first in the syntax string. */
|
||||||
|
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
|
||||||
|
return _("missing mnemonic in syntax string");
|
||||||
|
++syn;
|
||||||
|
|
||||||
|
/* Generate a case sensitive regular expression that emulates case
|
||||||
|
insensitive matching in the "C" locale. We cannot generate a case
|
||||||
|
insensitive regular expression because in Turkish locales, 'i' and 'I'
|
||||||
|
are not equal modulo case conversion. */
|
||||||
|
|
||||||
|
/* Copy the literal mnemonic out of the insn. */
|
||||||
|
for (; *mnem; mnem++)
|
||||||
|
{
|
||||||
|
char c = *mnem;
|
||||||
|
|
||||||
|
if (ISALPHA (c))
|
||||||
|
{
|
||||||
|
*rx++ = '[';
|
||||||
|
*rx++ = TOLOWER (c);
|
||||||
|
*rx++ = TOUPPER (c);
|
||||||
|
*rx++ = ']';
|
||||||
|
}
|
||||||
|
else
|
||||||
|
*rx++ = c;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Copy any remaining literals from the syntax string into the rx. */
|
||||||
|
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
|
||||||
|
{
|
||||||
|
if (CGEN_SYNTAX_CHAR_P (* syn))
|
||||||
|
{
|
||||||
|
char c = CGEN_SYNTAX_CHAR (* syn);
|
||||||
|
|
||||||
|
switch (c)
|
||||||
|
{
|
||||||
|
/* Escape any regex metacharacters in the syntax. */
|
||||||
|
case '.': case '[': case '\\':
|
||||||
|
case '*': case '^': case '$':
|
||||||
|
|
||||||
|
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
|
||||||
|
case '?': case '{': case '}':
|
||||||
|
case '(': case ')': case '*':
|
||||||
|
case '|': case '+': case ']':
|
||||||
|
#endif
|
||||||
|
*rx++ = '\\';
|
||||||
|
*rx++ = c;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
if (ISALPHA (c))
|
||||||
|
{
|
||||||
|
*rx++ = '[';
|
||||||
|
*rx++ = TOLOWER (c);
|
||||||
|
*rx++ = TOUPPER (c);
|
||||||
|
*rx++ = ']';
|
||||||
|
}
|
||||||
|
else
|
||||||
|
*rx++ = c;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Replace non-syntax fields with globs. */
|
||||||
|
*rx++ = '.';
|
||||||
|
*rx++ = '*';
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Trailing whitespace ok. */
|
||||||
|
* rx++ = '[';
|
||||||
|
* rx++ = ' ';
|
||||||
|
* rx++ = '\t';
|
||||||
|
* rx++ = ']';
|
||||||
|
* rx++ = '*';
|
||||||
|
|
||||||
|
/* But anchor it after that. */
|
||||||
|
* rx++ = '$';
|
||||||
|
* rx = '\0';
|
||||||
|
|
||||||
|
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
|
||||||
|
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
|
||||||
|
|
||||||
|
if (reg_err == 0)
|
||||||
|
return NULL;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
static char msg[80];
|
||||||
|
|
||||||
|
regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
|
||||||
|
regfree ((regex_t *) CGEN_INSN_RX (insn));
|
||||||
|
free (CGEN_INSN_RX (insn));
|
||||||
|
(CGEN_INSN_RX (insn)) = NULL;
|
||||||
|
return msg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Default insn parser.
|
||||||
|
|
||||||
|
The syntax string is scanned and operands are parsed and stored in FIELDS.
|
||||||
|
Relocs are queued as we go via other callbacks.
|
||||||
|
|
||||||
|
??? Note that this is currently an all-or-nothing parser. If we fail to
|
||||||
|
parse the instruction, we return 0 and the caller will start over from
|
||||||
|
the beginning. Backtracking will be necessary in parsing subexpressions,
|
||||||
|
but that can be handled there. Not handling backtracking here may get
|
||||||
|
expensive in the case of the m68k. Deal with later.
|
||||||
|
|
||||||
|
Returns NULL for success, an error message for failure. */
|
||||||
|
|
||||||
|
static const char *
|
||||||
|
parse_insn_normal (CGEN_CPU_DESC cd,
|
||||||
|
const CGEN_INSN *insn,
|
||||||
|
const char **strp,
|
||||||
|
CGEN_FIELDS *fields)
|
||||||
|
{
|
||||||
|
/* ??? Runtime added insns not handled yet. */
|
||||||
|
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||||||
|
const char *str = *strp;
|
||||||
|
const char *errmsg;
|
||||||
|
const char *p;
|
||||||
|
const CGEN_SYNTAX_CHAR_TYPE * syn;
|
||||||
|
#ifdef CGEN_MNEMONIC_OPERANDS
|
||||||
|
/* FIXME: wip */
|
||||||
|
int past_opcode_p;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* For now we assume the mnemonic is first (there are no leading operands).
|
||||||
|
We can parse it without needing to set up operand parsing.
|
||||||
|
GAS's input scrubber will ensure mnemonics are lowercase, but we may
|
||||||
|
not be called from GAS. */
|
||||||
|
p = CGEN_INSN_MNEMONIC (insn);
|
||||||
|
while (*p && TOLOWER (*p) == TOLOWER (*str))
|
||||||
|
++p, ++str;
|
||||||
|
|
||||||
|
if (* p)
|
||||||
|
return _("unrecognized instruction");
|
||||||
|
|
||||||
|
#ifndef CGEN_MNEMONIC_OPERANDS
|
||||||
|
if (* str && ! ISSPACE (* str))
|
||||||
|
return _("unrecognized instruction");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
CGEN_INIT_PARSE (cd);
|
||||||
|
cgen_init_parse_operand (cd);
|
||||||
|
#ifdef CGEN_MNEMONIC_OPERANDS
|
||||||
|
past_opcode_p = 0;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* We don't check for (*str != '\0') here because we want to parse
|
||||||
|
any trailing fake arguments in the syntax string. */
|
||||||
|
syn = CGEN_SYNTAX_STRING (syntax);
|
||||||
|
|
||||||
|
/* Mnemonics come first for now, ensure valid string. */
|
||||||
|
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
|
||||||
|
abort ();
|
||||||
|
|
||||||
|
++syn;
|
||||||
|
|
||||||
|
while (* syn != 0)
|
||||||
|
{
|
||||||
|
/* Non operand chars must match exactly. */
|
||||||
|
if (CGEN_SYNTAX_CHAR_P (* syn))
|
||||||
|
{
|
||||||
|
/* FIXME: While we allow for non-GAS callers above, we assume the
|
||||||
|
first char after the mnemonic part is a space. */
|
||||||
|
/* FIXME: We also take inappropriate advantage of the fact that
|
||||||
|
GAS's input scrubber will remove extraneous blanks. */
|
||||||
|
if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
|
||||||
|
{
|
||||||
|
#ifdef CGEN_MNEMONIC_OPERANDS
|
||||||
|
if (CGEN_SYNTAX_CHAR(* syn) == ' ')
|
||||||
|
past_opcode_p = 1;
|
||||||
|
#endif
|
||||||
|
++ syn;
|
||||||
|
++ str;
|
||||||
|
}
|
||||||
|
else if (*str)
|
||||||
|
{
|
||||||
|
/* Syntax char didn't match. Can't be this insn. */
|
||||||
|
static char msg [80];
|
||||||
|
|
||||||
|
/* xgettext:c-format */
|
||||||
|
sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
|
||||||
|
CGEN_SYNTAX_CHAR(*syn), *str);
|
||||||
|
return msg;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Ran out of input. */
|
||||||
|
static char msg [80];
|
||||||
|
|
||||||
|
/* xgettext:c-format */
|
||||||
|
sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
|
||||||
|
CGEN_SYNTAX_CHAR(*syn));
|
||||||
|
return msg;
|
||||||
|
}
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CGEN_MNEMONIC_OPERANDS
|
||||||
|
(void) past_opcode_p;
|
||||||
|
#endif
|
||||||
|
/* We have an operand of some sort. */
|
||||||
|
errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
|
||||||
|
if (errmsg)
|
||||||
|
return errmsg;
|
||||||
|
|
||||||
|
/* Done with this operand, continue with next one. */
|
||||||
|
++ syn;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If we're at the end of the syntax string, we're done. */
|
||||||
|
if (* syn == 0)
|
||||||
|
{
|
||||||
|
/* FIXME: For the moment we assume a valid `str' can only contain
|
||||||
|
blanks now. IE: We needn't try again with a longer version of
|
||||||
|
the insn and it is assumed that longer versions of insns appear
|
||||||
|
before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
|
||||||
|
while (ISSPACE (* str))
|
||||||
|
++ str;
|
||||||
|
|
||||||
|
if (* str != '\0')
|
||||||
|
return _("junk at end of line"); /* FIXME: would like to include `str' */
|
||||||
|
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* We couldn't parse it. */
|
||||||
|
return _("unrecognized instruction");
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Main entry point.
|
||||||
|
This routine is called for each instruction to be assembled.
|
||||||
|
STR points to the insn to be assembled.
|
||||||
|
We assume all necessary tables have been initialized.
|
||||||
|
The assembled instruction, less any fixups, is stored in BUF.
|
||||||
|
Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
|
||||||
|
still needs to be converted to target byte order, otherwise BUF is an array
|
||||||
|
of bytes in target byte order.
|
||||||
|
The result is a pointer to the insn's entry in the opcode table,
|
||||||
|
or NULL if an error occured (an error message will have already been
|
||||||
|
printed).
|
||||||
|
|
||||||
|
Note that when processing (non-alias) macro-insns,
|
||||||
|
this function recurses.
|
||||||
|
|
||||||
|
??? It's possible to make this cpu-independent.
|
||||||
|
One would have to deal with a few minor things.
|
||||||
|
At this point in time doing so would be more of a curiosity than useful
|
||||||
|
[for example this file isn't _that_ big], but keeping the possibility in
|
||||||
|
mind helps keep the design clean. */
|
||||||
|
|
||||||
|
const CGEN_INSN *
|
||||||
|
epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
|
||||||
|
const char *str,
|
||||||
|
CGEN_FIELDS *fields,
|
||||||
|
CGEN_INSN_BYTES_PTR buf,
|
||||||
|
char **errmsg)
|
||||||
|
{
|
||||||
|
const char *start;
|
||||||
|
CGEN_INSN_LIST *ilist;
|
||||||
|
const char *parse_errmsg = NULL;
|
||||||
|
const char *insert_errmsg = NULL;
|
||||||
|
int recognized_mnemonic = 0;
|
||||||
|
|
||||||
|
/* Skip leading white space. */
|
||||||
|
while (ISSPACE (* str))
|
||||||
|
++ str;
|
||||||
|
|
||||||
|
/* The instructions are stored in hashed lists.
|
||||||
|
Get the first in the list. */
|
||||||
|
ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
|
||||||
|
|
||||||
|
/* Keep looking until we find a match. */
|
||||||
|
start = str;
|
||||||
|
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
|
||||||
|
{
|
||||||
|
const CGEN_INSN *insn = ilist->insn;
|
||||||
|
recognized_mnemonic = 1;
|
||||||
|
|
||||||
|
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
|
||||||
|
/* Not usually needed as unsupported opcodes
|
||||||
|
shouldn't be in the hash lists. */
|
||||||
|
/* Is this insn supported by the selected cpu? */
|
||||||
|
if (! epiphany_cgen_insn_supported (cd, insn))
|
||||||
|
continue;
|
||||||
|
#endif
|
||||||
|
/* If the RELAXED attribute is set, this is an insn that shouldn't be
|
||||||
|
chosen immediately. Instead, it is used during assembler/linker
|
||||||
|
relaxation if possible. */
|
||||||
|
if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
str = start;
|
||||||
|
|
||||||
|
/* Skip this insn if str doesn't look right lexically. */
|
||||||
|
if (CGEN_INSN_RX (insn) != NULL &&
|
||||||
|
regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* Allow parse/insert handlers to obtain length of insn. */
|
||||||
|
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||||||
|
|
||||||
|
parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
|
||||||
|
if (parse_errmsg != NULL)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* ??? 0 is passed for `pc'. */
|
||||||
|
insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
|
||||||
|
(bfd_vma) 0);
|
||||||
|
if (insert_errmsg != NULL)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
/* It is up to the caller to actually output the insn and any
|
||||||
|
queued relocs. */
|
||||||
|
return insn;
|
||||||
|
}
|
||||||
|
|
||||||
|
{
|
||||||
|
static char errbuf[150];
|
||||||
|
const char *tmp_errmsg;
|
||||||
|
#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||||||
|
#define be_verbose 1
|
||||||
|
#else
|
||||||
|
#define be_verbose 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (be_verbose)
|
||||||
|
{
|
||||||
|
/* If requesting verbose error messages, use insert_errmsg.
|
||||||
|
Failing that, use parse_errmsg. */
|
||||||
|
tmp_errmsg = (insert_errmsg ? insert_errmsg :
|
||||||
|
parse_errmsg ? parse_errmsg :
|
||||||
|
recognized_mnemonic ?
|
||||||
|
_("unrecognized form of instruction") :
|
||||||
|
_("unrecognized instruction"));
|
||||||
|
|
||||||
|
if (strlen (start) > 50)
|
||||||
|
/* xgettext:c-format */
|
||||||
|
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
|
||||||
|
else
|
||||||
|
/* xgettext:c-format */
|
||||||
|
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (strlen (start) > 50)
|
||||||
|
/* xgettext:c-format */
|
||||||
|
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
|
||||||
|
else
|
||||||
|
/* xgettext:c-format */
|
||||||
|
sprintf (errbuf, _("bad instruction `%.50s'"), start);
|
||||||
|
}
|
||||||
|
|
||||||
|
*errmsg = errbuf;
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
}
|
||||||
2271
opcodes/epiphany-desc.c
Normal file
2271
opcodes/epiphany-desc.c
Normal file
File diff suppressed because it is too large
Load Diff
402
opcodes/epiphany-desc.h
Normal file
402
opcodes/epiphany-desc.h
Normal file
@ -0,0 +1,402 @@
|
|||||||
|
/* CPU data header for epiphany.
|
||||||
|
|
||||||
|
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||||
|
|
||||||
|
Copyright 1996-2010 Free Software Foundation, Inc.
|
||||||
|
|
||||||
|
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||||
|
|
||||||
|
This file is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3, or (at your option)
|
||||||
|
any later version.
|
||||||
|
|
||||||
|
It is distributed in the hope that it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||||
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||||
|
License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along
|
||||||
|
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef EPIPHANY_CPU_H
|
||||||
|
#define EPIPHANY_CPU_H
|
||||||
|
|
||||||
|
#define CGEN_ARCH epiphany
|
||||||
|
|
||||||
|
/* Given symbol S, return epiphany_cgen_<S>. */
|
||||||
|
#define CGEN_SYM(s) epiphany##_cgen_##s
|
||||||
|
|
||||||
|
|
||||||
|
/* Selected cpu families. */
|
||||||
|
#define HAVE_CPU_EPIPHANYBF
|
||||||
|
#define HAVE_CPU_EPIPHANYMF
|
||||||
|
|
||||||
|
#define CGEN_INSN_LSB0_P 1
|
||||||
|
|
||||||
|
/* Minimum size of any insn (in bytes). */
|
||||||
|
#define CGEN_MIN_INSN_SIZE 2
|
||||||
|
|
||||||
|
/* Maximum size of any insn (in bytes). */
|
||||||
|
#define CGEN_MAX_INSN_SIZE 4
|
||||||
|
|
||||||
|
#define CGEN_INT_INSN_P 1
|
||||||
|
|
||||||
|
/* Maximum number of syntax elements in an instruction. */
|
||||||
|
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
|
||||||
|
|
||||||
|
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
|
||||||
|
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
|
||||||
|
we can't hash on everything up to the space. */
|
||||||
|
#define CGEN_MNEMONIC_OPERANDS
|
||||||
|
|
||||||
|
/* Maximum number of fields in an instruction. */
|
||||||
|
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
|
||||||
|
|
||||||
|
/* Enums. */
|
||||||
|
|
||||||
|
/* Enum declaration for opc enums. */
|
||||||
|
typedef enum insn_opc {
|
||||||
|
OP4_BRANCH16, OP4_LDSTR16X, OP4_FLOW16, OP4_IMM16
|
||||||
|
, OP4_LDSTR16D, OP4_LDSTR16P, OP4_LSHIFT16, OP4_DSP16
|
||||||
|
, OP4_BRANCH, OP4_LDSTRX, OP4_ALU16, OP4_IMM32
|
||||||
|
, OP4_LDSTRD, OP4_LDSTRP, OP4_ASHIFT16, OP4_MISC
|
||||||
|
} INSN_OPC;
|
||||||
|
|
||||||
|
/* Enum declaration for memory access width. */
|
||||||
|
typedef enum insn_wordsize {
|
||||||
|
OPW_BYTE, OPW_SHORT, OPW_WORD, OPW_DOUBLE
|
||||||
|
} INSN_WORDSIZE;
|
||||||
|
|
||||||
|
/* Enum declaration for memory access direction. */
|
||||||
|
typedef enum insn_memory_access {
|
||||||
|
OP_LOAD, OP_STORE
|
||||||
|
} INSN_MEMORY_ACCESS;
|
||||||
|
|
||||||
|
/* Enum declaration for trap instruction dispatch code. */
|
||||||
|
typedef enum trap_codes {
|
||||||
|
TRAP_WRITE, TRAP_READ, TRAP_OPEN, TRAP_EXIT
|
||||||
|
, TRAP_PASS, TRAP_FAIL, TRAP_CLOSE, TRAP_OTHER
|
||||||
|
} TRAP_CODES;
|
||||||
|
|
||||||
|
/* Enum declaration for branch conditions. */
|
||||||
|
typedef enum insn_cond {
|
||||||
|
OPC_EQ, OPC_NE, OPC_GTU, OPC_GTEU
|
||||||
|
, OPC_LTEU, OPC_LTU, OPC_GT, OPC_GTE
|
||||||
|
, OPC_LT, OPC_LTE, OPC_BEQ, OPC_BNE
|
||||||
|
, OPC_BLT, OPC_BLTE, OPC_B, OPC_BL
|
||||||
|
} INSN_COND;
|
||||||
|
|
||||||
|
/* Enum declaration for binary operator subcodes. */
|
||||||
|
typedef enum insn_bop {
|
||||||
|
OPB_EOR, OPB_ADD, OPB_LSL, OPB_SUB
|
||||||
|
, OPB_LSR, OPB_AND, OPB_ASR, OPB_ORR
|
||||||
|
} INSN_BOP;
|
||||||
|
|
||||||
|
/* Enum declaration for binary operator subcodes. */
|
||||||
|
typedef enum insn_bopext {
|
||||||
|
OPBE_FEXT, OPBE_FDEP, OPBE_LFSR
|
||||||
|
} INSN_BOPEXT;
|
||||||
|
|
||||||
|
/* Enum declaration for floating operators. */
|
||||||
|
typedef enum insn_fop {
|
||||||
|
OPF_ADD, OPF_SUB, OPF_MUL, OPF_MADD
|
||||||
|
, OPF_MSUB, OPF_FLOAT, OPF_FIX, OPF_FABS
|
||||||
|
} INSN_FOP;
|
||||||
|
|
||||||
|
/* Enum declaration for extended floating operators. */
|
||||||
|
typedef enum insn_fopexn {
|
||||||
|
OPF_FRECIP, OPF_FSQRT
|
||||||
|
} INSN_FOPEXN;
|
||||||
|
|
||||||
|
/* Enum declaration for immediate operators. */
|
||||||
|
typedef enum insn_immop {
|
||||||
|
OPI_ADD = 1, OPI_SUB = 3, OPI_TRAP = 7
|
||||||
|
} INSN_IMMOP;
|
||||||
|
|
||||||
|
/* Enum declaration for don't cares. */
|
||||||
|
typedef enum insn_dc_25_2 {
|
||||||
|
OPI_25_2_MBZ
|
||||||
|
} INSN_DC_25_2;
|
||||||
|
|
||||||
|
/* Enum declaration for . */
|
||||||
|
typedef enum gr_names {
|
||||||
|
H_REGISTERS_SB = 9, H_REGISTERS_SL = 10, H_REGISTERS_FP = 11, H_REGISTERS_IP = 12
|
||||||
|
, H_REGISTERS_SP = 13, H_REGISTERS_LR = 14, H_REGISTERS_R0 = 0, H_REGISTERS_R1 = 1
|
||||||
|
, H_REGISTERS_R2 = 2, H_REGISTERS_R3 = 3, H_REGISTERS_R4 = 4, H_REGISTERS_R5 = 5
|
||||||
|
, H_REGISTERS_R6 = 6, H_REGISTERS_R7 = 7, H_REGISTERS_R8 = 8, H_REGISTERS_R9 = 9
|
||||||
|
, H_REGISTERS_R10 = 10, H_REGISTERS_R11 = 11, H_REGISTERS_R12 = 12, H_REGISTERS_R13 = 13
|
||||||
|
, H_REGISTERS_R14 = 14, H_REGISTERS_R15 = 15, H_REGISTERS_R16 = 16, H_REGISTERS_R17 = 17
|
||||||
|
, H_REGISTERS_R18 = 18, H_REGISTERS_R19 = 19, H_REGISTERS_R20 = 20, H_REGISTERS_R21 = 21
|
||||||
|
, H_REGISTERS_R22 = 22, H_REGISTERS_R23 = 23, H_REGISTERS_R24 = 24, H_REGISTERS_R25 = 25
|
||||||
|
, H_REGISTERS_R26 = 26, H_REGISTERS_R27 = 27, H_REGISTERS_R28 = 28, H_REGISTERS_R29 = 29
|
||||||
|
, H_REGISTERS_R30 = 30, H_REGISTERS_R31 = 31, H_REGISTERS_R32 = 32, H_REGISTERS_R33 = 33
|
||||||
|
, H_REGISTERS_R34 = 34, H_REGISTERS_R35 = 35, H_REGISTERS_R36 = 36, H_REGISTERS_R37 = 37
|
||||||
|
, H_REGISTERS_R38 = 38, H_REGISTERS_R39 = 39, H_REGISTERS_R40 = 40, H_REGISTERS_R41 = 41
|
||||||
|
, H_REGISTERS_R42 = 42, H_REGISTERS_R43 = 43, H_REGISTERS_R44 = 44, H_REGISTERS_R45 = 45
|
||||||
|
, H_REGISTERS_R46 = 46, H_REGISTERS_R47 = 47, H_REGISTERS_R48 = 48, H_REGISTERS_R49 = 49
|
||||||
|
, H_REGISTERS_R50 = 50, H_REGISTERS_R51 = 51, H_REGISTERS_R52 = 52, H_REGISTERS_R53 = 53
|
||||||
|
, H_REGISTERS_R54 = 54, H_REGISTERS_R55 = 55, H_REGISTERS_R56 = 56, H_REGISTERS_R57 = 57
|
||||||
|
, H_REGISTERS_R58 = 58, H_REGISTERS_R59 = 59, H_REGISTERS_R60 = 60, H_REGISTERS_R61 = 61
|
||||||
|
, H_REGISTERS_R62 = 62, H_REGISTERS_R63 = 63, H_REGISTERS_A1 = 0, H_REGISTERS_A2 = 1
|
||||||
|
, H_REGISTERS_A3 = 2, H_REGISTERS_A4 = 3, H_REGISTERS_V1 = 4, H_REGISTERS_V2 = 5
|
||||||
|
, H_REGISTERS_V3 = 6, H_REGISTERS_V4 = 7, H_REGISTERS_V5 = 8, H_REGISTERS_V6 = 9
|
||||||
|
, H_REGISTERS_V7 = 10, H_REGISTERS_V8 = 11
|
||||||
|
} GR_NAMES;
|
||||||
|
|
||||||
|
/* Enum declaration for +/- index register. */
|
||||||
|
typedef enum post_index {
|
||||||
|
DIR_POSTINC, DIR_POSTDEC
|
||||||
|
} POST_INDEX;
|
||||||
|
|
||||||
|
/* Enum declaration for postmodify displacement. */
|
||||||
|
typedef enum disp_post_modify {
|
||||||
|
PMOD_DISP, PMOD_POST
|
||||||
|
} DISP_POST_MODIFY;
|
||||||
|
|
||||||
|
/* Enum declaration for . */
|
||||||
|
typedef enum cr_names {
|
||||||
|
H_CORE_REGISTERS_CONFIG, H_CORE_REGISTERS_STATUS, H_CORE_REGISTERS_PC, H_CORE_REGISTERS_DEBUG
|
||||||
|
, H_CORE_REGISTERS_IAB, H_CORE_REGISTERS_LC, H_CORE_REGISTERS_LS, H_CORE_REGISTERS_LE
|
||||||
|
, H_CORE_REGISTERS_IRET, H_CORE_REGISTERS_IMASK, H_CORE_REGISTERS_ILAT, H_CORE_REGISTERS_ILATST
|
||||||
|
, H_CORE_REGISTERS_ILATCL, H_CORE_REGISTERS_IPEND, H_CORE_REGISTERS_CTIMER0, H_CORE_REGISTERS_CTIMER1
|
||||||
|
, H_CORE_REGISTERS_HSTATUS
|
||||||
|
} CR_NAMES;
|
||||||
|
|
||||||
|
/* Enum declaration for . */
|
||||||
|
typedef enum crdma_names {
|
||||||
|
H_COREDMA_REGISTERS_DMA0CONFIG, H_COREDMA_REGISTERS_DMA0STRIDE, H_COREDMA_REGISTERS_DMA0COUNT, H_COREDMA_REGISTERS_DMA0SRCADDR
|
||||||
|
, H_COREDMA_REGISTERS_DMA0DSTADDR, H_COREDMA_REGISTERS_DMA0AUTO0, H_COREDMA_REGISTERS_DMA0AUTO1, H_COREDMA_REGISTERS_DMA0STATUS
|
||||||
|
, H_COREDMA_REGISTERS_DMA1CONFIG, H_COREDMA_REGISTERS_DMA1STRIDE, H_COREDMA_REGISTERS_DMA1COUNT, H_COREDMA_REGISTERS_DMA1SRCADDR
|
||||||
|
, H_COREDMA_REGISTERS_DMA1DSTADDR, H_COREDMA_REGISTERS_DMA1AUTO0, H_COREDMA_REGISTERS_DMA1AUTO1, H_COREDMA_REGISTERS_DMA1STATUS
|
||||||
|
} CRDMA_NAMES;
|
||||||
|
|
||||||
|
/* Enum declaration for . */
|
||||||
|
typedef enum crmem_names {
|
||||||
|
H_COREMEM_REGISTERS_MEMCONFIG, H_COREMEM_REGISTERS_MEMSTATUS, H_COREMEM_REGISTERS_MEMPROTECT, H_COREMEM_REGISTERS_MEMRESERVE
|
||||||
|
} CRMEM_NAMES;
|
||||||
|
|
||||||
|
/* Enum declaration for . */
|
||||||
|
typedef enum crmesh_names {
|
||||||
|
H_COREMESH_REGISTERS_MESHCONFIG, H_COREMESH_REGISTERS_COREID, H_COREMESH_REGISTERS_MESHMULTICAST, H_COREMESH_REGISTERS_SWRESET
|
||||||
|
} CRMESH_NAMES;
|
||||||
|
|
||||||
|
/* Attributes. */
|
||||||
|
|
||||||
|
/* Enum declaration for machine type selection. */
|
||||||
|
typedef enum mach_attr {
|
||||||
|
MACH_BASE, MACH_EPIPHANY32, MACH_MAX
|
||||||
|
} MACH_ATTR;
|
||||||
|
|
||||||
|
/* Enum declaration for instruction set selection. */
|
||||||
|
typedef enum isa_attr {
|
||||||
|
ISA_EPIPHANY, ISA_MAX
|
||||||
|
} ISA_ATTR;
|
||||||
|
|
||||||
|
/* Number of architecture variants. */
|
||||||
|
#define MAX_ISAS 1
|
||||||
|
#define MAX_MACHS ((int) MACH_MAX)
|
||||||
|
|
||||||
|
/* Ifield support. */
|
||||||
|
|
||||||
|
/* Ifield attribute indices. */
|
||||||
|
|
||||||
|
/* Enum declaration for cgen_ifld attrs. */
|
||||||
|
typedef enum cgen_ifld_attr {
|
||||||
|
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
|
||||||
|
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
|
||||||
|
, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
|
||||||
|
} CGEN_IFLD_ATTR;
|
||||||
|
|
||||||
|
/* Number of non-boolean elements in cgen_ifld_attr. */
|
||||||
|
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
|
||||||
|
|
||||||
|
/* cgen_ifld attribute accessor macros. */
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0)
|
||||||
|
|
||||||
|
/* Enum declaration for epiphany ifield types. */
|
||||||
|
typedef enum ifield_type {
|
||||||
|
EPIPHANY_F_NIL, EPIPHANY_F_ANYOF, EPIPHANY_F_OPC, EPIPHANY_F_OPC_4_1
|
||||||
|
, EPIPHANY_F_OPC_6_3, EPIPHANY_F_OPC_8_5, EPIPHANY_F_OPC_19_4, EPIPHANY_F_CONDCODE
|
||||||
|
, EPIPHANY_F_SECONDARY_CCS, EPIPHANY_F_SHIFT, EPIPHANY_F_WORDSIZE, EPIPHANY_F_STORE
|
||||||
|
, EPIPHANY_F_OPC_8_1, EPIPHANY_F_OPC_31_32, EPIPHANY_F_SIMM8, EPIPHANY_F_SIMM24
|
||||||
|
, EPIPHANY_F_SDISP3, EPIPHANY_F_DISP3, EPIPHANY_F_DISP8, EPIPHANY_F_IMM8
|
||||||
|
, EPIPHANY_F_IMM_27_8, EPIPHANY_F_ADDSUBX, EPIPHANY_F_SUBD, EPIPHANY_F_PM
|
||||||
|
, EPIPHANY_F_RM, EPIPHANY_F_RN, EPIPHANY_F_RD, EPIPHANY_F_RM_X
|
||||||
|
, EPIPHANY_F_RN_X, EPIPHANY_F_RD_X, EPIPHANY_F_DC_9_1, EPIPHANY_F_SN
|
||||||
|
, EPIPHANY_F_SD, EPIPHANY_F_SN_X, EPIPHANY_F_SD_X, EPIPHANY_F_DC_7_4
|
||||||
|
, EPIPHANY_F_TRAP_SWI_9_1, EPIPHANY_F_GIEN_GIDIS_9_1, EPIPHANY_F_DC_15_3, EPIPHANY_F_DC_15_7
|
||||||
|
, EPIPHANY_F_DC_15_6, EPIPHANY_F_TRAP_NUM, EPIPHANY_F_DC_20_1, EPIPHANY_F_DC_21_1
|
||||||
|
, EPIPHANY_F_DC_21_2, EPIPHANY_F_DC_22_3, EPIPHANY_F_DC_22_2, EPIPHANY_F_DC_22_1
|
||||||
|
, EPIPHANY_F_DC_25_6, EPIPHANY_F_DC_25_4, EPIPHANY_F_DC_25_2, EPIPHANY_F_DC_25_1
|
||||||
|
, EPIPHANY_F_DC_28_1, EPIPHANY_F_DC_31_3, EPIPHANY_F_DISP11, EPIPHANY_F_SDISP11
|
||||||
|
, EPIPHANY_F_IMM16, EPIPHANY_F_RD6, EPIPHANY_F_RN6, EPIPHANY_F_RM6
|
||||||
|
, EPIPHANY_F_SD6, EPIPHANY_F_SN6, EPIPHANY_F_MAX
|
||||||
|
} IFIELD_TYPE;
|
||||||
|
|
||||||
|
#define MAX_IFLD ((int) EPIPHANY_F_MAX)
|
||||||
|
|
||||||
|
/* Hardware attribute indices. */
|
||||||
|
|
||||||
|
/* Enum declaration for cgen_hw attrs. */
|
||||||
|
typedef enum cgen_hw_attr {
|
||||||
|
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
|
||||||
|
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
|
||||||
|
} CGEN_HW_ATTR;
|
||||||
|
|
||||||
|
/* Number of non-boolean elements in cgen_hw_attr. */
|
||||||
|
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
|
||||||
|
|
||||||
|
/* cgen_hw attribute accessor macros. */
|
||||||
|
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
|
||||||
|
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
|
||||||
|
|
||||||
|
/* Enum declaration for epiphany hardware types. */
|
||||||
|
typedef enum cgen_hw_type {
|
||||||
|
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
|
||||||
|
, HW_H_IADDR, HW_H_REGISTERS, HW_H_FPREGISTERS, HW_H_ZBIT
|
||||||
|
, HW_H_NBIT, HW_H_CBIT, HW_H_VBIT, HW_H_VSBIT
|
||||||
|
, HW_H_BZBIT, HW_H_BNBIT, HW_H_BVBIT, HW_H_BUBIT
|
||||||
|
, HW_H_BIBIT, HW_H_BCBIT, HW_H_BVSBIT, HW_H_BISBIT
|
||||||
|
, HW_H_BUSBIT, HW_H_EXPCAUSE0BIT, HW_H_EXPCAUSE1BIT, HW_H_EXPCAUSE2BIT
|
||||||
|
, HW_H_EXTFSTALLBIT, HW_H_TRMBIT, HW_H_INVEXCENBIT, HW_H_OVFEXCENBIT
|
||||||
|
, HW_H_UNEXCENBIT, HW_H_TIMER0BIT0, HW_H_TIMER0BIT1, HW_H_TIMER0BIT2
|
||||||
|
, HW_H_TIMER0BIT3, HW_H_TIMER1BIT0, HW_H_TIMER1BIT1, HW_H_TIMER1BIT2
|
||||||
|
, HW_H_TIMER1BIT3, HW_H_MBKPTENBIT, HW_H_CLOCKGATEENBIT, HW_H_CORECFGRESBIT12
|
||||||
|
, HW_H_CORECFGRESBIT13, HW_H_CORECFGRESBIT14, HW_H_CORECFGRESBIT15, HW_H_CORECFGRESBIT16
|
||||||
|
, HW_H_CORECFGRESBIT20, HW_H_CORECFGRESBIT21, HW_H_CORECFGRESBIT24, HW_H_CORECFGRESBIT25
|
||||||
|
, HW_H_CORECFGRESBIT26, HW_H_CORECFGRESBIT27, HW_H_CORECFGRESBIT28, HW_H_CORECFGRESBIT29
|
||||||
|
, HW_H_CORECFGRESBIT30, HW_H_CORECFGRESBIT31, HW_H_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT1
|
||||||
|
, HW_H_ARITHMETIC_MODEBIT2, HW_H_GIDISABLEBIT, HW_H_KMBIT, HW_H_CAIBIT
|
||||||
|
, HW_H_SFLAGBIT, HW_H_PC, HW_H_MEMADDR, HW_H_CORE_REGISTERS
|
||||||
|
, HW_H_COREDMA_REGISTERS, HW_H_COREMEM_REGISTERS, HW_H_COREMESH_REGISTERS, HW_MAX
|
||||||
|
} CGEN_HW_TYPE;
|
||||||
|
|
||||||
|
#define MAX_HW ((int) HW_MAX)
|
||||||
|
|
||||||
|
/* Operand attribute indices. */
|
||||||
|
|
||||||
|
/* Enum declaration for cgen_operand attrs. */
|
||||||
|
typedef enum cgen_operand_attr {
|
||||||
|
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
|
||||||
|
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
|
||||||
|
, CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
|
||||||
|
, CGEN_OPERAND_END_NBOOLS
|
||||||
|
} CGEN_OPERAND_ATTR;
|
||||||
|
|
||||||
|
/* Number of non-boolean elements in cgen_operand_attr. */
|
||||||
|
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
|
||||||
|
|
||||||
|
/* cgen_operand attribute accessor macros. */
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0)
|
||||||
|
|
||||||
|
/* Enum declaration for epiphany operand types. */
|
||||||
|
typedef enum cgen_operand_type {
|
||||||
|
EPIPHANY_OPERAND_PC, EPIPHANY_OPERAND_ZBIT, EPIPHANY_OPERAND_NBIT, EPIPHANY_OPERAND_CBIT
|
||||||
|
, EPIPHANY_OPERAND_VBIT, EPIPHANY_OPERAND_BZBIT, EPIPHANY_OPERAND_BNBIT, EPIPHANY_OPERAND_BVBIT
|
||||||
|
, EPIPHANY_OPERAND_BCBIT, EPIPHANY_OPERAND_BUBIT, EPIPHANY_OPERAND_BIBIT, EPIPHANY_OPERAND_VSBIT
|
||||||
|
, EPIPHANY_OPERAND_BVSBIT, EPIPHANY_OPERAND_BISBIT, EPIPHANY_OPERAND_BUSBIT, EPIPHANY_OPERAND_EXPCAUSE0BIT
|
||||||
|
, EPIPHANY_OPERAND_EXPCAUSE1BIT, EPIPHANY_OPERAND_EXPCAUSE2BIT, EPIPHANY_OPERAND_EXTFSTALLBIT, EPIPHANY_OPERAND_TRMBIT
|
||||||
|
, EPIPHANY_OPERAND_INVEXCENBIT, EPIPHANY_OPERAND_OVFEXCENBIT, EPIPHANY_OPERAND_UNEXCENBIT, EPIPHANY_OPERAND_TIMER0BIT0
|
||||||
|
, EPIPHANY_OPERAND_TIMER0BIT1, EPIPHANY_OPERAND_TIMER0BIT2, EPIPHANY_OPERAND_TIMER0BIT3, EPIPHANY_OPERAND_TIMER1BIT0
|
||||||
|
, EPIPHANY_OPERAND_TIMER1BIT1, EPIPHANY_OPERAND_TIMER1BIT2, EPIPHANY_OPERAND_TIMER1BIT3, EPIPHANY_OPERAND_MBKPTENBIT
|
||||||
|
, EPIPHANY_OPERAND_CLOCKGATEENBIT, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2
|
||||||
|
, EPIPHANY_OPERAND_CORECFGRESBIT12, EPIPHANY_OPERAND_CORECFGRESBIT13, EPIPHANY_OPERAND_CORECFGRESBIT14, EPIPHANY_OPERAND_CORECFGRESBIT15
|
||||||
|
, EPIPHANY_OPERAND_CORECFGRESBIT16, EPIPHANY_OPERAND_CORECFGRESBIT20, EPIPHANY_OPERAND_CORECFGRESBIT21, EPIPHANY_OPERAND_CORECFGRESBIT24
|
||||||
|
, EPIPHANY_OPERAND_CORECFGRESBIT25, EPIPHANY_OPERAND_CORECFGRESBIT26, EPIPHANY_OPERAND_CORECFGRESBIT27, EPIPHANY_OPERAND_CORECFGRESBIT28
|
||||||
|
, EPIPHANY_OPERAND_CORECFGRESBIT29, EPIPHANY_OPERAND_CORECFGRESBIT30, EPIPHANY_OPERAND_CORECFGRESBIT31, EPIPHANY_OPERAND_GIDISABLEBIT
|
||||||
|
, EPIPHANY_OPERAND_KMBIT, EPIPHANY_OPERAND_CAIBIT, EPIPHANY_OPERAND_SFLAGBIT, EPIPHANY_OPERAND_MEMADDR
|
||||||
|
, EPIPHANY_OPERAND_SIMM24, EPIPHANY_OPERAND_SIMM8, EPIPHANY_OPERAND_RD, EPIPHANY_OPERAND_RN
|
||||||
|
, EPIPHANY_OPERAND_RM, EPIPHANY_OPERAND_FRD, EPIPHANY_OPERAND_FRN, EPIPHANY_OPERAND_FRM
|
||||||
|
, EPIPHANY_OPERAND_RD6, EPIPHANY_OPERAND_RN6, EPIPHANY_OPERAND_RM6, EPIPHANY_OPERAND_FRD6
|
||||||
|
, EPIPHANY_OPERAND_FRN6, EPIPHANY_OPERAND_FRM6, EPIPHANY_OPERAND_SD, EPIPHANY_OPERAND_SN
|
||||||
|
, EPIPHANY_OPERAND_SD6, EPIPHANY_OPERAND_SN6, EPIPHANY_OPERAND_SDDMA, EPIPHANY_OPERAND_SNDMA
|
||||||
|
, EPIPHANY_OPERAND_SDMEM, EPIPHANY_OPERAND_SNMEM, EPIPHANY_OPERAND_SDMESH, EPIPHANY_OPERAND_SNMESH
|
||||||
|
, EPIPHANY_OPERAND_SIMM3, EPIPHANY_OPERAND_SIMM11, EPIPHANY_OPERAND_DISP3, EPIPHANY_OPERAND_TRAPNUM6
|
||||||
|
, EPIPHANY_OPERAND_SWI_NUM, EPIPHANY_OPERAND_DISP11, EPIPHANY_OPERAND_SHIFT, EPIPHANY_OPERAND_IMM16
|
||||||
|
, EPIPHANY_OPERAND_IMM8, EPIPHANY_OPERAND_DIRECTION, EPIPHANY_OPERAND_DPMI, EPIPHANY_OPERAND_MAX
|
||||||
|
} CGEN_OPERAND_TYPE;
|
||||||
|
|
||||||
|
/* Number of operands types. */
|
||||||
|
#define MAX_OPERANDS 91
|
||||||
|
|
||||||
|
/* Maximum number of operands referenced by any insn. */
|
||||||
|
#define MAX_OPERAND_INSTANCES 8
|
||||||
|
|
||||||
|
/* Insn attribute indices. */
|
||||||
|
|
||||||
|
/* Enum declaration for cgen_insn attrs. */
|
||||||
|
typedef enum cgen_insn_attr {
|
||||||
|
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
|
||||||
|
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
|
||||||
|
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_SHORT_INSN, CGEN_INSN_IMM3
|
||||||
|
, CGEN_INSN_IMM8, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
|
||||||
|
, CGEN_INSN_END_NBOOLS
|
||||||
|
} CGEN_INSN_ATTR;
|
||||||
|
|
||||||
|
/* Number of non-boolean elements in cgen_insn_attr. */
|
||||||
|
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
|
||||||
|
|
||||||
|
/* cgen_insn attribute accessor macros. */
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_SHORT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SHORT_INSN)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_IMM3_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM3)) != 0)
|
||||||
|
#define CGEN_ATTR_CGEN_INSN_IMM8_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM8)) != 0)
|
||||||
|
|
||||||
|
/* cgen.h uses things we just defined. */
|
||||||
|
#include "opcode/cgen.h"
|
||||||
|
|
||||||
|
extern const struct cgen_ifld epiphany_cgen_ifld_table[];
|
||||||
|
|
||||||
|
/* Attributes. */
|
||||||
|
extern const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[];
|
||||||
|
extern const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[];
|
||||||
|
extern const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[];
|
||||||
|
extern const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[];
|
||||||
|
|
||||||
|
/* Hardware decls. */
|
||||||
|
|
||||||
|
extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
|
||||||
|
extern CGEN_KEYWORD epiphany_cgen_opval_gr_names;
|
||||||
|
extern CGEN_KEYWORD epiphany_cgen_opval_cr_names;
|
||||||
|
extern CGEN_KEYWORD epiphany_cgen_opval_crdma_names;
|
||||||
|
extern CGEN_KEYWORD epiphany_cgen_opval_crmem_names;
|
||||||
|
extern CGEN_KEYWORD epiphany_cgen_opval_crmesh_names;
|
||||||
|
|
||||||
|
extern const CGEN_HW_ENTRY epiphany_cgen_hw_table[];
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* EPIPHANY_CPU_H */
|
||||||
698
opcodes/epiphany-dis.c
Normal file
698
opcodes/epiphany-dis.c
Normal file
@ -0,0 +1,698 @@
|
|||||||
|
/* Disassembler interface for targets using CGEN. -*- C -*-
|
||||||
|
CGEN: Cpu tools GENerator
|
||||||
|
|
||||||
|
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||||
|
- the resultant file is machine generated, cgen-dis.in isn't
|
||||||
|
|
||||||
|
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
|
||||||
|
2008, 2010 Free Software Foundation, Inc.
|
||||||
|
|
||||||
|
This file is part of libopcodes.
|
||||||
|
|
||||||
|
This library is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3, or (at your option)
|
||||||
|
any later version.
|
||||||
|
|
||||||
|
It is distributed in the hope that it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||||
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||||
|
License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||||
|
|
||||||
|
/* ??? Eventually more and more of this stuff can go to cpu-independent files.
|
||||||
|
Keep that in mind. */
|
||||||
|
|
||||||
|
#include "sysdep.h"
|
||||||
|
#include <stdio.h>
|
||||||
|
#include "ansidecl.h"
|
||||||
|
#include "dis-asm.h"
|
||||||
|
#include "bfd.h"
|
||||||
|
#include "symcat.h"
|
||||||
|
#include "libiberty.h"
|
||||||
|
#include "epiphany-desc.h"
|
||||||
|
#include "epiphany-opc.h"
|
||||||
|
#include "opintl.h"
|
||||||
|
|
||||||
|
/* Default text to print if an instruction isn't recognized. */
|
||||||
|
#define UNKNOWN_INSN_MSG _("*unknown*")
|
||||||
|
|
||||||
|
static void print_normal
|
||||||
|
(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
|
||||||
|
static void print_address
|
||||||
|
(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
|
||||||
|
static void print_keyword
|
||||||
|
(CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
|
||||||
|
static void print_insn_normal
|
||||||
|
(CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
|
||||||
|
static int print_insn
|
||||||
|
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
|
||||||
|
static int default_print_insn
|
||||||
|
(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
|
||||||
|
static int read_insn
|
||||||
|
(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
|
||||||
|
unsigned long *);
|
||||||
|
|
||||||
|
/* -- disassembler routines inserted here. */
|
||||||
|
|
||||||
|
/* -- dis.c */
|
||||||
|
|
||||||
|
#define CGEN_PRINT_INSN epiphany_print_insn
|
||||||
|
|
||||||
|
static int
|
||||||
|
epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||||
|
{
|
||||||
|
bfd_byte buf[CGEN_MAX_INSN_SIZE];
|
||||||
|
int buflen;
|
||||||
|
int status;
|
||||||
|
|
||||||
|
info->bytes_per_chunk = 2;
|
||||||
|
|
||||||
|
/* Attempt to read the base part of the insn. */
|
||||||
|
info->bytes_per_line = buflen = cd->base_insn_bitsize / 8;
|
||||||
|
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||||
|
|
||||||
|
/* Try again with the minimum part, if min < base. */
|
||||||
|
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
|
||||||
|
{
|
||||||
|
info->bytes_per_line = buflen = cd->min_insn_bitsize / 8;
|
||||||
|
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status != 0)
|
||||||
|
{
|
||||||
|
(*info->memory_error_func) (status, pc, info);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return print_insn (cd, pc, info, buf, buflen);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void * dis_info,
|
||||||
|
long value,
|
||||||
|
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *) dis_info;
|
||||||
|
(*info->fprintf_func) (info->stream, value ? "-" : "+");
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void * dis_info,
|
||||||
|
long value,
|
||||||
|
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
print_address (cd, dis_info, value, attrs, pc, length);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void * dis_info,
|
||||||
|
unsigned long value,
|
||||||
|
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *)dis_info;
|
||||||
|
|
||||||
|
if (value & 0x800)
|
||||||
|
(*info->fprintf_func) (info->stream, "-");
|
||||||
|
|
||||||
|
value &= 0x7ff;
|
||||||
|
print_address (cd, dis_info, value, attrs, pc, length);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* -- */
|
||||||
|
|
||||||
|
void epiphany_cgen_print_operand
|
||||||
|
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
|
||||||
|
|
||||||
|
/* Main entry point for printing operands.
|
||||||
|
XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
|
||||||
|
of dis-asm.h on cgen.h.
|
||||||
|
|
||||||
|
This function is basically just a big switch statement. Earlier versions
|
||||||
|
used tables to look up the function to use, but
|
||||||
|
- if the table contains both assembler and disassembler functions then
|
||||||
|
the disassembler contains much of the assembler and vice-versa,
|
||||||
|
- there's a lot of inlining possibilities as things grow,
|
||||||
|
- using a switch statement avoids the function call overhead.
|
||||||
|
|
||||||
|
This function could be moved into `print_insn_normal', but keeping it
|
||||||
|
separate makes clear the interface between `print_insn_normal' and each of
|
||||||
|
the handlers. */
|
||||||
|
|
||||||
|
void
|
||||||
|
epiphany_cgen_print_operand (CGEN_CPU_DESC cd,
|
||||||
|
int opindex,
|
||||||
|
void * xinfo,
|
||||||
|
CGEN_FIELDS *fields,
|
||||||
|
void const *attrs ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc,
|
||||||
|
int length)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *) xinfo;
|
||||||
|
|
||||||
|
switch (opindex)
|
||||||
|
{
|
||||||
|
case EPIPHANY_OPERAND_DIRECTION :
|
||||||
|
print_postindex (cd, info, fields->f_addsubx, 0, pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_DISP11 :
|
||||||
|
print_uimm_not_reg (cd, info, fields->f_disp11, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_DISP3 :
|
||||||
|
print_normal (cd, info, fields->f_disp3, 0, pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_DPMI :
|
||||||
|
print_postindex (cd, info, fields->f_subd, 0, pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRD :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRD6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRM :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRM6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRN :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_FRN6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_IMM16 :
|
||||||
|
print_address (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_IMM8 :
|
||||||
|
print_address (cd, info, fields->f_imm8, 0|(1<<CGEN_OPERAND_RELAX), pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RD :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RD6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RM :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RM6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RN :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_RN6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SD :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SD6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SDDMA :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SDMEM :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SDMESH :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SHIFT :
|
||||||
|
print_normal (cd, info, fields->f_shift, 0, pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM11 :
|
||||||
|
print_simm_not_reg (cd, info, fields->f_sdisp11, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM24 :
|
||||||
|
print_address (cd, info, fields->f_simm24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM3 :
|
||||||
|
print_simm_not_reg (cd, info, fields->f_sdisp3, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX), pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SIMM8 :
|
||||||
|
print_address (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SN :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn, 0);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SN6 :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SNDMA :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SNMEM :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SNMESH :
|
||||||
|
print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_SWI_NUM :
|
||||||
|
print_uimm_not_reg (cd, info, fields->f_trap_num, 0, pc, length);
|
||||||
|
break;
|
||||||
|
case EPIPHANY_OPERAND_TRAPNUM6 :
|
||||||
|
print_normal (cd, info, fields->f_trap_num, 0, pc, length);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default :
|
||||||
|
/* xgettext:c-format */
|
||||||
|
fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
|
||||||
|
opindex);
|
||||||
|
abort ();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
cgen_print_fn * const epiphany_cgen_print_handlers[] =
|
||||||
|
{
|
||||||
|
print_insn_normal,
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
void
|
||||||
|
epiphany_cgen_init_dis (CGEN_CPU_DESC cd)
|
||||||
|
{
|
||||||
|
epiphany_cgen_init_opcode_table (cd);
|
||||||
|
epiphany_cgen_init_ibld_table (cd);
|
||||||
|
cd->print_handlers = & epiphany_cgen_print_handlers[0];
|
||||||
|
cd->print_operand = epiphany_cgen_print_operand;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Default print handler. */
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void *dis_info,
|
||||||
|
long value,
|
||||||
|
unsigned int attrs,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *) dis_info;
|
||||||
|
|
||||||
|
/* Print the operand as directed by the attributes. */
|
||||||
|
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
|
||||||
|
; /* nothing to do */
|
||||||
|
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
|
||||||
|
(*info->fprintf_func) (info->stream, "%ld", value);
|
||||||
|
else
|
||||||
|
(*info->fprintf_func) (info->stream, "0x%lx", value);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Default address handler. */
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void *dis_info,
|
||||||
|
bfd_vma value,
|
||||||
|
unsigned int attrs,
|
||||||
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||||
|
int length ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *) dis_info;
|
||||||
|
|
||||||
|
/* Print the operand as directed by the attributes. */
|
||||||
|
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
|
||||||
|
; /* Nothing to do. */
|
||||||
|
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
|
||||||
|
(*info->print_address_func) (value, info);
|
||||||
|
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
|
||||||
|
(*info->print_address_func) (value, info);
|
||||||
|
else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
|
||||||
|
(*info->fprintf_func) (info->stream, "%ld", (long) value);
|
||||||
|
else
|
||||||
|
(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Keyword print handler. */
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
void *dis_info,
|
||||||
|
CGEN_KEYWORD *keyword_table,
|
||||||
|
long value,
|
||||||
|
unsigned int attrs ATTRIBUTE_UNUSED)
|
||||||
|
{
|
||||||
|
disassemble_info *info = (disassemble_info *) dis_info;
|
||||||
|
const CGEN_KEYWORD_ENTRY *ke;
|
||||||
|
|
||||||
|
ke = cgen_keyword_lookup_value (keyword_table, value);
|
||||||
|
if (ke != NULL)
|
||||||
|
(*info->fprintf_func) (info->stream, "%s", ke->name);
|
||||||
|
else
|
||||||
|
(*info->fprintf_func) (info->stream, "???");
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Default insn printer.
|
||||||
|
|
||||||
|
DIS_INFO is defined as `void *' so the disassembler needn't know anything
|
||||||
|
about disassemble_info. */
|
||||||
|
|
||||||
|
static void
|
||||||
|
print_insn_normal (CGEN_CPU_DESC cd,
|
||||||
|
void *dis_info,
|
||||||
|
const CGEN_INSN *insn,
|
||||||
|
CGEN_FIELDS *fields,
|
||||||
|
bfd_vma pc,
|
||||||
|
int length)
|
||||||
|
{
|
||||||
|
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
||||||
|
disassemble_info *info = (disassemble_info *) dis_info;
|
||||||
|
const CGEN_SYNTAX_CHAR_TYPE *syn;
|
||||||
|
|
||||||
|
CGEN_INIT_PRINT (cd);
|
||||||
|
|
||||||
|
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
||||||
|
{
|
||||||
|
if (CGEN_SYNTAX_MNEMONIC_P (*syn))
|
||||||
|
{
|
||||||
|
(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (CGEN_SYNTAX_CHAR_P (*syn))
|
||||||
|
{
|
||||||
|
(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* We have an operand. */
|
||||||
|
epiphany_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
|
||||||
|
fields, CGEN_INSN_ATTRS (insn), pc, length);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
|
||||||
|
the extract info.
|
||||||
|
Returns 0 if all is well, non-zero otherwise. */
|
||||||
|
|
||||||
|
static int
|
||||||
|
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||||
|
bfd_vma pc,
|
||||||
|
disassemble_info *info,
|
||||||
|
bfd_byte *buf,
|
||||||
|
int buflen,
|
||||||
|
CGEN_EXTRACT_INFO *ex_info,
|
||||||
|
unsigned long *insn_value)
|
||||||
|
{
|
||||||
|
int status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||||
|
|
||||||
|
if (status != 0)
|
||||||
|
{
|
||||||
|
(*info->memory_error_func) (status, pc, info);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
ex_info->dis_info = info;
|
||||||
|
ex_info->valid = (1 << buflen) - 1;
|
||||||
|
ex_info->insn_bytes = buf;
|
||||||
|
|
||||||
|
*insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Utility to print an insn.
|
||||||
|
BUF is the base part of the insn, target byte order, BUFLEN bytes long.
|
||||||
|
The result is the size of the insn in bytes or zero for an unknown insn
|
||||||
|
or -1 if an error occurs fetching data (memory_error_func will have
|
||||||
|
been called). */
|
||||||
|
|
||||||
|
static int
|
||||||
|
print_insn (CGEN_CPU_DESC cd,
|
||||||
|
bfd_vma pc,
|
||||||
|
disassemble_info *info,
|
||||||
|
bfd_byte *buf,
|
||||||
|
unsigned int buflen)
|
||||||
|
{
|
||||||
|
CGEN_INSN_INT insn_value;
|
||||||
|
const CGEN_INSN_LIST *insn_list;
|
||||||
|
CGEN_EXTRACT_INFO ex_info;
|
||||||
|
int basesize;
|
||||||
|
|
||||||
|
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
|
||||||
|
basesize = cd->base_insn_bitsize < buflen * 8 ?
|
||||||
|
cd->base_insn_bitsize : buflen * 8;
|
||||||
|
insn_value = cgen_get_insn_value (cd, buf, basesize);
|
||||||
|
|
||||||
|
|
||||||
|
/* Fill in ex_info fields like read_insn would. Don't actually call
|
||||||
|
read_insn, since the incoming buffer is already read (and possibly
|
||||||
|
modified a la m32r). */
|
||||||
|
ex_info.valid = (1 << buflen) - 1;
|
||||||
|
ex_info.dis_info = info;
|
||||||
|
ex_info.insn_bytes = buf;
|
||||||
|
|
||||||
|
/* The instructions are stored in hash lists.
|
||||||
|
Pick the first one and keep trying until we find the right one. */
|
||||||
|
|
||||||
|
insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
|
||||||
|
while (insn_list != NULL)
|
||||||
|
{
|
||||||
|
const CGEN_INSN *insn = insn_list->insn;
|
||||||
|
CGEN_FIELDS fields;
|
||||||
|
int length;
|
||||||
|
unsigned long insn_value_cropped;
|
||||||
|
|
||||||
|
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
|
||||||
|
/* Not needed as insn shouldn't be in hash lists if not supported. */
|
||||||
|
/* Supported by this cpu? */
|
||||||
|
if (! epiphany_cgen_insn_supported (cd, insn))
|
||||||
|
{
|
||||||
|
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Basic bit mask must be correct. */
|
||||||
|
/* ??? May wish to allow target to defer this check until the extract
|
||||||
|
handler. */
|
||||||
|
|
||||||
|
/* Base size may exceed this instruction's size. Extract the
|
||||||
|
relevant part from the buffer. */
|
||||||
|
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
|
||||||
|
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
|
||||||
|
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
|
||||||
|
info->endian == BFD_ENDIAN_BIG);
|
||||||
|
else
|
||||||
|
insn_value_cropped = insn_value;
|
||||||
|
|
||||||
|
if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
|
||||||
|
== CGEN_INSN_BASE_VALUE (insn))
|
||||||
|
{
|
||||||
|
/* Printing is handled in two passes. The first pass parses the
|
||||||
|
machine insn and extracts the fields. The second pass prints
|
||||||
|
them. */
|
||||||
|
|
||||||
|
/* Make sure the entire insn is loaded into insn_value, if it
|
||||||
|
can fit. */
|
||||||
|
if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
|
||||||
|
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
|
||||||
|
{
|
||||||
|
unsigned long full_insn_value;
|
||||||
|
int rc = read_insn (cd, pc, info, buf,
|
||||||
|
CGEN_INSN_BITSIZE (insn) / 8,
|
||||||
|
& ex_info, & full_insn_value);
|
||||||
|
if (rc != 0)
|
||||||
|
return rc;
|
||||||
|
length = CGEN_EXTRACT_FN (cd, insn)
|
||||||
|
(cd, insn, &ex_info, full_insn_value, &fields, pc);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
length = CGEN_EXTRACT_FN (cd, insn)
|
||||||
|
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
|
||||||
|
|
||||||
|
/* Length < 0 -> error. */
|
||||||
|
if (length < 0)
|
||||||
|
return length;
|
||||||
|
if (length > 0)
|
||||||
|
{
|
||||||
|
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
|
||||||
|
/* Length is in bits, result is in bytes. */
|
||||||
|
return length / 8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Default value for CGEN_PRINT_INSN.
|
||||||
|
The result is the size of the insn in bytes or zero for an unknown insn
|
||||||
|
or -1 if an error occured fetching bytes. */
|
||||||
|
|
||||||
|
#ifndef CGEN_PRINT_INSN
|
||||||
|
#define CGEN_PRINT_INSN default_print_insn
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static int
|
||||||
|
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||||
|
{
|
||||||
|
bfd_byte buf[CGEN_MAX_INSN_SIZE];
|
||||||
|
int buflen;
|
||||||
|
int status;
|
||||||
|
|
||||||
|
/* Attempt to read the base part of the insn. */
|
||||||
|
buflen = cd->base_insn_bitsize / 8;
|
||||||
|
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||||
|
|
||||||
|
/* Try again with the minimum part, if min < base. */
|
||||||
|
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
|
||||||
|
{
|
||||||
|
buflen = cd->min_insn_bitsize / 8;
|
||||||
|
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status != 0)
|
||||||
|
{
|
||||||
|
(*info->memory_error_func) (status, pc, info);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return print_insn (cd, pc, info, buf, buflen);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Main entry point.
|
||||||
|
Print one instruction from PC on INFO->STREAM.
|
||||||
|
Return the size of the instruction (in bytes). */
|
||||||
|
|
||||||
|
typedef struct cpu_desc_list
|
||||||
|
{
|
||||||
|
struct cpu_desc_list *next;
|
||||||
|
CGEN_BITSET *isa;
|
||||||
|
int mach;
|
||||||
|
int endian;
|
||||||
|
CGEN_CPU_DESC cd;
|
||||||
|
} cpu_desc_list;
|
||||||
|
|
||||||
|
int
|
||||||
|
print_insn_epiphany (bfd_vma pc, disassemble_info *info)
|
||||||
|
{
|
||||||
|
static cpu_desc_list *cd_list = 0;
|
||||||
|
cpu_desc_list *cl = 0;
|
||||||
|
static CGEN_CPU_DESC cd = 0;
|
||||||
|
static CGEN_BITSET *prev_isa;
|
||||||
|
static int prev_mach;
|
||||||
|
static int prev_endian;
|
||||||
|
int length;
|
||||||
|
CGEN_BITSET *isa;
|
||||||
|
int mach;
|
||||||
|
int endian = (info->endian == BFD_ENDIAN_BIG
|
||||||
|
? CGEN_ENDIAN_BIG
|
||||||
|
: CGEN_ENDIAN_LITTLE);
|
||||||
|
enum bfd_architecture arch;
|
||||||
|
|
||||||
|
/* ??? gdb will set mach but leave the architecture as "unknown" */
|
||||||
|
#ifndef CGEN_BFD_ARCH
|
||||||
|
#define CGEN_BFD_ARCH bfd_arch_epiphany
|
||||||
|
#endif
|
||||||
|
arch = info->arch;
|
||||||
|
if (arch == bfd_arch_unknown)
|
||||||
|
arch = CGEN_BFD_ARCH;
|
||||||
|
|
||||||
|
/* There's no standard way to compute the machine or isa number
|
||||||
|
so we leave it to the target. */
|
||||||
|
#ifdef CGEN_COMPUTE_MACH
|
||||||
|
mach = CGEN_COMPUTE_MACH (info);
|
||||||
|
#else
|
||||||
|
mach = info->mach;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CGEN_COMPUTE_ISA
|
||||||
|
{
|
||||||
|
static CGEN_BITSET *permanent_isa;
|
||||||
|
|
||||||
|
if (!permanent_isa)
|
||||||
|
permanent_isa = cgen_bitset_create (MAX_ISAS);
|
||||||
|
isa = permanent_isa;
|
||||||
|
cgen_bitset_clear (isa);
|
||||||
|
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
isa = info->insn_sets;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* If we've switched cpu's, try to find a handle we've used before */
|
||||||
|
if (cd
|
||||||
|
&& (cgen_bitset_compare (isa, prev_isa) != 0
|
||||||
|
|| mach != prev_mach
|
||||||
|
|| endian != prev_endian))
|
||||||
|
{
|
||||||
|
cd = 0;
|
||||||
|
for (cl = cd_list; cl; cl = cl->next)
|
||||||
|
{
|
||||||
|
if (cgen_bitset_compare (cl->isa, isa) == 0 &&
|
||||||
|
cl->mach == mach &&
|
||||||
|
cl->endian == endian)
|
||||||
|
{
|
||||||
|
cd = cl->cd;
|
||||||
|
prev_isa = cd->isas;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If we haven't initialized yet, initialize the opcode table. */
|
||||||
|
if (! cd)
|
||||||
|
{
|
||||||
|
const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
|
||||||
|
const char *mach_name;
|
||||||
|
|
||||||
|
if (!arch_type)
|
||||||
|
abort ();
|
||||||
|
mach_name = arch_type->printable_name;
|
||||||
|
|
||||||
|
prev_isa = cgen_bitset_copy (isa);
|
||||||
|
prev_mach = mach;
|
||||||
|
prev_endian = endian;
|
||||||
|
cd = epiphany_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
|
||||||
|
CGEN_CPU_OPEN_BFDMACH, mach_name,
|
||||||
|
CGEN_CPU_OPEN_ENDIAN, prev_endian,
|
||||||
|
CGEN_CPU_OPEN_END);
|
||||||
|
if (!cd)
|
||||||
|
abort ();
|
||||||
|
|
||||||
|
/* Save this away for future reference. */
|
||||||
|
cl = xmalloc (sizeof (struct cpu_desc_list));
|
||||||
|
cl->cd = cd;
|
||||||
|
cl->isa = prev_isa;
|
||||||
|
cl->mach = mach;
|
||||||
|
cl->endian = endian;
|
||||||
|
cl->next = cd_list;
|
||||||
|
cd_list = cl;
|
||||||
|
|
||||||
|
epiphany_cgen_init_dis (cd);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* We try to have as much common code as possible.
|
||||||
|
But at this point some targets need to take over. */
|
||||||
|
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
|
||||||
|
but if not possible try to move this hook elsewhere rather than
|
||||||
|
have two hooks. */
|
||||||
|
length = CGEN_PRINT_INSN (cd, pc, info);
|
||||||
|
if (length > 0)
|
||||||
|
return length;
|
||||||
|
if (length < 0)
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||||||
|
return cd->default_insn_bitsize / 8;
|
||||||
|
}
|
||||||
1709
opcodes/epiphany-ibld.c
Normal file
1709
opcodes/epiphany-ibld.c
Normal file
File diff suppressed because it is too large
Load Diff
4035
opcodes/epiphany-opc.c
Normal file
4035
opcodes/epiphany-opc.c
Normal file
File diff suppressed because it is too large
Load Diff
226
opcodes/epiphany-opc.h
Normal file
226
opcodes/epiphany-opc.h
Normal file
@ -0,0 +1,226 @@
|
|||||||
|
/* Instruction opcode header for epiphany.
|
||||||
|
|
||||||
|
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||||
|
|
||||||
|
Copyright 1996-2010 Free Software Foundation, Inc.
|
||||||
|
|
||||||
|
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||||
|
|
||||||
|
This file is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3, or (at your option)
|
||||||
|
any later version.
|
||||||
|
|
||||||
|
It is distributed in the hope that it will be useful, but WITHOUT
|
||||||
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||||
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||||
|
License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License along
|
||||||
|
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef EPIPHANY_OPC_H
|
||||||
|
#define EPIPHANY_OPC_H
|
||||||
|
|
||||||
|
/* -- opc.h */
|
||||||
|
|
||||||
|
/* enumerate relaxation types for gas. */
|
||||||
|
typedef enum epiphany_relax_types
|
||||||
|
{
|
||||||
|
EPIPHANY_RELAX_NONE=0,
|
||||||
|
EPIPHANY_RELAX_NEED_RELAXING,
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */
|
||||||
|
EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */
|
||||||
|
EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */
|
||||||
|
EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */
|
||||||
|
|
||||||
|
EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */
|
||||||
|
EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */
|
||||||
|
|
||||||
|
} EPIPHANY_RELAX_TYPES;
|
||||||
|
|
||||||
|
/* Override disassembly hashing... */
|
||||||
|
|
||||||
|
/* Can only depend on instruction having 4 decode bits which gets us to the
|
||||||
|
major groups of 16/32 instructions. */
|
||||||
|
#undef CGEN_DIS_HASH_SIZE
|
||||||
|
#if 1
|
||||||
|
|
||||||
|
/* hash code on the 4 LSBs */
|
||||||
|
#define CGEN_DIS_HASH_SIZE 16
|
||||||
|
|
||||||
|
#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf)
|
||||||
|
#else
|
||||||
|
#define CGEN_DIS_HASH_SIZE 1
|
||||||
|
#define CGEN_DIS_HASH(buf, value) 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern const char * parse_shortregs (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
CGEN_KEYWORD * keywords,
|
||||||
|
long * valuep);
|
||||||
|
|
||||||
|
extern const char * parse_branch_addr (CGEN_CPU_DESC cd,
|
||||||
|
const char ** strp,
|
||||||
|
int opindex,
|
||||||
|
int opinfo,
|
||||||
|
enum cgen_parse_operand_result * resultp,
|
||||||
|
unsigned long * valuep);
|
||||||
|
|
||||||
|
/* Allows reason codes to be output when assembler errors occur. */
|
||||||
|
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||||||
|
|
||||||
|
|
||||||
|
/* -- opc.c */
|
||||||
|
/* Enum declaration for epiphany instruction types. */
|
||||||
|
typedef enum cgen_insn_type {
|
||||||
|
EPIPHANY_INSN_INVALID, EPIPHANY_INSN_BEQ16, EPIPHANY_INSN_BEQ, EPIPHANY_INSN_BNE16
|
||||||
|
, EPIPHANY_INSN_BNE, EPIPHANY_INSN_BGTU16, EPIPHANY_INSN_BGTU, EPIPHANY_INSN_BGTEU16
|
||||||
|
, EPIPHANY_INSN_BGTEU, EPIPHANY_INSN_BLTEU16, EPIPHANY_INSN_BLTEU, EPIPHANY_INSN_BLTU16
|
||||||
|
, EPIPHANY_INSN_BLTU, EPIPHANY_INSN_BGT16, EPIPHANY_INSN_BGT, EPIPHANY_INSN_BGTE16
|
||||||
|
, EPIPHANY_INSN_BGTE, EPIPHANY_INSN_BLT16, EPIPHANY_INSN_BLT, EPIPHANY_INSN_BLTE16
|
||||||
|
, EPIPHANY_INSN_BLTE, EPIPHANY_INSN_BBEQ16, EPIPHANY_INSN_BBEQ, EPIPHANY_INSN_BBNE16
|
||||||
|
, EPIPHANY_INSN_BBNE, EPIPHANY_INSN_BBLT16, EPIPHANY_INSN_BBLT, EPIPHANY_INSN_BBLTE16
|
||||||
|
, EPIPHANY_INSN_BBLTE, EPIPHANY_INSN_B16, EPIPHANY_INSN_B, EPIPHANY_INSN_BL16
|
||||||
|
, EPIPHANY_INSN_BL, EPIPHANY_INSN_JR16, EPIPHANY_INSN_RTS, EPIPHANY_INSN_JR
|
||||||
|
, EPIPHANY_INSN_JALR16, EPIPHANY_INSN_JALR, EPIPHANY_INSN_LDRBX16_S, EPIPHANY_INSN_LDRBP16_S
|
||||||
|
, EPIPHANY_INSN_LDRBX_L, EPIPHANY_INSN_LDRBP_L, EPIPHANY_INSN_LDRBD16_S, EPIPHANY_INSN_LDRBD_L
|
||||||
|
, EPIPHANY_INSN_LDRBDPM_L, EPIPHANY_INSN_LDRHX16_S, EPIPHANY_INSN_LDRHP16_S, EPIPHANY_INSN_LDRHX_L
|
||||||
|
, EPIPHANY_INSN_LDRHP_L, EPIPHANY_INSN_LDRHD16_S, EPIPHANY_INSN_LDRHD_L, EPIPHANY_INSN_LDRHDPM_L
|
||||||
|
, EPIPHANY_INSN_LDRX16_S, EPIPHANY_INSN_LDRP16_S, EPIPHANY_INSN_LDRX_L, EPIPHANY_INSN_LDRP_L
|
||||||
|
, EPIPHANY_INSN_LDRD16_S, EPIPHANY_INSN_LDRD_L, EPIPHANY_INSN_LDRDPM_L, EPIPHANY_INSN_LDRDX16_S
|
||||||
|
, EPIPHANY_INSN_LDRDP16_S, EPIPHANY_INSN_LDRDX_L, EPIPHANY_INSN_LDRDP_L, EPIPHANY_INSN_LDRDD16_S
|
||||||
|
, EPIPHANY_INSN_LDRDD_L, EPIPHANY_INSN_LDRDDPM_L, EPIPHANY_INSN_TESTSETBT, EPIPHANY_INSN_TESTSETHT
|
||||||
|
, EPIPHANY_INSN_TESTSETT, EPIPHANY_INSN_STRBX16, EPIPHANY_INSN_STRBX, EPIPHANY_INSN_STRBP16
|
||||||
|
, EPIPHANY_INSN_STRBP, EPIPHANY_INSN_STRBD16, EPIPHANY_INSN_STRBD, EPIPHANY_INSN_STRBDPM
|
||||||
|
, EPIPHANY_INSN_STRHX16, EPIPHANY_INSN_STRHX, EPIPHANY_INSN_STRHP16, EPIPHANY_INSN_STRHP
|
||||||
|
, EPIPHANY_INSN_STRHD16, EPIPHANY_INSN_STRHD, EPIPHANY_INSN_STRHDPM, EPIPHANY_INSN_STRX16
|
||||||
|
, EPIPHANY_INSN_STRX, EPIPHANY_INSN_STRP16, EPIPHANY_INSN_STRP, EPIPHANY_INSN_STRD16
|
||||||
|
, EPIPHANY_INSN_STRD, EPIPHANY_INSN_STRDPM, EPIPHANY_INSN_STRDX16, EPIPHANY_INSN_STRDX
|
||||||
|
, EPIPHANY_INSN_STRDP16, EPIPHANY_INSN_STRDP, EPIPHANY_INSN_STRDD16, EPIPHANY_INSN_STRDD
|
||||||
|
, EPIPHANY_INSN_STRDDPM, EPIPHANY_INSN_CMOV16EQ, EPIPHANY_INSN_CMOVEQ, EPIPHANY_INSN_CMOV16NE
|
||||||
|
, EPIPHANY_INSN_CMOVNE, EPIPHANY_INSN_CMOV16GTU, EPIPHANY_INSN_CMOVGTU, EPIPHANY_INSN_CMOV16GTEU
|
||||||
|
, EPIPHANY_INSN_CMOVGTEU, EPIPHANY_INSN_CMOV16LTEU, EPIPHANY_INSN_CMOVLTEU, EPIPHANY_INSN_CMOV16LTU
|
||||||
|
, EPIPHANY_INSN_CMOVLTU, EPIPHANY_INSN_CMOV16GT, EPIPHANY_INSN_CMOVGT, EPIPHANY_INSN_CMOV16GTE
|
||||||
|
, EPIPHANY_INSN_CMOVGTE, EPIPHANY_INSN_CMOV16LT, EPIPHANY_INSN_CMOVLT, EPIPHANY_INSN_CMOV16LTE
|
||||||
|
, EPIPHANY_INSN_CMOVLTE, EPIPHANY_INSN_CMOV16B, EPIPHANY_INSN_CMOVB, EPIPHANY_INSN_CMOV16BEQ
|
||||||
|
, EPIPHANY_INSN_CMOVBEQ, EPIPHANY_INSN_CMOV16BNE, EPIPHANY_INSN_CMOVBNE, EPIPHANY_INSN_CMOV16BLT
|
||||||
|
, EPIPHANY_INSN_CMOVBLT, EPIPHANY_INSN_CMOV16BLTE, EPIPHANY_INSN_CMOVBLTE, EPIPHANY_INSN_MOVTS16
|
||||||
|
, EPIPHANY_INSN_MOVTS6, EPIPHANY_INSN_MOVTSDMA, EPIPHANY_INSN_MOVTSMEM, EPIPHANY_INSN_MOVTSMESH
|
||||||
|
, EPIPHANY_INSN_MOVFS16, EPIPHANY_INSN_MOVFS6, EPIPHANY_INSN_MOVFSDMA, EPIPHANY_INSN_MOVFSMEM
|
||||||
|
, EPIPHANY_INSN_MOVFSMESH, EPIPHANY_INSN_NOP, EPIPHANY_INSN_SNOP, EPIPHANY_INSN_UNIMPL
|
||||||
|
, EPIPHANY_INSN_IDLE, EPIPHANY_INSN_BKPT, EPIPHANY_INSN_MBKPT, EPIPHANY_INSN_RTI
|
||||||
|
, EPIPHANY_INSN_WAND, EPIPHANY_INSN_SYNC, EPIPHANY_INSN_GIEN, EPIPHANY_INSN_GIDIS
|
||||||
|
, EPIPHANY_INSN_SWI_NUM, EPIPHANY_INSN_SWI, EPIPHANY_INSN_TRAP16, EPIPHANY_INSN_ADD16
|
||||||
|
, EPIPHANY_INSN_ADD, EPIPHANY_INSN_SUB16, EPIPHANY_INSN_SUB, EPIPHANY_INSN_AND16
|
||||||
|
, EPIPHANY_INSN_AND, EPIPHANY_INSN_ORR16, EPIPHANY_INSN_ORR, EPIPHANY_INSN_EOR16
|
||||||
|
, EPIPHANY_INSN_EOR, EPIPHANY_INSN_ADDI16, EPIPHANY_INSN_ADDI, EPIPHANY_INSN_SUBI16
|
||||||
|
, EPIPHANY_INSN_SUBI, EPIPHANY_INSN_ASR16, EPIPHANY_INSN_ASR, EPIPHANY_INSN_LSR16
|
||||||
|
, EPIPHANY_INSN_LSR, EPIPHANY_INSN_LSL16, EPIPHANY_INSN_LSL, EPIPHANY_INSN_LSRI16
|
||||||
|
, EPIPHANY_INSN_LSRI32, EPIPHANY_INSN_LSLI16, EPIPHANY_INSN_LSLI32, EPIPHANY_INSN_ASRI16
|
||||||
|
, EPIPHANY_INSN_ASRI32, EPIPHANY_INSN_BITR16, EPIPHANY_INSN_BITR, EPIPHANY_INSN_FEXT
|
||||||
|
, EPIPHANY_INSN_FDEP, EPIPHANY_INSN_LFSR, EPIPHANY_INSN_MOV8, EPIPHANY_INSN_MOV16
|
||||||
|
, EPIPHANY_INSN_MOVT, EPIPHANY_INSN_F_ADDF16, EPIPHANY_INSN_F_ADDF32, EPIPHANY_INSN_F_SUBF16
|
||||||
|
, EPIPHANY_INSN_F_SUBF32, EPIPHANY_INSN_F_MULF16, EPIPHANY_INSN_F_MULF32, EPIPHANY_INSN_F_MADDF16
|
||||||
|
, EPIPHANY_INSN_F_MADDF32, EPIPHANY_INSN_F_MSUBF16, EPIPHANY_INSN_F_MSUBF32, EPIPHANY_INSN_F_ABSF16
|
||||||
|
, EPIPHANY_INSN_F_ABSF32, EPIPHANY_INSN_F_LOATF16, EPIPHANY_INSN_F_LOATF32, EPIPHANY_INSN_F_IXF16
|
||||||
|
, EPIPHANY_INSN_F_IXF32, EPIPHANY_INSN_F_RECIPF32, EPIPHANY_INSN_F_SQRTF32
|
||||||
|
} CGEN_INSN_TYPE;
|
||||||
|
|
||||||
|
/* Index of `invalid' insn place holder. */
|
||||||
|
#define CGEN_INSN_INVALID EPIPHANY_INSN_INVALID
|
||||||
|
|
||||||
|
/* Total number of insns in table. */
|
||||||
|
#define MAX_INSNS ((int) EPIPHANY_INSN_F_SQRTF32 + 1)
|
||||||
|
|
||||||
|
/* This struct records data prior to insertion or after extraction. */
|
||||||
|
struct cgen_fields
|
||||||
|
{
|
||||||
|
int length;
|
||||||
|
long f_nil;
|
||||||
|
long f_anyof;
|
||||||
|
long f_opc;
|
||||||
|
long f_opc_4_1;
|
||||||
|
long f_opc_6_3;
|
||||||
|
long f_opc_8_5;
|
||||||
|
long f_opc_19_4;
|
||||||
|
long f_condcode;
|
||||||
|
long f_secondary_ccs;
|
||||||
|
long f_shift;
|
||||||
|
long f_wordsize;
|
||||||
|
long f_store;
|
||||||
|
long f_opc_8_1;
|
||||||
|
long f_opc_31_32;
|
||||||
|
long f_simm8;
|
||||||
|
long f_simm24;
|
||||||
|
long f_sdisp3;
|
||||||
|
long f_disp3;
|
||||||
|
long f_disp8;
|
||||||
|
long f_imm8;
|
||||||
|
long f_imm_27_8;
|
||||||
|
long f_addsubx;
|
||||||
|
long f_subd;
|
||||||
|
long f_pm;
|
||||||
|
long f_rm;
|
||||||
|
long f_rn;
|
||||||
|
long f_rd;
|
||||||
|
long f_rm_x;
|
||||||
|
long f_rn_x;
|
||||||
|
long f_rd_x;
|
||||||
|
long f_dc_9_1;
|
||||||
|
long f_sn;
|
||||||
|
long f_sd;
|
||||||
|
long f_sn_x;
|
||||||
|
long f_sd_x;
|
||||||
|
long f_dc_7_4;
|
||||||
|
long f_trap_swi_9_1;
|
||||||
|
long f_gien_gidis_9_1;
|
||||||
|
long f_dc_15_3;
|
||||||
|
long f_dc_15_7;
|
||||||
|
long f_dc_15_6;
|
||||||
|
long f_trap_num;
|
||||||
|
long f_dc_20_1;
|
||||||
|
long f_dc_21_1;
|
||||||
|
long f_dc_21_2;
|
||||||
|
long f_dc_22_3;
|
||||||
|
long f_dc_22_2;
|
||||||
|
long f_dc_22_1;
|
||||||
|
long f_dc_25_6;
|
||||||
|
long f_dc_25_4;
|
||||||
|
long f_dc_25_2;
|
||||||
|
long f_dc_25_1;
|
||||||
|
long f_dc_28_1;
|
||||||
|
long f_dc_31_3;
|
||||||
|
long f_disp11;
|
||||||
|
long f_sdisp11;
|
||||||
|
long f_imm16;
|
||||||
|
long f_rd6;
|
||||||
|
long f_rn6;
|
||||||
|
long f_rm6;
|
||||||
|
long f_sd6;
|
||||||
|
long f_sn6;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define CGEN_INIT_PARSE(od) \
|
||||||
|
{\
|
||||||
|
}
|
||||||
|
#define CGEN_INIT_INSERT(od) \
|
||||||
|
{\
|
||||||
|
}
|
||||||
|
#define CGEN_INIT_EXTRACT(od) \
|
||||||
|
{\
|
||||||
|
}
|
||||||
|
#define CGEN_INIT_PRINT(od) \
|
||||||
|
{\
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* EPIPHANY_OPC_H */
|
||||||
@ -24,6 +24,13 @@ dis-buf.c
|
|||||||
dis-init.c
|
dis-init.c
|
||||||
disassemble.c
|
disassemble.c
|
||||||
dlx-dis.c
|
dlx-dis.c
|
||||||
|
epiphany-asm.c
|
||||||
|
epiphany-desc.c
|
||||||
|
epiphany-desc.h
|
||||||
|
epiphany-dis.c
|
||||||
|
epiphany-ibld.c
|
||||||
|
epiphany-opc.c
|
||||||
|
epiphany-opc.h
|
||||||
fr30-asm.c
|
fr30-asm.c
|
||||||
fr30-desc.c
|
fr30-desc.c
|
||||||
fr30-desc.h
|
fr30-desc.h
|
||||||
@ -121,6 +128,7 @@ mep-opc.c
|
|||||||
mep-opc.h
|
mep-opc.h
|
||||||
microblaze-dis.c
|
microblaze-dis.c
|
||||||
microblaze-opc.h
|
microblaze-opc.h
|
||||||
|
micromips-opc.c
|
||||||
mips-dis.c
|
mips-dis.c
|
||||||
mips-opc.c
|
mips-opc.c
|
||||||
mips16-opc.c
|
mips16-opc.c
|
||||||
|
|||||||
@ -8,7 +8,7 @@ msgid ""
|
|||||||
msgstr ""
|
msgstr ""
|
||||||
"Project-Id-Version: PACKAGE VERSION\n"
|
"Project-Id-Version: PACKAGE VERSION\n"
|
||||||
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
|
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
|
||||||
"POT-Creation-Date: 2011-06-02 14:30+0100\n"
|
"POT-Creation-Date: 2011-10-25 11:34+0100\n"
|
||||||
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
|
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
|
||||||
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
|
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
|
||||||
"Language-Team: LANGUAGE <LL@li.org>\n"
|
"Language-Team: LANGUAGE <LL@li.org>\n"
|
||||||
@ -111,23 +111,23 @@ msgstr ""
|
|||||||
msgid "must specify .jd or no nullify suffix"
|
msgid "must specify .jd or no nullify suffix"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: arm-dis.c:1994
|
#: arm-dis.c:2000
|
||||||
msgid "<illegal precision>"
|
msgid "<illegal precision>"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#. XXX - should break 'option' at following delimiter.
|
#. XXX - should break 'option' at following delimiter.
|
||||||
#: arm-dis.c:4376
|
#: arm-dis.c:4395
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Unrecognised register name set: %s\n"
|
msgid "Unrecognised register name set: %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#. XXX - should break 'option' at following delimiter.
|
#. XXX - should break 'option' at following delimiter.
|
||||||
#: arm-dis.c:4384
|
#: arm-dis.c:4403
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Unrecognised disassembler option: %s\n"
|
msgid "Unrecognised disassembler option: %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: arm-dis.c:4976
|
#: arm-dis.c:4995
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -135,25 +135,25 @@ msgid ""
|
|||||||
"the -M switch:\n"
|
"the -M switch:\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: avr-dis.c:115 avr-dis.c:135
|
#: avr-dis.c:115 avr-dis.c:136
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "undefined"
|
msgid "undefined"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: avr-dis.c:197
|
#: avr-dis.c:198
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Internal disassembler error"
|
msgid "Internal disassembler error"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: avr-dis.c:250
|
#: avr-dis.c:251
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "unknown constraint `%c'"
|
msgid "unknown constraint `%c'"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201
|
#: cgen-asm.c:336 epiphany-ibld.c:201 fr30-ibld.c:201 frv-ibld.c:201
|
||||||
#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201
|
#: ip2k-ibld.c:201 iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201
|
||||||
#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201
|
#: m32r-ibld.c:201 mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201
|
||||||
#: xstormy16-ibld.c:201
|
#: xc16x-ibld.c:201 xstormy16-ibld.c:201
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "operand out of range (%ld not between %ld and %ld)"
|
msgid "operand out of range (%ld not between %ld and %ld)"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
@ -179,6 +179,198 @@ msgstr ""
|
|||||||
msgid "Address 0x%s is out of bounds.\n"
|
msgid "Address 0x%s is out of bounds.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:68
|
||||||
|
msgid "register unavailable for short instructions"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:115
|
||||||
|
msgid "register name used as immediate value"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#. Don't treat "mov ip,ip" as a move-immediate.
|
||||||
|
#: epiphany-asm.c:178 epiphany-asm.c:234
|
||||||
|
msgid "register source in immediate move"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:187
|
||||||
|
msgid "byte relocation unsupported"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#. -- assembler routines inserted here.
|
||||||
|
#. -- asm.c
|
||||||
|
#: epiphany-asm.c:193 frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95
|
||||||
|
#: lm32-asm.c:127 lm32-asm.c:157 lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247
|
||||||
|
#: m32c-asm.c:140 m32c-asm.c:235 m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355
|
||||||
|
#: m32r-asm.c:53 mep-asm.c:241 mep-asm.c:259 mep-asm.c:274 mep-asm.c:289
|
||||||
|
#: mep-asm.c:301 openrisc-asm.c:54
|
||||||
|
msgid "missing `)'"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:270
|
||||||
|
msgid "ABORT: unknown operand"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:296
|
||||||
|
msgid "Not a pc-relative address."
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:455 fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511
|
||||||
|
#: iq2000-asm.c:459 lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328
|
||||||
|
#: mep-asm.c:1286 mt-asm.c:595 openrisc-asm.c:241 xc16x-asm.c:376
|
||||||
|
#: xstormy16-asm.c:276
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while parsing.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:506 fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562
|
||||||
|
#: iq2000-asm.c:510 lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379
|
||||||
|
#: mep-asm.c:1337 mt-asm.c:646 openrisc-asm.c:292 xc16x-asm.c:427
|
||||||
|
#: xstormy16-asm.c:327
|
||||||
|
msgid "missing mnemonic in syntax string"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#. We couldn't parse it.
|
||||||
|
#: epiphany-asm.c:641 epiphany-asm.c:645 epiphany-asm.c:734 epiphany-asm.c:841
|
||||||
|
#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449
|
||||||
|
#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701
|
||||||
|
#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649
|
||||||
|
#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539
|
||||||
|
#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774
|
||||||
|
#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518
|
||||||
|
#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565
|
||||||
|
#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981
|
||||||
|
#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627
|
||||||
|
#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762
|
||||||
|
#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555
|
||||||
|
#: xstormy16-asm.c:662
|
||||||
|
msgid "unrecognized instruction"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:688 fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744
|
||||||
|
#: iq2000-asm.c:692 lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561
|
||||||
|
#: mep-asm.c:1519 mt-asm.c:828 openrisc-asm.c:474 xc16x-asm.c:609
|
||||||
|
#: xstormy16-asm.c:509
|
||||||
|
#, c-format
|
||||||
|
msgid "syntax error (expected char `%c', found `%c')"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:698 fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754
|
||||||
|
#: iq2000-asm.c:702 lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571
|
||||||
|
#: mep-asm.c:1529 mt-asm.c:838 openrisc-asm.c:484 xc16x-asm.c:619
|
||||||
|
#: xstormy16-asm.c:519
|
||||||
|
#, c-format
|
||||||
|
msgid "syntax error (expected char `%c', found end of instruction)"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:728 fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784
|
||||||
|
#: iq2000-asm.c:732 lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601
|
||||||
|
#: mep-asm.c:1559 mt-asm.c:868 openrisc-asm.c:514 xc16x-asm.c:649
|
||||||
|
#: xstormy16-asm.c:549
|
||||||
|
msgid "junk at end of line"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:840 fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896
|
||||||
|
#: iq2000-asm.c:844 lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713
|
||||||
|
#: mep-asm.c:1671 mt-asm.c:980 openrisc-asm.c:626 xc16x-asm.c:761
|
||||||
|
#: xstormy16-asm.c:661
|
||||||
|
msgid "unrecognized form of instruction"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:854 fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910
|
||||||
|
#: iq2000-asm.c:858 lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727
|
||||||
|
#: mep-asm.c:1685 mt-asm.c:994 openrisc-asm.c:640 xc16x-asm.c:775
|
||||||
|
#: xstormy16-asm.c:675
|
||||||
|
#, c-format
|
||||||
|
msgid "bad instruction `%.50s...'"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-asm.c:857 fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913
|
||||||
|
#: iq2000-asm.c:861 lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730
|
||||||
|
#: mep-asm.c:1688 mt-asm.c:997 openrisc-asm.c:643 xc16x-asm.c:778
|
||||||
|
#: xstormy16-asm.c:678
|
||||||
|
#, c-format
|
||||||
|
msgid "bad instruction `%.50s'"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#. Default text to print if an instruction isn't recognized.
|
||||||
|
#: epiphany-dis.c:41 fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41
|
||||||
|
#: lm32-dis.c:41 m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277
|
||||||
|
#: mt-dis.c:41 openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
|
||||||
|
msgid "*unknown*"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-dis.c:277 fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288
|
||||||
|
#: iq2000-dis.c:189 lm32-dis.c:147 m32c-dis.c:891 m32r-dis.c:279
|
||||||
|
#: mep-dis.c:1187 mt-dis.c:290 openrisc-dis.c:135 xc16x-dis.c:420
|
||||||
|
#: xstormy16-dis.c:168
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while printing insn.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:164 fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164
|
||||||
|
#: iq2000-ibld.c:164 lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164
|
||||||
|
#: mep-ibld.c:164 mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164
|
||||||
|
#: xstormy16-ibld.c:164
|
||||||
|
#, c-format
|
||||||
|
msgid "operand out of range (%ld not between %ld and %lu)"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:185 fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185
|
||||||
|
#: iq2000-ibld.c:185 lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185
|
||||||
|
#: mep-ibld.c:185 mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185
|
||||||
|
#: xstormy16-ibld.c:185
|
||||||
|
#, c-format
|
||||||
|
msgid "operand out of range (0x%lx not between 0 and 0x%lx)"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:872 fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604
|
||||||
|
#: iq2000-ibld.c:710 lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662
|
||||||
|
#: mep-ibld.c:1205 mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749
|
||||||
|
#: xstormy16-ibld.c:675
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while building insn.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:1166 fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679
|
||||||
|
#: iq2000-ibld.c:885 lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799
|
||||||
|
#: mep-ibld.c:1804 mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969
|
||||||
|
#: xstormy16-ibld.c:821
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while decoding insn.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:1309 fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753
|
||||||
|
#: iq2000-ibld.c:1016 lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912
|
||||||
|
#: mep-ibld.c:2274 mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190
|
||||||
|
#: xstormy16-ibld.c:931
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while getting int operand.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:1434 fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809
|
||||||
|
#: iq2000-ibld.c:1129 lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007
|
||||||
|
#: mep-ibld.c:2726 mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393
|
||||||
|
#: xstormy16-ibld.c:1023
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while getting vma operand.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:1566 fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868
|
||||||
|
#: iq2000-ibld.c:1249 lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108
|
||||||
|
#: mep-ibld.c:3139 mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597
|
||||||
|
#: xstormy16-ibld.c:1122
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while setting int operand.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: epiphany-ibld.c:1688 fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917
|
||||||
|
#: iq2000-ibld.c:1359 lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199
|
||||||
|
#: mep-ibld.c:3542 mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791
|
||||||
|
#: xstormy16-ibld.c:1211
|
||||||
|
#, c-format
|
||||||
|
msgid "Unrecognized field %d while setting vma operand.\n"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879
|
#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879
|
||||||
msgid "Register number is not valid"
|
msgid "Register number is not valid"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
@ -195,145 +387,6 @@ msgstr ""
|
|||||||
msgid "Register list is not valid"
|
msgid "Register list is not valid"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459
|
|
||||||
#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595
|
|
||||||
#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while parsing.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510
|
|
||||||
#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646
|
|
||||||
#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327
|
|
||||||
msgid "missing mnemonic in syntax string"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#. We couldn't parse it.
|
|
||||||
#: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449
|
|
||||||
#: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701
|
|
||||||
#: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649
|
|
||||||
#: iq2000-asm.c:738 iq2000-asm.c:845 lm32-asm.c:535 lm32-asm.c:539
|
|
||||||
#: lm32-asm.c:628 lm32-asm.c:735 m32c-asm.c:1770 m32c-asm.c:1774
|
|
||||||
#: m32c-asm.c:1863 m32c-asm.c:1970 m32r-asm.c:514 m32r-asm.c:518
|
|
||||||
#: m32r-asm.c:607 m32r-asm.c:714 mep-asm.c:1472 mep-asm.c:1476 mep-asm.c:1565
|
|
||||||
#: mep-asm.c:1672 mt-asm.c:781 mt-asm.c:785 mt-asm.c:874 mt-asm.c:981
|
|
||||||
#: openrisc-asm.c:427 openrisc-asm.c:431 openrisc-asm.c:520 openrisc-asm.c:627
|
|
||||||
#: xc16x-asm.c:562 xc16x-asm.c:566 xc16x-asm.c:655 xc16x-asm.c:762
|
|
||||||
#: xstormy16-asm.c:462 xstormy16-asm.c:466 xstormy16-asm.c:555
|
|
||||||
#: xstormy16-asm.c:662
|
|
||||||
msgid "unrecognized instruction"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692
|
|
||||||
#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828
|
|
||||||
#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509
|
|
||||||
#, c-format
|
|
||||||
msgid "syntax error (expected char `%c', found `%c')"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702
|
|
||||||
#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838
|
|
||||||
#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519
|
|
||||||
#, c-format
|
|
||||||
msgid "syntax error (expected char `%c', found end of instruction)"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732
|
|
||||||
#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868
|
|
||||||
#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549
|
|
||||||
msgid "junk at end of line"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844
|
|
||||||
#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980
|
|
||||||
#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661
|
|
||||||
msgid "unrecognized form of instruction"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858
|
|
||||||
#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994
|
|
||||||
#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675
|
|
||||||
#, c-format
|
|
||||||
msgid "bad instruction `%.50s...'"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861
|
|
||||||
#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997
|
|
||||||
#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678
|
|
||||||
#, c-format
|
|
||||||
msgid "bad instruction `%.50s'"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#. Default text to print if an instruction isn't recognized.
|
|
||||||
#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41
|
|
||||||
#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41
|
|
||||||
#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41
|
|
||||||
msgid "*unknown*"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147
|
|
||||||
#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290
|
|
||||||
#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while printing insn.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164
|
|
||||||
#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164
|
|
||||||
#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164
|
|
||||||
#, c-format
|
|
||||||
msgid "operand out of range (%ld not between %ld and %lu)"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185
|
|
||||||
#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185
|
|
||||||
#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185
|
|
||||||
#, c-format
|
|
||||||
msgid "operand out of range (0x%lx not between 0 and 0x%lx)"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710
|
|
||||||
#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205
|
|
||||||
#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while building insn.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885
|
|
||||||
#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804
|
|
||||||
#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while decoding insn.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016
|
|
||||||
#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274
|
|
||||||
#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while getting int operand.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129
|
|
||||||
#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726
|
|
||||||
#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while getting vma operand.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249
|
|
||||||
#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139
|
|
||||||
#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while setting int operand.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359
|
|
||||||
#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542
|
|
||||||
#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211
|
|
||||||
#, c-format
|
|
||||||
msgid "Unrecognized field %d while setting vma operand.\n"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: frv-asm.c:608
|
#: frv-asm.c:608
|
||||||
msgid "missing `]'"
|
msgid "missing `]'"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
@ -350,15 +403,6 @@ msgstr ""
|
|||||||
msgid "register number must be even"
|
msgid "register number must be even"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#. -- assembler routines inserted here.
|
|
||||||
#. -- asm.c
|
|
||||||
#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157
|
|
||||||
#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235
|
|
||||||
#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241
|
|
||||||
#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54
|
|
||||||
msgid "missing `)'"
|
|
||||||
msgstr ""
|
|
||||||
|
|
||||||
#: h8300-dis.c:314
|
#: h8300-dis.c:314
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Hmmmm 0x%x"
|
msgid "Hmmmm 0x%x"
|
||||||
@ -380,11 +424,11 @@ msgstr ""
|
|||||||
msgid "%02x\t\t*unknown*"
|
msgid "%02x\t\t*unknown*"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:10774
|
#: i386-dis.c:10504
|
||||||
msgid "<internal disassembler error>"
|
msgid "<internal disassembler error>"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11071
|
#: i386-dis.c:10801
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -393,126 +437,126 @@ msgid ""
|
|||||||
"with the -M switch (multiple options should be separated by commas):\n"
|
"with the -M switch (multiple options should be separated by commas):\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11075
|
#: i386-dis.c:10805
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " x86-64 Disassemble in 64bit mode\n"
|
msgid " x86-64 Disassemble in 64bit mode\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11076
|
#: i386-dis.c:10806
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " i386 Disassemble in 32bit mode\n"
|
msgid " i386 Disassemble in 32bit mode\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11077
|
#: i386-dis.c:10807
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " i8086 Disassemble in 16bit mode\n"
|
msgid " i8086 Disassemble in 16bit mode\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11078
|
#: i386-dis.c:10808
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " att Display instruction in AT&T syntax\n"
|
msgid " att Display instruction in AT&T syntax\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11079
|
#: i386-dis.c:10809
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " intel Display instruction in Intel syntax\n"
|
msgid " intel Display instruction in Intel syntax\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11080
|
#: i386-dis.c:10810
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
" att-mnemonic\n"
|
" att-mnemonic\n"
|
||||||
" Display instruction in AT&T mnemonic\n"
|
" Display instruction in AT&T mnemonic\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11082
|
#: i386-dis.c:10812
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
" intel-mnemonic\n"
|
" intel-mnemonic\n"
|
||||||
" Display instruction in Intel mnemonic\n"
|
" Display instruction in Intel mnemonic\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11084
|
#: i386-dis.c:10814
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " addr64 Assume 64bit address size\n"
|
msgid " addr64 Assume 64bit address size\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11085
|
#: i386-dis.c:10815
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " addr32 Assume 32bit address size\n"
|
msgid " addr32 Assume 32bit address size\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11086
|
#: i386-dis.c:10816
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " addr16 Assume 16bit address size\n"
|
msgid " addr16 Assume 16bit address size\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11087
|
#: i386-dis.c:10817
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " data32 Assume 32bit data size\n"
|
msgid " data32 Assume 32bit data size\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11088
|
#: i386-dis.c:10818
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " data16 Assume 16bit data size\n"
|
msgid " data16 Assume 16bit data size\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-dis.c:11089
|
#: i386-dis.c:10819
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid " suffix Always display instruction suffix in AT&T syntax\n"
|
msgid " suffix Always display instruction suffix in AT&T syntax\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:467 ia64-gen.c:307
|
#: i386-gen.c:483 ia64-gen.c:307
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "%s: Error: "
|
msgid "%s: Error: "
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:599
|
#: i386-gen.c:615
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "%s: %d: Unknown bitfield: %s\n"
|
msgid "%s: %d: Unknown bitfield: %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:601
|
#: i386-gen.c:617
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Unknown bitfield: %s\n"
|
msgid "Unknown bitfield: %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:657
|
#: i386-gen.c:673
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "%s: %d: Missing `)' in bitfield: %s\n"
|
msgid "%s: %d: Missing `)' in bitfield: %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:922
|
#: i386-gen.c:938
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "can't find i386-opc.tbl for reading, errno = %s\n"
|
msgid "can't find i386-opc.tbl for reading, errno = %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:1053
|
#: i386-gen.c:1069
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "can't find i386-reg.tbl for reading, errno = %s\n"
|
msgid "can't find i386-reg.tbl for reading, errno = %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:1130
|
#: i386-gen.c:1146
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "can't create i386-init.h, errno = %s\n"
|
msgid "can't create i386-init.h, errno = %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:1219 ia64-gen.c:2820
|
#: i386-gen.c:1235 ia64-gen.c:2820
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "unable to change directory to \"%s\", errno = %s\n"
|
msgid "unable to change directory to \"%s\", errno = %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:1226
|
#: i386-gen.c:1242
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "%d unused bits in i386_cpu_flags.\n"
|
msgid "%d unused bits in i386_cpu_flags.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:1233
|
#: i386-gen.c:1249
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "%d unused bits in i386_operand_type.\n"
|
msgid "%d unused bits in i386_operand_type.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: i386-gen.c:1247
|
#: i386-gen.c:1263
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "can't create i386-tbl.h, errno = %s\n"
|
msgid "can't create i386-tbl.h, errno = %s\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
@ -830,26 +874,41 @@ msgstr ""
|
|||||||
msgid "Value is not aligned enough"
|
msgid "Value is not aligned enough"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:845
|
#: mips-dis.c:947
|
||||||
msgid "# internal error, incomplete extension sequence (+)"
|
msgid "# internal error, incomplete extension sequence (+)"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:1011
|
#: mips-dis.c:1113
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "# internal error, undefined extension sequence (+%c)"
|
msgid "# internal error, undefined extension sequence (+%c)"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:1371
|
#: mips-dis.c:1485
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "# internal error, undefined modifier (%c)"
|
msgid "# internal error, undefined modifier (%c)"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:1975
|
#: mips-dis.c:2089
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "# internal disassembler error, unrecognised modifier (%c)"
|
msgid "# internal disassembler error, unrecognised modifier (%c)"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2213
|
#: mips-dis.c:2664
|
||||||
|
#, c-format
|
||||||
|
msgid "# internal disassembler error, unrecognized modifier (+%c)"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: mips-dis.c:2894
|
||||||
|
#, c-format
|
||||||
|
msgid "# internal disassembler error, unrecognized modifier (m%c)"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: mips-dis.c:2904
|
||||||
|
#, c-format
|
||||||
|
msgid "# internal disassembler error, unrecognized modifier (%c)"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: mips-dis.c:3052
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -857,7 +916,7 @@ msgid ""
|
|||||||
"with the -M switch (multiple options should be separated by commas):\n"
|
"with the -M switch (multiple options should be separated by commas):\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2217
|
#: mips-dis.c:3056
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -865,7 +924,7 @@ msgid ""
|
|||||||
" Default: based on binary being disassembled.\n"
|
" Default: based on binary being disassembled.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2221
|
#: mips-dis.c:3060
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -873,7 +932,7 @@ msgid ""
|
|||||||
" Default: numeric.\n"
|
" Default: numeric.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2225
|
#: mips-dis.c:3064
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -882,7 +941,7 @@ msgid ""
|
|||||||
" Default: based on binary being disassembled.\n"
|
" Default: based on binary being disassembled.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2230
|
#: mips-dis.c:3069
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -891,7 +950,7 @@ msgid ""
|
|||||||
" Default: based on binary being disassembled.\n"
|
" Default: based on binary being disassembled.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2235
|
#: mips-dis.c:3074
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -899,7 +958,7 @@ msgid ""
|
|||||||
" specified ABI.\n"
|
" specified ABI.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2239
|
#: mips-dis.c:3078
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -907,7 +966,7 @@ msgid ""
|
|||||||
" specified architecture.\n"
|
" specified architecture.\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2243
|
#: mips-dis.c:3082
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -915,12 +974,12 @@ msgid ""
|
|||||||
" "
|
" "
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2248 mips-dis.c:2256 mips-dis.c:2258
|
#: mips-dis.c:3087 mips-dis.c:3095 mips-dis.c:3097
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "\n"
|
msgid "\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: mips-dis.c:2250
|
#: mips-dis.c:3089
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid ""
|
msgid ""
|
||||||
"\n"
|
"\n"
|
||||||
@ -995,43 +1054,51 @@ msgid ""
|
|||||||
"the -M switch:\n"
|
"the -M switch:\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:879 ppc-opc.c:907
|
#: ppc-opc.c:906 ppc-opc.c:936
|
||||||
msgid "invalid conditional option"
|
msgid "invalid conditional option"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:909
|
#: ppc-opc.c:908 ppc-opc.c:938
|
||||||
|
msgid "invalid counter access"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: ppc-opc.c:940
|
||||||
msgid "attempt to set y bit when using + or - modifier"
|
msgid "attempt to set y bit when using + or - modifier"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:941
|
#: ppc-opc.c:972
|
||||||
msgid "invalid mask field"
|
msgid "invalid mask field"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:967
|
#: ppc-opc.c:998
|
||||||
msgid "ignoring invalid mfcr mask"
|
msgid "ignoring invalid mfcr mask"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:1017 ppc-opc.c:1052
|
#: ppc-opc.c:1048 ppc-opc.c:1083
|
||||||
msgid "illegal bitmask"
|
msgid "illegal bitmask"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:1172
|
#: ppc-opc.c:1170
|
||||||
|
msgid "address register in load range"
|
||||||
|
msgstr ""
|
||||||
|
|
||||||
|
#: ppc-opc.c:1223
|
||||||
msgid "index register in load range"
|
msgid "index register in load range"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:1188
|
#: ppc-opc.c:1239 ppc-opc.c:1295
|
||||||
msgid "source and target register operands must be different"
|
msgid "source and target register operands must be different"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:1203
|
#: ppc-opc.c:1254
|
||||||
msgid "invalid register operand when updating"
|
msgid "invalid register operand when updating"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:1282
|
#: ppc-opc.c:1349
|
||||||
msgid "invalid sprg number"
|
msgid "invalid sprg number"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: ppc-opc.c:1452
|
#: ppc-opc.c:1519
|
||||||
msgid "invalid constant"
|
msgid "invalid constant"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
@ -1058,23 +1125,23 @@ msgstr ""
|
|||||||
msgid "<illegal instruction>"
|
msgid "<illegal instruction>"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: sparc-dis.c:283
|
#: sparc-dis.c:285
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
|
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: sparc-dis.c:294
|
#: sparc-dis.c:296
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
|
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#: sparc-dis.c:344
|
#: sparc-dis.c:346
|
||||||
#, c-format
|
#, c-format
|
||||||
msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
|
msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
#. Mark as non-valid instruction.
|
#. Mark as non-valid instruction.
|
||||||
#: sparc-dis.c:1015
|
#: sparc-dis.c:1028
|
||||||
msgid "unknown"
|
msgid "unknown"
|
||||||
msgstr ""
|
msgstr ""
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user