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arch64: Add optional operand register pair support tests

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Add tests to cover the full range of behaviors observed around
optional register operands for the `tlbip' and `sysp' instructions,
namely:

  * Not all `tlbip' operations take GPR operands.  When this is the
  case, we should check that neither optional operand was supplied.
  * When a `tlbip' operation is labeled with the `F_HASXT' flag, xzr
  is not a valid optional operand.  In such case, at least the fist
  optional register needs to be specified with a non-xzr value.
  * The first operand for both insns should be either xzr or an
  even-numbered register (n % 2 == 0).  In the former scenario, the
  second operand should default to xzr too, while in the latter, it
  should default to n + 1.
This commit is contained in:
Victor Do Nascimento 2023-12-13 13:02:30 +00:00
parent 9af8f67118
commit e3a478523e
5 changed files with 57 additions and 0 deletions
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4
gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d Normal file
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#name: Illegal optional operand pair use
#as: -mno-verbose-error
#source: illegal-sysp-tlbip-optional.s
#error_output: illegal-sysp-tlbip-optional.l

4
gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l Normal file
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[^:]*: Assembler messages:
[^:]*:5: Error: missing register at operand 2 -- `tlbip vale3nxs'
[^:]*:9: Error: extraneous register at operand 2 -- `tlbip paall,x0'
[^:]*:10: Error: extraneous register at operand 2 -- `tlbip paall,x0,x1'

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gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s Normal file
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.arch armv9.4-a+d128
/* TLBIP operands marked with the F_HASXT don not allow xzr to be used
as GPR arguments and so require at least one register to be specified. */
tlbip vale3nxs
/* Conversely, those without the flag do not allow us to specify registers,
so the only accepted alternative is the complete omission of optional ops. */
tlbip paall, x0
tlbip paall, x0, x1

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gas/testsuite/gas/aarch64/sysp-tlbip-optional.d Normal file
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#objdump: -dr
.*
Disassembly of section \.text:
0+ <\.text>:
[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
[^:]*: d54e879f sysp #6, C8, C7, #4
[^:]*: d54e97bf sysp #6, C9, C7, #5
[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3

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gas/testsuite/gas/aarch64/sysp-tlbip-optional.s Normal file
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.arch armv9.4-a+d128
/* TLBIP operands marked with the F_HASXT don not allow xzr to be used
as GPR arguments and so require at least one register to be specified. */
tlbip vale3nxs, x0
tlbip vale3nxs, x0, x1
tlbip vale3nxs, x2
tlbip vale3nxs, x2, x3
/* Conversely, those without the flag do not allow us to specify registers,
so the only accepted alternative is the complete omission of optional ops. */
tlbip paall
/* No such checking is carried out when the same instruction is issued
directly via the sysp implementation defined maintenance instruction,
such that both GRPs are optional. */
sysp #6, C9, C7, #5
sysp #6, C9, C7, #5, x0
sysp #6, C9, C7, #5, x0, x1
sysp #6, c9, c7, #5, x2
sysp #6, c9, c7, #5, x2, x3